From babdd7ce81f503a6971d47e8ade079a597fe9846 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Thu, 22 Feb 2024 14:13:49 +0800
Subject: [PATCH] apply transform

---
 data/registers/vrefbuf_v1.yaml | 20 --------------------
 transforms/VREFBUF.yaml        |  3 +++
 2 files changed, 3 insertions(+), 20 deletions(-)
 create mode 100644 transforms/VREFBUF.yaml

diff --git a/data/registers/vrefbuf_v1.yaml b/data/registers/vrefbuf_v1.yaml
index 45db2e4..b3ba308 100644
--- a/data/registers/vrefbuf_v1.yaml
+++ b/data/registers/vrefbuf_v1.yaml
@@ -23,7 +23,6 @@ fieldset/CSR:
     description: Voltage reference buffer mode enable.
     bit_offset: 0
     bit_size: 1
-    enum: ENVR
   - name: HIZ
     description: High impedance mode.
     bit_offset: 1
@@ -38,16 +37,6 @@ fieldset/CSR:
     description: Voltage reference buffer ready.
     bit_offset: 3
     bit_size: 1
-    enum: VRR
-enum/ENVR:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Internal voltage reference mode disable (external voltage reference mode).
-    value: 0
-  - name: Enabled
-    description: Internal voltage reference mode (reference buffer enable or hold mode) enable.
-    value: 1
 enum/HIZ:
   bit_size: 1
   variants:
@@ -57,15 +46,6 @@ enum/HIZ:
   - name: HighZ
     description: VREF+ pin is high impedance.
     value: 1
-enum/VRR:
-  bit_size: 1
-  variants:
-  - name: NotReady
-    description: The voltage reference buffer output is not ready.
-    value: 0
-  - name: Ready
-    description: The voltage reference buffer output reached the requested level.
-    value: 1
 enum/VRS:
   bit_size: 1
   variants:
diff --git a/transforms/VREFBUF.yaml b/transforms/VREFBUF.yaml
new file mode 100644
index 0000000..6f15143
--- /dev/null
+++ b/transforms/VREFBUF.yaml
@@ -0,0 +1,3 @@
+transforms:
+  - !DeleteEnums
+    from: ^(ENVR|VRR)$