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rcc: cleanup variants and rename ahb -> clk

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This commit is contained in:
xoviat 2023-10-15 18:01:50 -05:00
parent 8b8686a852
commit b9a89a1851
15 changed files with 162 additions and 130 deletions
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12
data/registers/rcc_c0.yaml
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@ -688,7 +688,7 @@ enum/ADCSEL:
- name: SYS
description: System clock
value: 0
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
enum/HPRE:
@ -778,13 +778,13 @@ enum/HSIKERDIV:
enum/I2C1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK
value: 0
- name: SYS
description: SYSCLK
value: 1
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
enum/I2S1SEL:
@ -793,7 +793,7 @@ enum/I2S1SEL:
- name: SYS
description: SYSCLK
value: 0
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
- name: I2S_CKIN
@ -949,13 +949,13 @@ enum/SYSDIV:
enum/USART1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK
value: 0
- name: SYS
description: SYSCLK
value: 1
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
- name: LSE

2
data/registers/rcc_f0.yaml
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@ -1057,7 +1057,7 @@ enum/SW:
enum/USARTSW:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK selected as USART clock source
value: 0
- name: SYS

4
data/registers/rcc_f3.yaml
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@ -1244,7 +1244,7 @@ enum/SW:
enum/TIMSW:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL
@ -1253,7 +1253,7 @@ enum/TIMSW:
enum/USARTSW:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK selected as USART clock source
value: 0
- name: SYS

4
data/registers/rcc_f3_v2.yaml
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@ -1220,7 +1220,7 @@ enum/SW:
enum/TIMSW:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL
@ -1229,7 +1229,7 @@ enum/TIMSW:
enum/USARTSW:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK selected as USART clock source
value: 0
- name: SYS

4
data/registers/rcc_f4.yaml
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@ -1766,7 +1766,7 @@ enum/CKDFSDMASEL:
enum/CKDFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: APB2 clock used as Kernel clock
value: 0
- name: SYSCLK
@ -1859,7 +1859,7 @@ enum/ISSRC:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI

2
data/registers/rcc_f410.yaml
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@ -849,7 +849,7 @@ enum/ISSRC:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI

8
data/registers/rcc_f7.yaml
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@ -1716,7 +1716,7 @@ enum/CKMSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source
value: 0
- name: SYSCLK
@ -1785,7 +1785,7 @@ enum/ISSRC:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI
@ -3159,7 +3159,7 @@ enum/TIMPRE:
enum/USART1SEL:
bit_size: 2
variants:
- name: APB2
- name: PCLK2
description: APB2 clock (PCLK2) is selected as USART clock
value: 0
- name: SYSCLK
@ -3174,7 +3174,7 @@ enum/USART1SEL:
enum/USART2SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) is selected as USART clock
value: 0
- name: SYSCLK

42
data/registers/rcc_g0.yaml
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@ -1182,7 +1182,7 @@ enum/ADCSEL:
- name: SYS
description: SYSCLK used as ADC clock source
value: 0
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK used as ADC clock source
value: 1
- name: HSI
@ -1200,10 +1200,10 @@ enum/CECSEL:
enum/FDCANSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as FDCAN clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as FDCAN clock source
value: 1
- name: HSE
@ -1269,7 +1269,7 @@ enum/HSIDIV:
enum/I2C1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as I2C1 clock source
value: 0
- name: SYS
@ -1281,7 +1281,7 @@ enum/I2C1SEL:
enum/I2C2I2S1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as I2C2/I2S2 clock source
value: 0
- name: SYS
@ -1299,7 +1299,7 @@ enum/I2S1SEL:
- name: SYS
description: SYSCLK used as I2S1 clock source
value: 0
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK used as I2S1 clock source
value: 1
- name: HSI
@ -1314,7 +1314,7 @@ enum/I2S2SEL:
- name: SYS
description: SYSCLK used as I2S2 clock source
value: 0
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK used as I2S2 clock source
value: 1
- name: HSI
@ -1326,7 +1326,7 @@ enum/I2S2SEL:
enum/LPTIM1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as LPTIM1 clock source
value: 0
- name: LSI
@ -1341,7 +1341,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as LPTIM2 clock source
value: 0
- name: LSI
@ -1356,7 +1356,7 @@ enum/LPTIM2SEL:
enum/LPUART1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as LPUART1 clock source
value: 0
- name: SYS
@ -1371,7 +1371,7 @@ enum/LPUART1SEL:
enum/LPUART2SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as LPUART2 clock source
value: 0
- name: SYS
@ -1461,10 +1461,10 @@ enum/MCOSEL:
- name: LSE
description: LSE selected as MCO source
value: 7
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK selected as MCO source
value: 8
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK selected as MCO source
value: 9
- name: RTCCLK
@ -1809,7 +1809,7 @@ enum/RNGSEL:
- name: SYS
description: SYSCLK used as RNG clock source
value: 2
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as RNG clock source
value: 3
enum/RTCSEL:
@ -1836,7 +1836,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 1
- name: PLLRCLK
- name: PLL1_R
description: PLLRCLK selected as system clock
value: 2
- name: LSI
@ -1851,7 +1851,7 @@ enum/TIM15SEL:
- name: TIMPCLK
description: TIMPCLK used as TIM15 clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as TIM15 clock source
value: 1
enum/TIM1SEL:
@ -1860,13 +1860,13 @@ enum/TIM1SEL:
- name: TIMPCLK
description: TIMPCLK used as TIM1 clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as TIM1 clock source
value: 1
enum/USART1SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as USART1 clock source
value: 0
- name: SYS
@ -1881,7 +1881,7 @@ enum/USART1SEL:
enum/USART2SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as USART2 clock source
value: 0
- name: SYS
@ -1896,7 +1896,7 @@ enum/USART2SEL:
enum/USART3SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: PCLK used as USART3 clock source
value: 0
- name: SYS
@ -1914,7 +1914,7 @@ enum/USBSEL:
- name: HSI48
description: HSI48 used as USB clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as USB clock source
value: 1
- name: HSE

4
data/registers/rcc_g4.yaml
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@ -1358,7 +1358,7 @@ enum/CLK48SEL:
- name: HSI48
description: HSI48 oscillator clock selected as 48 MHz clock
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK selected as 48 MHz clock
value: 2
enum/HPRE:
@ -1875,6 +1875,6 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLLRCLK
- name: PLL1_R
description: PLLRCLK selected as system clock
value: 3

24
data/registers/rcc_h5.yaml
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@ -2125,7 +2125,7 @@ fieldset/SECCFGR:
enum/ADCDACSEL:
bit_size: 3
variants:
- name: AHB1
- name: HCLK1
description: rcc_hclk selected as kernel clock (default after reset)
value: 0
- name: SYS
@ -2245,7 +2245,7 @@ enum/HSIDIV:
enum/ICSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -2260,7 +2260,7 @@ enum/ICSEL:
enum/LPTIMSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as peripheral clock
value: 0
- name: PLL2_P
@ -2281,7 +2281,7 @@ enum/LPTIMSEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -2431,7 +2431,7 @@ enum/NSPRIV:
enum/OCTOSPISEL:
bit_size: 2
variants:
- name: AHB4
- name: HCLK4
description: rcc_hclk4 selected as kernel clock (default after reset)
value: 0
- name: PLL1_Q
@ -4030,7 +4030,7 @@ enum/SPI3SEL:
enum/SPI4SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -4051,7 +4051,7 @@ enum/SPI4SEL:
enum/SPI5SEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -4072,7 +4072,7 @@ enum/SPI5SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4126,13 +4126,13 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SYSTICKSEL:
bit_size: 2
variants:
- name: AHB1_DIV_8
- name: HCLK1_DIV_8
description: rcc_hclk/8 selected as clock source (default after reset)
value: 0
- name: LSI
@ -4162,7 +4162,7 @@ enum/TIMPRE:
enum/UARTSEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4183,7 +4183,7 @@ enum/UARTSEL:
enum/USARTSEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q

14
data/registers/rcc_h50.yaml
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@ -1335,7 +1335,7 @@ fieldset/RSR:
enum/ADCDACSEL:
bit_size: 3
variants:
- name: AHB1
- name: HCLK1
description: rcc_hclk selected as kernel clock (default after reset)
value: 0
- name: SYS
@ -1443,7 +1443,7 @@ enum/HSIDIV:
enum/ICSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -1458,7 +1458,7 @@ enum/ICSEL:
enum/LPTIMSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as peripheral clock
value: 0
- name: PLL2_P
@ -1476,7 +1476,7 @@ enum/LPTIMSEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -3108,7 +3108,7 @@ enum/RTCSEL:
enum/SPISEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -3147,7 +3147,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SYSTICKSEL:
@ -3183,7 +3183,7 @@ enum/TIMPRE:
enum/USARTSEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q

20
data/registers/rcc_h7.yaml
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@ -3535,7 +3535,7 @@ enum/CKPERSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: SYS
@ -3556,7 +3556,7 @@ enum/FDCANSEL:
enum/FMCSEL:
bit_size: 2
variants:
- name: AHB3
- name: HCLK3
description: AHB3 selected as peripheral clock
value: 0
- name: PLL1_Q
@ -3625,7 +3625,7 @@ enum/HSIDIV:
enum/I2C1235SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3640,7 +3640,7 @@ enum/I2C1235SEL:
enum/I2C4SEL:
bit_size: 2
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3655,7 +3655,7 @@ enum/I2C4SEL:
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
@ -3676,7 +3676,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
@ -5395,7 +5395,7 @@ enum/SPI45SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5434,7 +5434,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SWPSEL:
@ -5458,7 +5458,7 @@ enum/TIMPRE:
enum/USART16910SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5479,7 +5479,7 @@ enum/USART16910SEL:
enum/USART234578SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q

20
data/registers/rcc_h7ab.yaml
View File

@ -2470,7 +2470,7 @@ enum/CKPERSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: SYS
@ -2491,7 +2491,7 @@ enum/FDCANSEL:
enum/FMCSEL:
bit_size: 2
variants:
- name: AHB3
- name: HCLK3
description: rcc_hclk3 selected as peripheral clock
value: 0
- name: PLL1_Q
@ -2560,7 +2560,7 @@ enum/HSIDIV:
enum/I2C1235SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -2575,7 +2575,7 @@ enum/I2C1235SEL:
enum/I2C4SEL:
bit_size: 2
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL3_R
@ -2590,7 +2590,7 @@ enum/I2C4SEL:
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
@ -2611,7 +2611,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
@ -4330,7 +4330,7 @@ enum/SPI45SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4369,7 +4369,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SWPSEL:
@ -4393,7 +4393,7 @@ enum/TIMPRE:
enum/USART16910SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4414,7 +4414,7 @@ enum/USART16910SEL:
enum/USART234578SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q

20
data/registers/rcc_h7rm0433.yaml
View File

@ -3535,7 +3535,7 @@ enum/CKPERSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: SYS
@ -3556,7 +3556,7 @@ enum/FDCANSEL:
enum/FMCSEL:
bit_size: 2
variants:
- name: AHB3
- name: HCLK3
description: rcc_hclk3 selected as peripheral clock
value: 0
- name: PLL1_Q
@ -3625,7 +3625,7 @@ enum/HSIDIV:
enum/I2C1235SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3640,7 +3640,7 @@ enum/I2C1235SEL:
enum/I2C4SEL:
bit_size: 2
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3655,7 +3655,7 @@ enum/I2C4SEL:
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
@ -3676,7 +3676,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
@ -5395,7 +5395,7 @@ enum/SPI45SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5434,7 +5434,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SWPSEL:
@ -5458,7 +5458,7 @@ enum/TIMPRE:
enum/USART16910SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5479,7 +5479,7 @@ enum/USART16910SEL:
enum/USART234578SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q

98
stm32-data-gen/src/rcc.rs
View File

@ -15,48 +15,80 @@ pub struct PeripheralToClock(
impl PeripheralToClock {
pub fn parse(registers: &Registers) -> anyhow::Result<Self> {
let mut peripheral_to_clock = HashMap::new();
for (rcc_name, ir) in &registers.registers {
if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
let checked_rccs = HashSet::from([
"c0", "f0", "f1", "f100", "f1c1", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7",
"h7ab", "h7rm0433",
"c0", "f0", "f1", "f100", "f1c1", "f3", "f3_v2", "f7", "g0", "g4", "h5", "h50", "h7", "h7ab", "h7rm0433",
]);
let prohibited_variants = HashSet::from([
"APB",
"AHB",
"PCLK",
let allowed_variants = HashSet::from([
"DISABLE",
"SYS",
"PCLK1",
"PCLK1_TIM",
"PCLK2",
"PCLK2_TIM",
"PCLK3",
"PCLK4",
"RCC_PCLK1",
"RCC_PCLK2",
"RCC_PCLK3",
"RCC_PCLK4",
"HSI_KER",
"HSI48_KER",
"CSI_KER",
"LSI_KER",
"PER_CLK",
"HCLK",
"PCLK5",
"PCLK6",
"PCLK7",
"HCLK1",
"HCLK2",
"HCLK3",
"HCLK4",
"RCC_HCLK1",
"RCC_HCLK2",
"RCC_HCLK3",
"RCC_HCLK4",
"PLL3_1",
"NOCLK",
"NoMCO",
"NoClock",
"PLLP",
"PLLQ",
"PLLR",
"SYSCLK",
"HSI16",
"HCLK5",
"HCLK6",
"HCLK7",
"PLLI2S1_P",
"PLLI2S1_Q",
"PLLI2S1_R",
"PLLI2S2_P",
"PLLI2S2_Q",
"PLLI2S2_R",
"PLLSAI1_P",
"PLLSAI1_Q",
"PLLSAI1_R",
"PLLSAI2_P",
"PLLSAI2_Q",
"PLLSAI2_R",
"PLL1_P",
"PLL1_Q",
"PLL1_R",
"PLL2_P",
"PLL2_Q",
"PLL2_R",
"PLL3_P",
"PLL3_Q",
"PLL3_R",
"HSI",
"HSI48",
"LSI",
"CSI",
"HSE",
"LSE",
"AUDIOCLK",
"PER",
// TODO: variants to cleanup
"B_0x0",
"B_0x1",
"PLL",
"PLLCLK",
"TIMPCLK",
"HSI_Div244",
"CSI_DIV_122",
"HSI16_Div488",
"HSI16_Div8",
"HCLK_DIV_8",
"HCLK1_DIV_8",
"RCC_PCLK_D3",
"I2S_CKIN",
"DAC_HOLD",
"DAC_HOLD_2",
"TIMPCLK",
"RTCCLK",
"RTC_WKUP",
]);
for (rcc_name, ir) in &registers.registers {
if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = {
let rcc_blocks = &ir.blocks.get("RCC").unwrap().items;
@ -99,7 +131,7 @@ impl PeripheralToClock {
};
for v in &enumm.variants {
if prohibited_variants.contains(v.name.as_str()) {
if !allowed_variants.contains(v.name.as_str()) {
return Err(anyhow!(
"rcc: prohibited variant name {} for rcc_{}",
v.name.as_str(),