diff --git a/.vscode/settings.json b/.vscode/settings.json index ac189e5..ee57673 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -3,4 +3,10 @@ "[toml]": { "editor.formatOnSave": false }, + "[c]": { + "editor.formatOnSave": false + }, + "[cpp]": { + "editor.formatOnSave": false + }, } \ No newline at end of file diff --git a/Cargo.lock b/Cargo.lock index af26291..be1e011 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -53,7 +53,7 @@ source = "git+https://github.com/embassy-rs/chiptool?rev=1d9e0a39a6acc291e50cabc dependencies = [ "anyhow", "clap", - "env_logger", + "env_logger 0.9.3", "inflections", "log", "proc-macro2", @@ -71,7 +71,7 @@ source = "git+https://github.com/embassy-rs/chiptool#150ce4a3442001ef73e0c0f2924 dependencies = [ "anyhow", "clap", - "env_logger", + "env_logger 0.9.3", "inflections", "log", "proc-macro2", @@ -170,6 +170,19 @@ version = "1.8.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "7fcaabb2fef8c910e7f4c7ce9f67a1283a1715879a7c230ca9d6d1ae31f16d91" +[[package]] +name = "env_logger" +version = "0.7.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "44533bbbb3bb3c1fa17d9f2e4e38bbbaf8396ba82193c4cb1b6445d711445d36" +dependencies = [ + "atty", + "humantime 1.3.0", + "log", + "regex", + "termcolor", +] + [[package]] name = "env_logger" version = "0.9.3" @@ -177,7 +190,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "a12e6657c4c97ebab115a42dcee77225f7f482cdd841cf7088c657a42e9e00e7" dependencies = [ "atty", - "humantime", + "humantime 2.1.0", "log", "regex", "termcolor", @@ -219,6 +232,15 @@ dependencies = [ "libc", ] +[[package]] +name = "humantime" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "df004cfca50ef23c36850aaaa59ad52cc70d0e90243c3c7737a4dd32dc7a3c4f" +dependencies = [ + "quick-error", +] + [[package]] name = "humantime" version = "2.1.0" @@ -390,6 +412,16 @@ version = "6.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "ceedf44fb00f2d1984b0bc98102627ce622e083e49a5bacdb3e514fa4238e267" +[[package]] +name = "pretty_env_logger" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "926d36b9553851b8b0005f1275891b392ee4d2d833852c417ed025477350fb9d" +dependencies = [ + "env_logger 0.7.1", + "log", +] + [[package]] name = "proc-macro-error" version = "1.0.4" @@ -423,6 +455,12 @@ dependencies = [ "unicode-ident", ] +[[package]] +name = "quick-error" +version = "1.2.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a1d01941d82fa2ab50be1e79e6714289dd7cde78eba4c074bc5a4374f650dfe0" + [[package]] name = "quick-xml" version = "0.26.0" @@ -562,7 +600,9 @@ dependencies = [ "anyhow", "chiptool 0.1.0 (git+https://github.com/embassy-rs/chiptool?rev=1d9e0a39a6acc291e50cabc4ed617a87f06d5e89)", "glob", + "log", "num", + "pretty_env_logger", "quick-xml", "rayon", "ref_thread_local", diff --git a/d b/d index 51222b6..acb155e 100755 --- a/d +++ b/d @@ -10,9 +10,8 @@ case "$CMD" in download-all) rm -rf ./sources/ git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/ - # The following is a temporary workaround until https://github.com/embassy-rs/stm32-data/pull/175 is merged. cd ./sources/ - git checkout 3d60b46 + git checkout ca89656b ;; install-chiptool) cargo install --git https://github.com/embassy-rs/chiptool @@ -40,7 +39,7 @@ case "$CMD" in ;; ci) [ -d sources ] || ./d download-all - rm -rf build + rm -rf build/{data,stm32-metapac} cargo run --release --bin stm32-data-gen cargo run --release --bin stm32-metapac-gen (cd build/stm32-metapac && cargo check --features stm32h755zi-cm7,pac,metadata) diff --git a/data/dmamux/H5_GPDMA.yaml b/data/dmamux/H5_GPDMA.yaml new file mode 100644 index 0000000..cf24679 --- /dev/null +++ b/data/dmamux/H5_GPDMA.yaml @@ -0,0 +1,133 @@ +ADC1: 0 +ADC2: 1 +DAC1_CH1: 2 +DAC1_CH2: 3 +TIM6_UPD: 4 +TIM7_UPD: 5 +SPI1_RX: 6 +SPI1_TX: 7 +SPI2_RX: 8 +SPI2_TX: 9 +SPI3_RX: 10 +SPI3_TX: 11 +I2C1_RX: 12 +I2C1_TX: 13 +I2C2_RX: 15 +I2C2_TX: 16 +I2C3_RX: 18 +I2C3_TX: 19 +USART1_RX: 21 +USART1_TX: 22 +USART2_RX: 23 +USART2_TX: 24 +USART3_RX: 25 +USART3_TX: 26 +UART4_RX: 27 +UART4_TX: 28 +UART5_RX: 29 +UART5_TX: 30 +USART6_RX: 31 +USART6_TX: 32 +UART7_RX: 33 +UART7_TX: 34 +UART8_RX: 35 +UART8_TX: 36 +UART9_RX: 37 +UART9_TX: 38 +UART10_RX: 39 +UART10_TX: 40 +UART11_RX: 41 +UART11_TX: 42 +UART12_RX: 43 +UART12_TX: 44 +LPUART1_RX: 45 +LPUART1_TX: 46 +SPI4_RX: 47 +SPI4_TX: 48 +SPI5_RX: 49 +SPI5_TX: 50 +SPI6_RX: 51 +SPI6_TX: 52 +SAI1_A: 53 +SAI1_B: 54 +SAI2_A: 55 +SAI2_B: 56 +OSPI1: 57 +TIM1_CC1: 58 +TIM1_CC2: 59 +TIM1_CC3: 60 +TIM1_CC4: 61 +TIM1_UPD: 62 +TIM1_TRG: 63 +TIM1_COM: 64 +TIM8_CC1: 65 +TIM8_CC2: 66 +TIM8_CC3: 67 +TIM8_CC4: 68 +TIM8_UPD: 69 +TIM8_TIG: 70 +TIM8_COM: 71 +TIM2_CC1: 72 +TIM2_CC2: 73 +TIM2_CC3: 74 +TIM2_CC4: 75 +TIM2_UPD: 76 +TIM3_CC1: 77 +TIM3_CC2: 78 +TIM3_CC3: 79 +TIM3_CC4: 80 +TIM3_UPD: 81 +TIM3_TRG: 82 +TIM4_CC1: 83 +TIM4_CC2: 84 +TIM4_CC3: 85 +TIM4_CC4: 86 +TIM4_UPD: 87 +TIM5_CC1: 88 +TIM5_CC2: 89 +TIM5_CC3: 90 +TIM5_CC4: 91 +TIM5_UPD: 92 +TIM5_TRG: 93 +TIM15_CC1: 94 +TIM15_UPD: 95 +TIM15_TRG: 96 +TIM15_COM: 97 +TIM16_CC1: 98 +TIM16_UPD: 99 +TIM17_CC1: 100 +TIM17_UPD: 101 +LPTIM1_IC1: 102 +LPTIM1_IC2: 103 +LPTIM1_UE: 104 +LPTIM2_IC1: 105 +LPTIM2_IC2: 106 +LPTIM2_UE: 107 +DCMI: 108 +AES_OUT: 109 +AES_IN: 110 +HASH_IN: 111 +UCPD1_RX: 112 +UCPD1_TX: 113 +CORDIC_READ: 114 +CORDIC_WRITE: 115 +FMAC_READ: 116 +FMAC_WRITE: 117 +SAES_OUT: 118 +SAES_IN: 119 +I3C1_RX: 120 +I3C1_TX: 121 +I3C1_TC: 122 +I3C1_RS: 123 +I2C4_RX: 124 +I2C4_TX: 125 +RESE: 126 +LPTIM3_IC1: 127 +LPTIM3_IC2: 128 +LPTIM3_UE: 129 +LPTIM5_IC1: 130 +LPTIM5_IC2: 131 +LPTIM5_UE: 132 +LPTIM6_IC1: 133 +LPTIM6_IC2: 134 +LPTIM6_UE: 135 \ No newline at end of file diff --git a/data/registers/flash_h5.yaml b/data/registers/flash_h5.yaml new file mode 100644 index 0000000..06ac0e0 --- /dev/null +++ b/data/registers/flash_h5.yaml @@ -0,0 +1,1280 @@ +--- +block/FLASH: + description: FLASH address block description + items: + - name: ACR + description: FLASH access control register + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: FLASH non-secure key register + byte_offset: 4 + fieldset: NSKEYR + - name: SECKEYR + description: FLASH secure key register + byte_offset: 8 + fieldset: SECKEYR + - name: OPTKEYR + description: FLASH option key register + byte_offset: 12 + fieldset: OPTKEYR + - name: NSOBKKEYR + description: FLASH non-secure OBK key register + byte_offset: 16 + fieldset: NSOBKKEYR + - name: SECOBKKEYR + description: FLASH secure OBK key register + byte_offset: 20 + fieldset: SECOBKKEYR + - name: OPSR + description: FLASH operation status register + byte_offset: 24 + fieldset: OPSR + - name: OPTCR + description: FLASH option control register + byte_offset: 28 + fieldset: OPTCR + - name: NSSR + description: FLASH non-secure status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: FLASH secure status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: FLASH non-secure control register + byte_offset: 40 + fieldset: NSCR + - name: SECCR + description: FLASH secure control register + byte_offset: 44 + fieldset: SECCR + - name: NSCCR + description: FLASH non-secure clear control register + byte_offset: 48 + fieldset: NSCCR + - name: SECCCR + description: FLASH secure clear control register + byte_offset: 52 + fieldset: SECCCR + - name: PRIVCFGR + description: FLASH privilege configuration register + byte_offset: 60 + fieldset: PRIVCFGR + - name: NSOBKCFGR + description: FLASH non-secure OBK configuration register + byte_offset: 64 + fieldset: NSOBKCFGR + - name: SECOBKCFGR + description: FLASH secure OBK configuration register + byte_offset: 68 + fieldset: SECOBKCFGR + - name: HDPEXTR + description: FLASH HDP extension register + byte_offset: 72 + fieldset: HDPEXTR + - name: OPTSR_CUR + description: FLASH option status register + byte_offset: 80 + fieldset: OPTSR + - name: OPTSR_PRG + description: FLASH option status register + byte_offset: 84 + fieldset: OPTSR + - name: NSEPOCHR_CUR + description: FLASH non-secure EPOCH register + byte_offset: 96 + fieldset: NSEPOCHR + - name: SECEPOCHR_CUR + description: FLASH secure EPOCH register + byte_offset: 104 + fieldset: SECEPOCHR + - name: OPTSR2_CUR + description: FLASH option status register 2 + byte_offset: 112 + fieldset: OPTSR2 + - name: OPTSR2_PRG + description: FLASH option status register 2 + byte_offset: 116 + fieldset: OPTSR2 + - name: NSBOOTR_CUR + description: FLASH non-secure boot register + byte_offset: 128 + fieldset: NSBOOTR + - name: NSBOOTR_PRG + description: FLASH non-secure boot register + byte_offset: 132 + fieldset: NSBOOTR + - name: SECBOOTR_CUR + description: FLASH secure boot register + byte_offset: 136 + fieldset: SECBOOTR + - name: BOOTR_PRG + description: FLASH secure boot register + byte_offset: 140 + fieldset: BOOTR + - name: OTPBLR_CUR + description: FLASH non-secure OTP block lock + byte_offset: 144 + fieldset: OTPBLR + - name: OTPBLR_PRG + description: FLASH non-secure OTP block lock + byte_offset: 148 + fieldset: OTPBLR + - name: SECBB1R1 + description: FLASH secure block based register for Bank 1 + byte_offset: 160 + fieldset: SECBB + - name: SECBB1R2 + description: FLASH secure block based register for Bank 1 + byte_offset: 164 + fieldset: SECBB + - name: SECBB1R3 + description: FLASH secure block based register for Bank 1 + byte_offset: 168 + fieldset: SECBB + - name: SECBB1R4 + description: FLASH secure block based register for Bank 1 + byte_offset: 172 + fieldset: SECBB + - name: PRIVBB1R1 + description: FLASH privilege block based register for Bank 1 + byte_offset: 192 + fieldset: PRIVBB + - name: PRIVBB1R2 + description: FLASH privilege block based register for Bank 1 + byte_offset: 196 + fieldset: PRIVBB + - name: PRIVBB1R3 + description: FLASH privilege block based register for Bank 1 + byte_offset: 200 + fieldset: PRIVBB + - name: PRIVBB1R4 + description: FLASH privilege block based register for Bank 1 + byte_offset: 204 + fieldset: PRIVBB + - name: SECWM1R_CUR + description: FLASH security watermark for Bank 1 + byte_offset: 224 + fieldset: SECWM + - name: SECWM1R_PRG + description: FLASH security watermark for Bank 1 + byte_offset: 228 + fieldset: SECWM + - name: WRP1R_CUR + description: FLASH write sector group protection for Bank 1 + byte_offset: 232 + fieldset: WRP + - name: WRP1R_PRG + description: FLASH write sector group protection for Bank 1 + byte_offset: 236 + fieldset: WRP + - name: EDATA1R_CUR + description: FLASH data sector configuration Bank 1 + byte_offset: 240 + fieldset: EDATA1R + - name: EDATA1R_PRG + description: FLASH data sector configuration Bank 1 + byte_offset: 244 + fieldset: EDATA1R + - name: HDP1R_CUR + description: FLASH HDP Bank 1 configuration + byte_offset: 248 + fieldset: HDP1R + - name: HDP1R_PRG + description: FLASH HDP Bank 1 configuration + byte_offset: 252 + fieldset: HDP1R + - name: ECCCORR + description: FLASH ECC correction register + byte_offset: 256 + fieldset: ECCCORR + - name: ECCDETR + description: FLASH ECC detection register + byte_offset: 260 + fieldset: ECCDETR + - name: ECCDR + description: FLASH ECC data + byte_offset: 264 + fieldset: ECCDR + - name: SECBB2R1 + description: FLASH secure block-based register for Bank 2 + byte_offset: 416 + fieldset: SECBB + - name: SECBB2R2 + description: FLASH secure block-based register for Bank 2 + byte_offset: 420 + fieldset: SECBB + - name: SECBB2R3 + description: FLASH secure block-based register for Bank 2 + byte_offset: 424 + fieldset: SECBB + - name: SECBB2R4 + description: FLASH secure block-based register for Bank 2 + byte_offset: 428 + fieldset: SECBB + - name: PRIVBB2R1 + description: FLASH privilege block-based register for Bank 2 + byte_offset: 448 + fieldset: PRIVBB + - name: PRIVBB2R2 + description: FLASH privilege block-based register for Bank 2 + byte_offset: 452 + fieldset: PRIVBB + - name: PRIVBB2R3 + description: FLASH privilege block-based register for Bank 2 + byte_offset: 456 + fieldset: PRIVBB + - name: PRIVBB2R4 + description: FLASH privilege block-based register for Bank 2 + byte_offset: 460 + fieldset: PRIVBB + - name: SECWM2R_CUR + description: FLASH security watermark for Bank 2 + byte_offset: 480 + fieldset: SECWM + - name: SECWM2R_PRG + description: FLASH security watermark for Bank 2 + byte_offset: 484 + fieldset: SECWM + - name: WRP2R_CUR + description: FLASH write sector group protection for Bank 2 + byte_offset: 488 + fieldset: WRP + - name: WRP2R_PRG + description: FLASH write sector group protection for Bank 2 + byte_offset: 492 + fieldset: WRP + - name: EDATA2R_CUR + description: FLASH data sectors configuration Bank 2 + byte_offset: 496 + fieldset: EDATA2R + - name: EDATA2R_PRG + description: FLASH data sector configuration Bank 2 + byte_offset: 500 + fieldset: EDATA2R + - name: HDP2R_CUR + description: FLASH HDP Bank 2 configuration + byte_offset: 504 + fieldset: HDP2R + - name: HDP2R_PRG + description: FLASH HDP Bank 2 configuration + byte_offset: 508 + fieldset: HDP2R +fieldset/ACR: + description: FLASH access control register + fields: + - name: LATENCY + description: "Read latency\r These bits are used to control the number of wait states used during read operations on both nonvolatile memory banks. The application software has to program them to the correct value depending on the embedded flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct." + bit_offset: 0 + bit_size: 4 + - name: WRHIGHFREQ + description: "Flash signal delay \r These bits are used to control the delay between nonvolatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded flash memory interface frequency. Please refer to Table�44 for details.\r Note: No check is performed to verify that the configuration is correct. \r Note: Two WRHIGHFREQ values can be selected for some frequencies." + bit_offset: 4 + bit_size: 2 + - name: PRFTEN + description: "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account.\r Bits used to control the prefetch." + bit_offset: 8 + bit_size: 1 +fieldset/BOOTR: + description: FLASH secure boot register + fields: + - name: SECBOOT_LOCK + description: "A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting." + bit_offset: 0 + bit_size: 8 + enum: BOOTR_SECBOOT_LOCK + - name: SECBOOTADD + description: "Secure unique boot entry address.\r These bits allow configuring the secure UBE address." + bit_offset: 8 + bit_size: 24 +fieldset/ECCCORR: + description: FLASH ECC correction register + fields: + - name: ADDR_ECC + description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. \r ADDR_ECC is reset when the flag error is reset. \r The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area)." + bit_offset: 0 + bit_size: 16 + - name: OBK_ECC + description: Single ECC error corrected in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. + bit_offset: 20 + bit_size: 1 + - name: EDATA_ECC + description: "ECC fail for corrected ECC error in flash high-cycle data area\r It indicates if flash high-cycle data area is concerned by ECC error." + bit_offset: 21 + bit_size: 1 + - name: BK_ECC + description: "ECC fail bank for corrected ECC error\r It indicates which bank is concerned by ECC error" + bit_offset: 22 + bit_size: 1 + - name: SYSF_ECC + description: "ECC fail for corrected ECC error in system flash memory\r It indicates if system flash memory is concerned by ECC error." + bit_offset: 23 + bit_size: 1 + - name: OTP_ECC + description: "OTP ECC error bit\r This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield." + bit_offset: 24 + bit_size: 1 + - name: ECCCIE + description: "ECC single correction error interrupt enable bit\r When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation." + bit_offset: 25 + bit_size: 1 + - name: ECCC + description: "ECC correction set by hardware when single ECC error has been detected and corrected.\r Cleared by writing 1." + bit_offset: 30 + bit_size: 1 +fieldset/ECCDETR: + description: FLASH ECC detection register + fields: + - name: ADDR_ECC + description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. \r ADDR_ECC is reset when the flag error is reset. \r The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area)." + bit_offset: 0 + bit_size: 16 + - name: OBK_ECC + description: ECC fail double ECC error in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. + bit_offset: 20 + bit_size: 1 + - name: EDATA_ECC + description: "ECC fail double ECC error in flash high-cycle data area\r It indicates if flash high-cycle data area is concerned by ECC error." + bit_offset: 21 + bit_size: 1 + - name: BK_ECC + description: "ECC fail bank for double ECC error\r It indicates which bank is concerned by ECC error" + bit_offset: 22 + bit_size: 1 + - name: SYSF_ECC + description: "ECC fail for double ECC error in system flash memory\r It indicates if system flash memory is concerned by ECC error." + bit_offset: 23 + bit_size: 1 + - name: OTP_ECC + description: "OTP ECC error bit\r This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield." + bit_offset: 24 + bit_size: 1 + - name: ECCD + description: "ECC detection\r Set by hardware when two ECC error has been detected.\r When this bit is set, a NMI is generated.\r Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors." + bit_offset: 31 + bit_size: 1 +fieldset/ECCDR: + description: FLASH ECC data + fields: + - name: DATA_ECC + description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory." + bit_offset: 0 + bit_size: 16 +fieldset/EDATA1R: + description: FLASH data sector configuration Bank 1 + fields: + - name: EDATA1_STRT + description: "EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank 1 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher.\r ...\r Note: 111: The eight last sectors of the Bank 1 are reserved for flash high-cycle data" + bit_offset: 0 + bit_size: 3 + - name: EDATA1_EN + description: Bank 1 flash high-cycle data enable + bit_offset: 15 + bit_size: 1 +fieldset/EDATA2R: + description: FLASH data sector configuration Bank 2 + fields: + - name: EDATA2_STRT + description: "EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank 2 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher.\r ...\r Note: 111: The eight last sectors of the Bank 2 are reserved for flash high-cycle data." + bit_offset: 0 + bit_size: 3 + - name: EDATA2_EN + description: Bank 2 flash high-cycle data enable + bit_offset: 15 + bit_size: 1 +fieldset/HDP1R: + description: FLASH HDP Bank 1 configuration + fields: + - name: HDP1_STRT + description: HDPL barrier start set in number of 8-Kbyte sectors + bit_offset: 0 + bit_size: 7 + - name: HDP1_END + description: HDPL barrier end set in number of 8-Kbyte sectors + bit_offset: 16 + bit_size: 7 +fieldset/HDP2R: + description: FLASH HDP Bank 2 configuration + fields: + - name: HDP2_STRT + description: HDPL barrier start set in number of 8-Kbyte sectors + bit_offset: 0 + bit_size: 7 + - name: HDP2_END + description: HDPL barrier end set in number of 8-Kbyte sectors + bit_offset: 16 + bit_size: 7 +fieldset/HDPEXTR: + description: FLASH HDP extension register + fields: + - name: HDP1_EXT + description: HDP area extension in 8�Kbytes sectors in Bank1. Extension is added after the HDP1_END sector (included). + bit_offset: 0 + bit_size: 7 + - name: HDP2_EXT + description: HDP area extension in 8�Kbytes sectors in bank 2. Extension is added after the HDP2_END sector (included). + bit_offset: 16 + bit_size: 7 +fieldset/NSBOOTR: + description: FLASH non-secure boot register + fields: + - name: NSBOOT_LOCK + description: "A field locking the values of SWAP_ BANK, and NSBOOTADD settings." + bit_offset: 0 + bit_size: 8 + enum: NSBOOTR_NSBOOT_LOCK + - name: NSBOOTADD + description: "Non secure unique boot entry address \r These bits allow configuring the Non secure BOOT address" + bit_offset: 8 + bit_size: 24 +fieldset/NSCCR: + description: FLASH non-secure clear control register + fields: + - name: CLR_EOP + description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register." + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register." + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register." + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register." + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register." + bit_offset: 20 + bit_size: 1 + - name: CLR_OBKERR + description: "OBKERR flag clear bit.\r Setting this bit to 1 resets to 0 OBKERR flag in FLASH_NSSR register." + bit_offset: 21 + bit_size: 1 + - name: CLR_OBKWERR + description: "OBKWERR flag clear bit.\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_NSSR register." + bit_offset: 22 + bit_size: 1 + - name: CLR_OPTCHANGEERR + description: Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + bit_offset: 23 + bit_size: 1 +fieldset/NSCR: + description: FLASH non-secure control register + fields: + - name: LOCK + description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. \r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: PG + description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0. \r PG allows programming in Bank1 and Bank2." + bit_offset: 1 + bit_size: 1 + - name: SER + description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised." + bit_offset: 2 + bit_size: 1 + - name: BER + description: "erase request\r Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." + bit_offset: 3 + bit_size: 1 + - name: FW + description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. \r The embedded flash memory resets FW when the corresponding operation has been acknowledged. \r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty and was filled by non-secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). \r Since there is just one write buffer, FW can force a write in bank1 or bank2." + bit_offset: 4 + bit_size: 1 + - name: STRT + description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. \r STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software." + bit_offset: 5 + bit_size: 1 + - name: SNB + description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r .." + bit_offset: 6 + bit_size: 7 + - name: MER + description: "Mass erase request\r Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. \r If BER or SER are both set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0." + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: "write protection error interrupt enable bit\r When this bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: "programming sequence error interrupt enable bit\r When this bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 20 + bit_size: 1 + - name: OBKERRIE + description: "OBK general error interrupt enable bit\r OBKERRIE enables generating an interrupt in case of OBK specific access error. This bit can be programmed only when LOCK bit is cleared to 0." + bit_offset: 21 + bit_size: 1 + - name: OBKWERRIE + description: "OBK write error interrupt enable bit\r OBKWERRIE enables generation of interrupt in case of OBK specific write error. This bit can be programmed only when LOCK bit is cleared to 0." + bit_offset: 22 + bit_size: 1 + - name: OPTCHANGEERRIE + description: "Option byte change error interrupt enable bit\r This bit controls if an interrupt must be generated when an error occurs during an option byte change. It can be programmed only when LOCK bit is cleared to 0." + bit_offset: 23 + bit_size: 1 + - name: BKSEL + description: "Bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." + bit_offset: 31 + bit_size: 1 + enum: NSCR_BKSEL +fieldset/NSEPOCHR: + description: FLASH non-secure EPOCH register + fields: + - name: NS_EPOCH + description: Non-volatile non-secure EPOCH counter + bit_offset: 0 + bit_size: 24 +fieldset/NSKEYR: + description: FLASH non-secure key register + fields: + - name: NSKEY + description: Non-volatile memory non-secure configuration access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/NSOBKCFGR: + description: FLASH non-secure OBK configuration register + fields: + - name: LOCK + description: "OBKCFGR lock option configuration bit\r This bit locks the FLASH_NSOBKCFGR register. The correct write sequence to FLASH_NSOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: SWAP_SECT_REQ + description: "OBK swap sector request bit\r When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one.\r The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3." + bit_offset: 1 + bit_size: 1 + - name: ALT_SECT + description: "alternate sector bit\r This bit must not change while filling the write buffer, otherwise an error (OBKERR) is generated" + bit_offset: 2 + bit_size: 1 + - name: ALT_SECT_ERASE + description: "alternate sector erase bit\r When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as BUSY bit." + bit_offset: 3 + bit_size: 1 + - name: SWAP_OFFSET + description: "Key index (offset /16 bits) pointing for next swap.\r 0x01 means that only the first OBK data (128 bits) is copied from current to alternate OBK sector\r 0x02 means that the two first OBK data is copied …\r …" + bit_offset: 16 + bit_size: 9 +fieldset/NSOBKKEYR: + description: FLASH non-secure OBK key register + fields: + - name: NSOBKKEY + description: FLASH non-secure option bytes keys control access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/NSSR: + description: FLASH non-secure status register + fields: + - name: BSY + description: "busy flag\r BSY flag indicates that a flash memory is busy by an operation (write, erase, option byte change, OBK operation). It is set at the beginning of a flash memory operation and cleared when the operation finishes, or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: "write buffer not empty flag \r WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_NSCR\r the embedded flash memory detects an error that involves data loss\r This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: DBNE + description: "data buffer not empty flag \r DBNE flag is set when the flash interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: EOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register." + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: "strobe error flag \r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: "inconsistency error flag\r NSINCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears NSINCERR." + bit_offset: 20 + bit_size: 1 + - name: OBKERR + description: "OBK general error flag\r OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled." + bit_offset: 21 + bit_size: 1 + - name: OBKWERR + description: "OBK write error flag\r OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation." + bit_offset: 22 + bit_size: 1 + - name: OPTCHANGEERR + description: "Option byte change error flag \r OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. \r Writing 1 to CLR_OPTCHANGEERR of register FLASH_NSCCR clears OPTCHANGEERR.\r Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set." + bit_offset: 23 + bit_size: 1 +fieldset/OPSR: + description: FLASH operation status register + fields: + - name: ADDR_OP + description: Interrupted operation address + bit_offset: 0 + bit_size: 20 + - name: DATA_OP + description: "Flash high-cycle data area operation interrupted\r It indicates if flash high-cycle data area is concerned by operation." + bit_offset: 21 + bit_size: 1 + - name: BK_OP + description: "Interrupted operation bank\r It indicates which bank was concerned by operation." + bit_offset: 22 + bit_size: 1 + - name: SYSF_OP + description: "Operation in system flash memory interrupted \r Indicates that reset interrupted an ongoing operation in system flash." + bit_offset: 23 + bit_size: 1 + - name: OTP_OP + description: "OTP operation interrupted\r Indicates that reset interrupted an ongoing operation in OTP area (or OBKeys area)." + bit_offset: 24 + bit_size: 1 + - name: CODE_OP + description: Flash memory operation code + bit_offset: 29 + bit_size: 3 + enum: CODE_OP +fieldset/OPTCR: + description: FLASH option control register + fields: + - name: OPTLOCK + description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. \r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: OPTSTRT + description: "Option byte start change option configuration bit\r OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It is set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It is reseted at the same time as BSY bit.\r The user application cannot modify any FLASH_XXX_PRG flash interface register until the option change operation has been completed.\r Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in nonvolatile memory." + bit_offset: 1 + bit_size: 1 + - name: SWAP_BANK + description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR." + bit_offset: 31 + bit_size: 1 + enum: OPTCR_SWAP_BANK +fieldset/OPTKEYR: + description: FLASH option key register + fields: + - name: OPTKEY + description: FLASH option bytes control access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/OPTSR: + description: FLASH option status register + fields: + - name: BOR_LEV + description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset.\r 00 or 11: BOR Level 1, the threshold level is low (around 2.1�V)" + bit_offset: 0 + bit_size: 2 + enum: OPTSR_BOR_LEV + - name: BORH_EN + description: Brownout high enable + bit_offset: 2 + bit_size: 1 + - name: IWDG_SW + description: IWDG control mode option status bit + bit_offset: 3 + bit_size: 1 + enum: OPTSR_IWDG_SW + - name: WWDG_SW + description: WWDG control mode option status bit + bit_offset: 4 + bit_size: 1 + enum: OPTSR_WWDG_SW + - name: NRST_STOP + description: Core domain Stop entry reset option status bit + bit_offset: 6 + bit_size: 1 + enum: OPTSR_NRST_STOP + - name: NRST_STDBY + description: Core domain Standby entry reset option status bit + bit_offset: 7 + bit_size: 1 + enum: OPTSR_NRST_STDBY + - name: PRODUCT_STATE + description: "Life state code (based on Hamming 8,4). More information in Section�7.6.11: Product state transitions." + bit_offset: 8 + bit_size: 8 + - name: IO_VDD_HSLV + description: "High-speed IO at low VDD voltage configuration bit.\r This bit can be set only with VDD below 2.7�V." + bit_offset: 16 + bit_size: 1 + enum: OPTSR_IO_VDD_HSLV + - name: IO_VDDIO2_HSLV + description: "High-speed IO at low VDDIO2 voltage configuration bit.\r This bit can be set only with VDDIO2 below 2.7�V." + bit_offset: 17 + bit_size: 1 + enum: OPTSR_IO_VDDIO_HSLV + - name: IWDG_STOP + description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode." + bit_offset: 20 + bit_size: 1 + enum: OPTSR_IWDG_STOP + - name: IWDG_STDBY + description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode." + bit_offset: 21 + bit_size: 1 + enum: OPTSR_IWDG_STDBY + - name: BOOT_UBE + description: "Available only on cryptography enabled devices.\r Unique boot entry control, selects either ST or OEM iRoT for secure boot." + bit_offset: 22 + bit_size: 8 + enum: OPTSR_BOOT_UBE + - name: SWAP_BANK + description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. \r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset." + bit_offset: 31 + bit_size: 1 + enum: OPTSR_SWAP_BANK +fieldset/OPTSR2: + description: FLASH option status register 2 + fields: + - name: SRAM13_RST + description: SRAM1 and SRAM3 erase upon system reset + bit_offset: 2 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 3 + bit_size: 1 + - name: BKPRAM_ECC + description: Backup RAM ECC detection and correction disable + bit_offset: 4 + bit_size: 1 + enum: OPTSR_BKPRAM_ECC + - name: SRAM3_ECC + description: SRAM3 ECC detection and correction disable + bit_offset: 5 + bit_size: 1 + enum: OPTSR_SRAM_ECC + - name: SRAM2_ECC + description: SRAM2 ECC detection and correction disable + bit_offset: 6 + bit_size: 1 + enum: OPTSR_SRAM_ECC + - name: USBPD_DIS + description: USB power delivery configuration option bit + bit_offset: 8 + bit_size: 1 + - name: TZEN + description: "TrustZone enable configuration bits\r This bit enables the device is in TrustZone mode during an option byte change." + bit_offset: 24 + bit_size: 8 + enum: OPTSR_TZEN +fieldset/OTPBLR: + description: FLASH non-secure OTP block lock + fields: + - name: LOCKBL + description: "OTP block lock \r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it’s not possible to remove the write protection.\r Also if not locked, it is not possible to erase OTP words." + bit_offset: 0 + bit_size: 32 +fieldset/PRIVBB: + description: FLASH privilege block-based register for Bank 2 + fields: + - name: PRIVBB + description: Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + bit_offset: 0 + bit_size: 32 + enum: PRIVBBR_PRIVBB +fieldset/PRIVCFGR: + description: FLASH privilege configuration register + fields: + - name: SPRIV + description: privilege attribute for secure registers + bit_offset: 0 + bit_size: 1 + enum: SPRIV + - name: NSPRIV + description: privilege attribute for non secure registers + bit_offset: 1 + bit_size: 1 + enum: NSPRIV +fieldset/SECBB: + description: FLASH secure block-based register for Bank 2 + fields: + - name: SECBB + description: Secure/non-secure flash Bank 2 sector attribute + bit_offset: 0 + bit_size: 32 + enum: SECBBR_SECBB +fieldset/SECBOOTR: + description: FLASH secure boot register + fields: + - name: SECBOOT_LOCK + description: "A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings." + bit_offset: 0 + bit_size: 8 + enum: SECBOOTR_SECBOOT_LOCK + - name: SECBOOTADD + description: "Unique boot entry secure address \r These bits reflect the Secure UBE address" + bit_offset: 8 + bit_size: 24 +fieldset/SECCCR: + description: FLASH secure clear control register + fields: + - name: CLR_EOP + description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_SECSR register." + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_SECSR register." + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_SECSR register." + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_SECSR register." + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_SECSR register." + bit_offset: 20 + bit_size: 1 + - name: CLR_OBKERR + description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register." + bit_offset: 21 + bit_size: 1 + - name: CLR_OBKWERR + description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register." + bit_offset: 22 + bit_size: 1 +fieldset/SECCR: + description: FLASH secure control register + fields: + - name: LOCK + description: "configuration lock bit \r This bit locks the FLASH_SECCR register. The correct write sequence to FLASH_SECKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. \r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_SECCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: PG + description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0. \r PG allows programming in Bank1 and Bank2." + bit_offset: 1 + bit_size: 1 + - name: SER + description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. \r If BER and MER are also set, a PGSERR is raised." + bit_offset: 2 + bit_size: 1 + - name: BER + description: "erase request \r Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." + bit_offset: 3 + bit_size: 1 + - name: FW + description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. \r The embedded flash memory resets FW when the corresponding operation has been acknowledged. \r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty and was filled by secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). \r Since there is just one write buffer, FW can force a write in bank1 or bank2." + bit_offset: 4 + bit_size: 1 + - name: STRT + description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. \r STRT is reseted at the end of the operation or when an error occurs. It cannot be reset by software." + bit_offset: 5 + bit_size: 1 + - name: SNB + description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r .." + bit_offset: 6 + bit_size: 7 + - name: MER + description: "mass erase request\r Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. \r If BER or SER are also set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program/erase operation. EOPIE can be programmed only when LOCK is cleared to 0." + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 20 + bit_size: 1 + - name: OBKERRIE + description: "OBK general error interrupt enable bit\r OBKERRIE enables generating an interrupt in case of OBK specific access error. OBKERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 21 + bit_size: 1 + - name: OBKWERRIE + description: "OBK write error interrupt enable bit\r OBKWERRIE enables generation of interrupt in case of OBK specific write error. OBKWERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 22 + bit_size: 1 + - name: INV + description: "Flash memory security state invert.\r This bit inverts the flash memory security state." + bit_offset: 29 + bit_size: 1 + - name: BKSEL + description: "bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." + bit_offset: 31 + bit_size: 1 + enum: SECCR_BKSEL +fieldset/SECEPOCHR: + description: FLASH secure EPOCH register + fields: + - name: SEC_EPOCH + description: Non-volatile secure EPOCH counter + bit_offset: 0 + bit_size: 24 +fieldset/SECKEYR: + description: FLASH secure key register + fields: + - name: SECKEY + description: Non-volatile memory secure configuration access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/SECOBKCFGR: + description: FLASH secure OBK configuration register + fields: + - name: LOCK + description: "OBKCFGR lock option configuration bit\r This bit locks the FLASH_OBKCFGR register. The correct write sequence to FLASH_SECOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_SECOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: SWAP_SECT_REQ + description: "OBK swap sector request bit\r When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one.\r The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3." + bit_offset: 1 + bit_size: 1 + - name: ALT_SECT + description: "alternate sector bit\r This bit must not change while filling the write buffer, otherwise an error is generated" + bit_offset: 2 + bit_size: 1 + - name: ALT_SECT_ERASE + description: "alternate sector erase bit\r When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as the BUSY bit." + bit_offset: 3 + bit_size: 1 + - name: SWAP_OFFSET + description: "key index (offset /16 bits) pointing for next swap.\r …" + bit_offset: 16 + bit_size: 9 +fieldset/SECOBKKEYR: + description: FLASH secure OBK key register + fields: + - name: SECOBKKEY + description: FLASH secure option bytes keys control access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/SECSR: + description: FLASH secure status register + fields: + - name: BSY + description: "busy flag\r BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: "write buffer not empty flag \r WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the flash interface detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: DBNE + description: "data buffer not empty flag \r DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: EOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register." + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: "strobe error flag \r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR." + bit_offset: 20 + bit_size: 1 + - name: OBKERR + description: "OBK general error flag\r OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled." + bit_offset: 21 + bit_size: 1 + - name: OBKWERR + description: "OBK write error flag\r OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation." + bit_offset: 22 + bit_size: 1 +fieldset/SECWM: + description: FLASH security watermark for Bank 2 + fields: + - name: SECWMSTRT + description: Bank2 security WM area start sector + bit_offset: 0 + bit_size: 7 + - name: SECWMEND + description: Bank2 security WM end sector + bit_offset: 16 + bit_size: 7 +fieldset/WRP: + description: FLASH write sector group protection for Bank 1 + fields: + - name: WRPSG + description: "Bank1 sector group protection option status byte\r Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected)\r Bit 0: Group embedding sectors 0 to 3\r Bit 1: Group embedding sectors 4 to 7\r Bit N: Group embedding sectors 4 x N to 4 x N + 3\r Bit 31: Group embedding sectors 124 to 127" + bit_offset: 0 + bit_size: 32 +enum/BOOTR_SECBOOT_LOCK: + bit_size: 8 + variants: + - name: B_0xB4 + description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + value: 180 + - name: B_0xC3 + description: "The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules." + value: 195 +enum/CODE_OP: + bit_size: 3 + variants: + - name: B_0x0 + description: No flash operation on going during previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x2 + description: OBK alternate sector erase + value: 2 + - name: B_0x3 + description: Sector erase operation interrupted + value: 3 + - name: B_0x4 + description: Bank erase operation interrupted + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 + - name: B_0x7 + description: OBK swap sector request + value: 7 +enum/NSBOOTR_NSBOOT_LOCK: + bit_size: 8 + variants: + - name: B_0xB4 + description: The NSBOOTADD is frozen. SWAP_ BANK can only be modified with TZEN set to 0xB4 (enabled). + value: 180 + - name: B_0xC3 + description: The SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. + value: 195 +enum/NSCR_BKSEL: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 is selected for Bank erase / sector erase / interrupt enable + value: 0 + - name: B_0x1 + description: Bank2 is selected for BER / SER + value: 1 +enum/NSPRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: access to non secure registers is always granted + value: 0 + - name: B_0x1 + description: access to non secure registers is denied in case of unprivileged access. + value: 1 +enum/OPTCR_SWAP_BANK: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 +enum/OPTSR_BKPRAM_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: BKPRAM ECC check enabled + value: 0 + - name: B_0x1 + description: BKPRAM ECC check disabled + value: 1 +enum/OPTSR_BOOT_UBE: + bit_size: 8 + variants: + - name: B_0xB4 + description: OEM-iRoT (user flash) selected. In Open PRODUCT_STATE this value selects bootloader. Defaut value. + value: 180 + - name: B_0xC3 + description: ST-iRoT (system flash) selected + value: 195 +enum/OPTSR_BOR_LEV: + bit_size: 2 + variants: + - name: B_0x1 + description: "BOR Level 2, the threshold level is medium (around 2.4 V)" + value: 1 + - name: B_0x2 + description: "BOR Level 3, the threshold level is high (around 2.7 V)" + value: 2 +enum/OPTSR_IO_VDDIO_HSLV: + bit_size: 1 + variants: + - name: B_0x0 + description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7�V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7�V) + value: 1 +enum/OPTSR_IO_VDD_HSLV: + bit_size: 1 + variants: + - name: B_0x0 + description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7�V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7�V) + value: 1 +enum/OPTSR_IWDG_STDBY: + bit_size: 1 + variants: + - name: B_0x0 + description: Independent watchdog frozen in Standby mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in Standby mode. + value: 1 +enum/OPTSR_IWDG_STOP: + bit_size: 1 + variants: + - name: B_0x0 + description: Independent watchdog frozen in system Stop mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in system Stop mode. + value: 1 +enum/OPTSR_IWDG_SW: + bit_size: 1 + variants: + - name: B_0x0 + description: IWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: IWDG watchdog is controlled by software + value: 1 +enum/OPTSR_NRST_STDBY: + bit_size: 1 + variants: + - name: B_0x0 + description: a reset is generated when entering Standby mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Standby mode on core domain. + value: 1 +enum/OPTSR_NRST_STOP: + bit_size: 1 + variants: + - name: B_0x0 + description: a reset is generated when entering Stop mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Stop mode on core domain. + value: 1 +enum/OPTSR_SRAM_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: SRAM2 ECC check enabled + value: 0 + - name: B_0x1 + description: SRAM2 ECC check disabled + value: 1 +enum/OPTSR_SWAP_BANK: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 +enum/OPTSR_TZEN: + bit_size: 8 + variants: + - name: B_0xB4 + description: TrustZone enabled. + value: 180 + - name: B_0xC3 + description: TrustZone disabled + value: 195 +enum/OPTSR_WWDG_SW: + bit_size: 1 + variants: + - name: B_0x0 + description: WWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: WWDG watchdog is controlled by software + value: 1 +enum/PRIVBBR_PRIVBB: + bit_size: 32 + variants: + - name: B_0x0 + description: sectors (32 * (x-1) + y) in bank 2 is unprivileged + value: 0 + - name: B_0x1 + description: sector (32 * (x-1) + y) in bank 2 is privileged + value: 1 +enum/SECBBR_SECBB: + bit_size: 32 + variants: + - name: B_0x0 + description: sectors (32 * (x-1) + y) in bank 2 is non secure + value: 0 + - name: B_0x1 + description: sector (32 * (x-1) + y) in bank 2 is secure + value: 1 +enum/SECBOOTR_SECBOOT_LOCK: + bit_size: 8 + variants: + - name: B_0xB4 + description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled). + value: 180 + - name: B_0xC3 + description: "The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules." + value: 195 +enum/SECCR_BKSEL: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 is selected for Bank erase / sector erase / interrupt enable + value: 0 + - name: B_0x1 + description: Bank2 is selected for BER / SER + value: 1 +enum/SPRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: access to secure registers is always granted + value: 0 + - name: B_0x1 + description: access to secure registers is denied in case of unprivileged access. + value: 1 diff --git a/data/registers/flash_h50.yaml b/data/registers/flash_h50.yaml new file mode 100644 index 0000000..fa7f6f2 --- /dev/null +++ b/data/registers/flash_h50.yaml @@ -0,0 +1,779 @@ +--- +block/FLASH: + description: FLASH address block description + items: + - name: ACR + description: "FLASH access control register " + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: "FLASH key register " + byte_offset: 4 + fieldset: NSKEYR + - name: OPTKEYR + description: "FLASH option key register " + byte_offset: 12 + fieldset: OPTKEYR + - name: OPSR + description: "FLASH operation status register " + byte_offset: 24 + fieldset: OPSR + - name: OPTCR + description: "FLASH option control register " + byte_offset: 28 + fieldset: OPTCR + - name: NSSR + description: "FLASH non-secure status register " + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: "FLASH secure status register " + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: "FLASH Non Secure control register " + byte_offset: 40 + fieldset: NSCR + - name: NSCCR + description: "FLASH non-secure clear control register " + byte_offset: 48 + fieldset: NSCCR + - name: PRIVCFGR + description: "FLASH privilege configuration register " + byte_offset: 60 + fieldset: PRIVCFGR + - name: HDPEXTR + description: "FLASH HDP extension register " + byte_offset: 72 + fieldset: HDPEXTR + - name: OPTSR_CUR + description: "FLASH option status register " + byte_offset: 80 + fieldset: OPTSR + - name: OPTSR_PRG + description: "FLASH option status register " + byte_offset: 84 + fieldset: OPTSR + - name: OPTSR2_CUR + description: "FLASH option status register 2 " + byte_offset: 112 + fieldset: OPTSR2 + - name: OPTSR2_PRG + description: "FLASH option status register 2 " + byte_offset: 116 + fieldset: OPTSR2 + - name: NSBOOTR_CUR + description: "FLASH non-secure unique boot entry register " + byte_offset: 128 + fieldset: NSBOOTR + - name: NSBOOTR_PRG + description: "FLASH non-secure unique boot entry address " + byte_offset: 132 + fieldset: NSBOOTR + - name: OTPBLR_CUR + description: "FLASH non-secure OTP block lock " + byte_offset: 144 + fieldset: OTPBLR + - name: OTPBLR_PRG + description: "FLASH non-secure OTP block lock " + byte_offset: 148 + fieldset: OTPBLR + - name: PRIVBB1R + description: "FLASH privilege register for bank 1 " + byte_offset: 192 + fieldset: PRIVBB + - name: WRPSGN1R_CUR + description: "FLASH write sector protection for Bank1\t" + byte_offset: 232 + fieldset: WRP + - name: WRPSGN1R_PRG + description: "FLASH write sector protection for Bank1\t" + byte_offset: 236 + fieldset: WRP + - name: HDP1R_CUR + description: "FLASH HDP Bank1 register " + byte_offset: 248 + fieldset: HDP1R + - name: HDP1R_PRG + description: "FLASH HDP Bank1 register " + byte_offset: 252 + fieldset: HDP1R + - name: ECCCORR + description: "FLASH Flash ECC correction register " + byte_offset: 256 + fieldset: ECCCORR + - name: ECCDETR + description: "FLASH ECC detection register " + byte_offset: 260 + fieldset: ECCDETR + - name: ECCDR + description: "FLASH ECC data " + byte_offset: 264 + fieldset: ECCDR + - name: WRPSGN2R_CUR + description: "FLASH write sector protection for Bank2\t" + byte_offset: 488 + fieldset: WRP + - name: WRPSGN2R_PRG + description: "FLASH write sector protection for Bank2\t" + byte_offset: 492 + fieldset: WRP + - name: HDP2R_CUR + description: "FLASH HDP Bank2 register " + byte_offset: 504 + fieldset: HDP2R + - name: HDP2R_PRG + description: "FLASH HDP Bank2 register " + byte_offset: 508 + fieldset: HDP2R +fieldset/ACR: + description: "FLASH access control register " + fields: + - name: LATENCY + description: "Read latency\r These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct." + bit_offset: 0 + bit_size: 4 + - name: WRHIGHFREQ + description: "Flash signal delay\r These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details.\r Note: No check is performed to verify that the configuration is correct.\r Two WRHIGHFREQ values can be selected for some frequencies." + bit_offset: 4 + bit_size: 2 + - name: PRFTEN + description: "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account.\r Bits used to control the prefetch." + bit_offset: 8 + bit_size: 1 + - name: S_PRFTEN + description: "Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account.\r Bits used to control the prefetch functionality." + bit_offset: 9 + bit_size: 1 +fieldset/ECCCORR: + description: "FLASH Flash ECC correction register " + fields: + - name: ADDR_ECC + description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." + bit_offset: 0 + bit_size: 16 + - name: BK_ECC + description: "ECC bank flag for corrected ECC error\r It indicates which bank is concerned by ECC error" + bit_offset: 22 + bit_size: 1 + - name: SYSF_ECC + description: "ECC flag for corrected ECC error in system FLASH\r It indicates if system Flash memory is concerned by ECC error." + bit_offset: 23 + bit_size: 1 + - name: OTP_ECC + description: "OTP ECC error bit\r This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield." + bit_offset: 24 + bit_size: 1 + - name: ECCCIE + description: "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation." + bit_offset: 25 + bit_size: 1 + - name: ECCC + description: "ECC correction set by hardware when single ECC error has been detected and corrected.\r Cleared by writing 1." + bit_offset: 30 + bit_size: 1 +fieldset/ECCDETR: + description: "FLASH ECC detection register " + fields: + - name: ADDR_ECC + description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." + bit_offset: 0 + bit_size: 16 + - name: BK_ECC + description: "ECC fail bank for double ECC Error\r It indicates which bank is concerned by ECC error" + bit_offset: 22 + bit_size: 1 + - name: SYSF_ECC + description: "ECC fail for double ECC error in system Flash memory\r It indicates if system Flash memory is concerned by ECC error." + bit_offset: 23 + bit_size: 1 + - name: OTP_ECC + description: "OTP ECC error bit\r This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field." + bit_offset: 24 + bit_size: 1 + - name: ECCD + description: "ECC detection set by hardware when two ECC error has been detected.\r When this bit is set, a NMI is generated.\r Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors." + bit_offset: 31 + bit_size: 1 +fieldset/ECCDR: + description: "FLASH ECC data " + fields: + - name: DATA_ECC + description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory." + bit_offset: 0 + bit_size: 16 +fieldset/HDP1R: + description: "FLASH HDP Bank1 register " + fields: + - name: HDP1_STRT + description: HDPL barrier start set in number of 8 Kbytes sectors + bit_offset: 0 + bit_size: 3 + - name: HDP1_END + description: HDPL barrier end set in number of 8 Kbytes sectors + bit_offset: 16 + bit_size: 3 +fieldset/HDP2R: + description: "FLASH HDP Bank2 register " + fields: + - name: HDP2_STRT + description: Bank 2 HDPL barrier start set in number of 8 Kbytes sectors + bit_offset: 0 + bit_size: 3 + - name: HDP2_END + description: Bank 2 HDPL barrier end set in number of 8 Kbytes sectors + bit_offset: 16 + bit_size: 3 +fieldset/HDPEXTR: + description: "FLASH HDP extension register " + fields: + - name: HDP1_EXT + description: HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. + bit_offset: 0 + bit_size: 3 + - name: HDP2_EXT + description: HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector. + bit_offset: 16 + bit_size: 3 +fieldset/NSBOOTR: + description: "FLASH non-secure unique boot entry register " + fields: + - name: NSBOOT_LOCK + description: "A field locking the values of SWAP_BANK, and NSBOOTADD settings." + bit_offset: 0 + bit_size: 8 + enum: NSBOOTR_NSBOOT_LOCK + - name: NSBOOTADD + description: "unique boot entry address\r These bits reflect the UBE address" + bit_offset: 8 + bit_size: 24 +fieldset/NSCCR: + description: "FLASH non-secure clear control register " + fields: + - name: CLR_EOP + description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register." + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register." + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register." + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register." + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register." + bit_offset: 20 + bit_size: 1 + - name: CLR_OPTCHANGEERR + description: Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + bit_offset: 23 + bit_size: 1 +fieldset/NSCR: + description: "FLASH Non Secure control register " + fields: + - name: LOCK + description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset.\r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: PG + description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0.\r PG allows programming in Bank1 and Bank2." + bit_offset: 1 + bit_size: 1 + - name: SER + description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised." + bit_offset: 2 + bit_size: 1 + - name: BER + description: "erase request\r Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." + bit_offset: 3 + bit_size: 1 + - name: FW + description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0.\r The embedded Flash memory resets FW when the corresponding operation has been acknowledged.\r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).\r Since there is just one write buffer, FW can force a write in bank1 or bank2." + bit_offset: 4 + bit_size: 1 + - name: STRT + description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0.\r STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software." + bit_offset: 5 + bit_size: 1 + - name: SNB + description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r ..." + bit_offset: 6 + bit_size: 3 + - name: MER + description: "Mass erase request\r Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0.\r If BER or SER are both set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0." + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 20 + bit_size: 1 + - name: OPTCHANGEERRIE + description: "Option byte change error interrupt enable bit\r OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0." + bit_offset: 23 + bit_size: 1 + - name: BKSEL + description: "Bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." + bit_offset: 31 + bit_size: 1 + enum: BKSEL +fieldset/NSKEYR: + description: "FLASH key register " + fields: + - name: NSKEY + description: Non-volatile memory configuration access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/NSSR: + description: "FLASH non-secure status register " + fields: + - name: BSY + description: "busy flag\r BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_NSCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: DBNE + description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: EOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register." + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR." + bit_offset: 20 + bit_size: 1 + - name: OPTCHANGEERR + description: "Option byte change error flag\r OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1.\r Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR.\r Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set." + bit_offset: 23 + bit_size: 1 +fieldset/OPSR: + description: "FLASH operation status register " + fields: + - name: ADDR_OP + description: Interrupted operation address. + bit_offset: 0 + bit_size: 20 + - name: BK_OP + description: "Interrupted operation bank\r It indicates which bank was concerned by operation." + bit_offset: 22 + bit_size: 1 + - name: SYSF_OP + description: "Operation in system Flash memory interrupted\r Indicates that reset interrupted an ongoing operation in System Flash." + bit_offset: 23 + bit_size: 1 + - name: OTP_OP + description: "OTP operation interrupted\r Indicates that reset interrupted an ongoing operation in OTP area." + bit_offset: 24 + bit_size: 1 + - name: CODE_OP + description: Flash memory operation code + bit_offset: 29 + bit_size: 3 + enum: CODE_OP +fieldset/OPTCR: + description: "FLASH option control register " + fields: + - name: OPTLOCK + description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset.\r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: OPTSTRT + description: "Option byte start change option configuration bit\r OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit.\r The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed.\r Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory." + bit_offset: 1 + bit_size: 1 + - name: SWAP_BANK + description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR." + bit_offset: 31 + bit_size: 1 + enum: OPTCR_SWAP_BANK +fieldset/OPTKEYR: + description: "FLASH option key register " + fields: + - name: OPTKEY + description: FLASH option bytes control access unlock key + bit_offset: 0 + bit_size: 32 +fieldset/OPTSR: + description: "FLASH option status register " + fields: + - name: BOR_LEV + description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset." + bit_offset: 0 + bit_size: 2 + enum: OPTSR_BOR_LEV + - name: BORH_EN + description: Brownout high enable status bit + bit_offset: 2 + bit_size: 1 + - name: IWDG_SW + description: IWDG control mode option status bit + bit_offset: 3 + bit_size: 1 + enum: OPTSR_IWDG_SW + - name: WWDG_SW + description: WWDG control mode option status bit + bit_offset: 4 + bit_size: 1 + enum: OPTSR_WWDG_SW + - name: NRST_SHDW + description: Core domain Shutdown entry reset option status bit + bit_offset: 5 + bit_size: 1 + enum: OPTSR_NRST_SHDW + - name: NRST_STOP + description: Core domain Stop entry reset option status bit + bit_offset: 6 + bit_size: 1 + enum: OPTSR_NRST_STOP + - name: NRST_STDBY + description: Core domain Standby entry reset option status bit + bit_offset: 7 + bit_size: 1 + enum: OPTSR_NRST_STDBY + - name: PRODUCT_STATE + description: "Life state code (based on Hamming 8,4). More information in ." + bit_offset: 8 + bit_size: 8 + - name: IO_VDD_HSLV + description: High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. + bit_offset: 16 + bit_size: 1 + enum: OPTSR_IO_VDD_HSLV + - name: IO_VDDIO2_HSLV + description: High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. + bit_offset: 17 + bit_size: 1 + enum: OPTSR_IO_VDDIO_HSLV + - name: IWDG_STOP + description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode." + bit_offset: 20 + bit_size: 1 + enum: OPTSR_IWDG_STOP + - name: IWDG_STDBY + description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode." + bit_offset: 21 + bit_size: 1 + enum: OPTSR_IWDG_STDBY + - name: SWAP_BANK + description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not.\r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset." + bit_offset: 31 + bit_size: 1 + enum: OPTSR_SWAP_BANK +fieldset/OPTSR2: + description: "FLASH option status register 2 " + fields: + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 3 + bit_size: 1 + - name: BKPRAM_ECC + description: Backup RAM ECC detection and correction disable + bit_offset: 4 + bit_size: 1 + enum: OPTSR_BKPRAM_ECC + - name: SRAM2_ECC + description: SRAM2 ECC detection and correction disable + bit_offset: 6 + bit_size: 1 + enum: OPTSR_SRAM_ECC + - name: SRAM1_RST + description: SRAM1 erase upon system reset + bit_offset: 9 + bit_size: 1 + - name: SRAM1_ECC + description: SRAM1 ECC detection and correction disable + bit_offset: 10 + bit_size: 1 + enum: OPTSR_SRAM_ECC +fieldset/OTPBLR: + description: "FLASH non-secure OTP block lock " + fields: + - name: LOCKBL + description: "OTP block lock\r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it is not possible to remove the write protection.\r LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared." + bit_offset: 0 + bit_size: 32 +fieldset/PRIVBB: + description: "FLASH privilege register for bank 1 " + fields: + - name: PRIVBB + description: Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) + bit_offset: 0 + bit_size: 8 + enum: PRIVBB +fieldset/PRIVCFGR: + description: "FLASH privilege configuration register " + fields: + - name: NSPRIV + description: privilege attribute for non secure registers + bit_offset: 1 + bit_size: 1 + enum: NSPRIV +fieldset/SECSR: + description: "FLASH secure status register " + fields: + - name: SECBSY + description: "busy flag\r BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: SECWBNE + description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: SECDBNE + description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: SECEOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register." + bit_offset: 16 + bit_size: 1 + - name: SECWRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: SECPGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: SECSTRBERR + description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: SECINCERR + description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR." + bit_offset: 20 + bit_size: 1 +fieldset/WRP: + description: "FLASH write sector protection for Bank2\t" + fields: + - name: WRPSG + description: "Bank2 sector protection option status byte\r Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)" + bit_offset: 0 + bit_size: 8 +enum/BKSEL: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 is selected for Bank erase / sector erase / interrupt enable + value: 0 + - name: B_0x1 + description: Bank2 is selected for BER / SER + value: 1 +enum/CODE_OP: + bit_size: 3 + variants: + - name: B_0x0 + description: No Flash operation on going during previous reset + value: 0 + - name: B_0x1 + description: "Single write operation interrupted " + value: 1 + - name: B_0x3 + description: Sector erase operation interrupted + value: 3 + - name: B_0x4 + description: "Bank erase operation interrupted " + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 +enum/NSBOOTR_NSBOOT_LOCK: + bit_size: 8 + variants: + - name: B_0xB4 + description: The NSBOOTADD and SWAP_BANK are frozen. + value: 180 + - name: B_0xC3 + description: The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + value: 195 +enum/NSPRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: access to non secure registers is always granted + value: 0 + - name: B_0x1 + description: access to non secure registers is denied in case of non privileged access. + value: 1 +enum/OPTCR_SWAP_BANK: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 +enum/OPTSR_BKPRAM_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: "BKPRAM ECC check enabled " + value: 0 + - name: B_0x1 + description: BKPRAM ECC check disabled + value: 1 +enum/OPTSR_BOR_LEV: + bit_size: 2 + variants: + - name: B_0x0 + description: "BOR OFF, POR/PDR reset threshold level is applied" + value: 0 + - name: B_0x1 + description: "BOR Level 1, the threshold level is low (around 2.1 V)" + value: 1 + - name: B_0x2 + description: "BOR Level 2, the threshold level is medium (around 2.4 V)" + value: 2 + - name: B_0x3 + description: "BOR Level 3, the threshold level is high (around 2.7 V)" + value: 3 +enum/OPTSR_IO_VDDIO_HSLV: + bit_size: 1 + variants: + - name: B_0x0 + description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) " + value: 0 + - name: B_0x1 + description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) " + value: 1 +enum/OPTSR_IO_VDD_HSLV: + bit_size: 1 + variants: + - name: B_0x0 + description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) " + value: 0 + - name: B_0x1 + description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) " + value: 1 +enum/OPTSR_IWDG_STDBY: + bit_size: 1 + variants: + - name: B_0x0 + description: Independent watchdog frozen in Standby mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in Standby mode. + value: 1 +enum/OPTSR_IWDG_STOP: + bit_size: 1 + variants: + - name: B_0x0 + description: Independent watchdog frozen in system Stop mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in system Stop mode. + value: 1 +enum/OPTSR_IWDG_SW: + bit_size: 1 + variants: + - name: B_0x0 + description: IWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: IWDG watchdog is controlled by software + value: 1 +enum/OPTSR_NRST_SHDW: + bit_size: 1 + variants: + - name: B_0x0 + description: a reset is generated when entering Shutdown mode on core domain + value: 0 + - name: B_0x1 + description: "no reset generated when entering Shutdown mode on core domain. " + value: 1 +enum/OPTSR_NRST_STDBY: + bit_size: 1 + variants: + - name: B_0x0 + description: a reset is generated when entering Standby mode on core domain + value: 0 + - name: B_0x1 + description: "no reset generated when entering Standby mode on core domain. " + value: 1 +enum/OPTSR_NRST_STOP: + bit_size: 1 + variants: + - name: B_0x0 + description: a reset is generated when entering Stop mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Stop mode on core domain. + value: 1 +enum/OPTSR_SRAM_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: "SRAM2 ECC check enabled " + value: 0 + - name: B_0x1 + description: SRAM2 ECC check disabled + value: 1 +enum/OPTSR_SWAP_BANK: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 +enum/OPTSR_WWDG_SW: + bit_size: 1 + variants: + - name: B_0x0 + description: WWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: WWDG watchdog is controlled by software + value: 1 +enum/PRIVBB: + bit_size: 8 + variants: + - name: B_0x0 + description: sectors y in bank 1 is non privileged + value: 0 + - name: B_0x1 + description: sector y in bank 1 is privileged + value: 1 diff --git a/data/registers/pwr_h5.yaml b/data/registers/pwr_h5.yaml new file mode 100644 index 0000000..c90db26 --- /dev/null +++ b/data/registers/pwr_h5.yaml @@ -0,0 +1,582 @@ +--- +block/PWR: + description: Power control + items: + - name: PMCR + description: PWR power mode control register + byte_offset: 0 + fieldset: PMCR + - name: PMSR + description: PWR status register + byte_offset: 4 + fieldset: PMSR + - name: VOSCR + description: PWR voltage scaling control register + byte_offset: 16 + fieldset: VOSCR + - name: VOSSR + description: PWR voltage scaling status register + byte_offset: 20 + fieldset: VOSSR + - name: BDCR + description: PWR Backup domain control register + byte_offset: 32 + fieldset: BDCR + - name: DBPCR + description: PWR Backup domain control register + byte_offset: 36 + fieldset: DBPCR + - name: BDSR + description: PWR Backup domain status register + byte_offset: 40 + fieldset: BDSR + - name: UCPDR + description: PWR USB Type-C power delivery register + byte_offset: 44 + fieldset: UCPDR + - name: SCCR + description: PWR supply configuration control register + byte_offset: 48 + fieldset: SCCR + - name: VMCR + description: PWR voltage monitor control register + byte_offset: 52 + fieldset: VMCR + - name: USBSCR + description: PWR USB supply control register + byte_offset: 56 + fieldset: USBSCR + - name: VMSR + description: PWR voltage monitor status register + byte_offset: 60 + fieldset: VMSR + - name: WUSCR + description: PWR wakeup status clear register + byte_offset: 64 + fieldset: WUSCR + - name: WUSR + description: PWR wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUCR + description: PWR wakeup configuration register + byte_offset: 72 + fieldset: WUCR + - name: IORETR + description: PWR I/O retention register + byte_offset: 80 + fieldset: IORETR + - name: SECCFGR + description: PWR security configuration register + byte_offset: 256 + fieldset: SECCFGR + - name: PRIVCFGR + description: PWR privilege configuration register + byte_offset: 260 + fieldset: PRIVCFGR +fieldset/BDCR: + description: PWR Backup domain control register + fields: + - name: BREN + description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: Backup domain voltage and temperature monitoring enable + bit_offset: 1 + bit_size: 1 + - name: VBE + description: "VBAT charging enable\r Note: Reset only by POR,." + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + enum: VBRS +fieldset/BDSR: + description: PWR Backup domain status register + fields: + - name: BRRDY + description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/DBPCR: + description: PWR Backup domain control register + fields: + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." + bit_offset: 0 + bit_size: 1 +fieldset/IORETR: + description: PWR I/O retention register + fields: + - name: IORETEN + description: "IO retention enable:\r When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." + bit_offset: 0 + bit_size: 1 + - name: JTAGIORETEN + description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode" + bit_offset: 16 + bit_size: 1 +fieldset/PMCR: + description: PWR power mode control register + fields: + - name: LPMS + description: "low-power mode selection\r This bit defines the Deepsleep mode." + bit_offset: 0 + bit_size: 1 + - name: SVOS + description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." + bit_offset: 2 + bit_size: 2 + enum: SVOS + - name: CSSF + description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." + bit_offset: 7 + bit_size: 1 + - name: FLPS + description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." + bit_offset: 9 + bit_size: 1 + - name: BOOSTE + description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." + bit_offset: 12 + bit_size: 1 + - name: AVD_READY + description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." + bit_offset: 13 + bit_size: 1 + - name: ETHERNETSO + description: ETHERNET RAM shut-off in Stop mode. + bit_offset: 16 + bit_size: 1 + - name: SRAM3SO + description: AHB SRAM3 shut-off in Stop mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2_16SO + description: AHB SRAM2 16-Kbyte shut-off in Stop mode. + bit_offset: 24 + bit_size: 1 + - name: SRAM2_48SO + description: AHB SRAM2 48-Kbyte shut-off in Stop mode. + bit_offset: 25 + bit_size: 1 + - name: SRAM1SO + description: AHB SRAM1 shut-off in Stop mode + bit_offset: 26 + bit_size: 1 +fieldset/PMSR: + description: PWR status register + fields: + - name: STOPF + description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." + bit_offset: 5 + bit_size: 1 + - name: SBF + description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." + bit_offset: 6 + bit_size: 1 +fieldset/PRIVCFGR: + description: PWR privilege configuration register + fields: + - name: SPRIV + description: "PWR secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: PRIV + - name: NSPRIV + description: "PWR non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: PRIV +fieldset/SCCR: + description: PWR supply configuration control register + fields: + - name: BYPASS + description: power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." + bit_offset: 8 + bit_size: 1 + - name: SMPSEN + description: "SMPS enable \r The value is set by hardware when the package uses the SMPS regulator." + bit_offset: 9 + bit_size: 1 +fieldset/SECCFGR: + description: PWR security configuration register + fields: + - name: WUP1SEC + description: WUPx secure protection + bit_offset: 0 + bit_size: 1 + enum: SEC + - name: WUP2SEC + description: WUPx secure protection + bit_offset: 1 + bit_size: 1 + enum: SEC + - name: WUP3SEC + description: WUPx secure protection + bit_offset: 2 + bit_size: 1 + enum: SEC + - name: WUP4SEC + description: WUPx secure protection + bit_offset: 3 + bit_size: 1 + enum: SEC + - name: WUP5SEC + description: WUPx secure protection + bit_offset: 4 + bit_size: 1 + enum: SEC + - name: WUP6SEC + description: WUPx secure protection + bit_offset: 5 + bit_size: 1 + enum: SEC + - name: WUP7SEC + description: WUPx secure protection + bit_offset: 6 + bit_size: 1 + enum: SEC + - name: WUP8SEC + description: WUPx secure protection + bit_offset: 7 + bit_size: 1 + enum: SEC + - name: RETSEC + description: retention secure protection + bit_offset: 11 + bit_size: 1 + enum: SEC + - name: LPMSEC + description: low-power modes secure protection + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: SCMSEC + description: supply configuration and monitoring secure protection. + bit_offset: 13 + bit_size: 1 + enum: SEC + - name: VBSEC + description: backup domain secure protection + bit_offset: 14 + bit_size: 1 + enum: SEC + - name: VUSBSEC + description: voltage USB secure protection + bit_offset: 15 + bit_size: 1 + enum: SEC +fieldset/UCPDR: + description: PWR USB Type-C power delivery register + fields: + - name: UCPD_DBDIS + description: "USB Type-C and power delivery dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable)." + bit_offset: 0 + bit_size: 1 + - name: UCPD_STBY + description: "USB Type-c and Power delivery Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register." + bit_offset: 1 + bit_size: 1 +fieldset/USBSCR: + description: PWR USB supply control register + fields: + - name: USB33DEN + description: VDDUSB voltage level detector enable + bit_offset: 24 + bit_size: 1 + - name: USB33SV + description: "independent USB supply valid\r This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not." + bit_offset: 25 + bit_size: 1 +fieldset/VMCR: + description: PWR voltage monitor control register + fields: + - name: PVDE + description: PVD enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: AVDEN + description: peripheral voltage monitor on VDDA enable + bit_offset: 8 + bit_size: 1 + - name: ALS + description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." + bit_offset: 9 + bit_size: 2 + enum: ALS +fieldset/VMSR: + description: PWR voltage monitor status register + fields: + - name: AVDO + description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." + bit_offset: 19 + bit_size: 1 + enum: AVDO + - name: VDDIO2RDY + description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." + bit_offset: 20 + bit_size: 1 + - name: PVDO + description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." + bit_offset: 22 + bit_size: 1 + enum: PVDO + - name: USB33RDY + description: VDDUSB ready + bit_offset: 24 + bit_size: 1 +fieldset/VOSCR: + description: PWR voltage scaling control register + fields: + - name: VOS + description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." + bit_offset: 4 + bit_size: 2 + enum: VOS +fieldset/VOSSR: + description: PWR voltage scaling status register + fields: + - name: VOSRDY + description: Ready bit for VCORE voltage scaling output selection. + bit_offset: 3 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 14 + bit_size: 2 + enum: ACTVOS +fieldset/WUCR: + description: PWR wakeup configuration register + fields: + - name: WUPPUPD + description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." + bit_offset: 16 + bit_size: 2 + array: + len: 8 + stride: 2 + enum: WUPPUPD + - name: WUPEN + description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: WUPP + description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." + bit_offset: 8 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: WUPP +fieldset/WUSCR: + description: PWR wakeup status clear register + fields: + - name: CWUF + description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +fieldset/WUSR: + description: PWR wakeup status register + fields: + - name: WUF + description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +enum/ACTVOS: + bit_size: 2 + variants: + - name: B_0x0 + description: VOS3 (lowest power) + value: 0 + - name: B_0x1 + description: VOS2 + value: 1 + - name: B_0x2 + description: VOS1 + value: 2 + - name: B_0x3 + description: VOS0 (highest frequency) + value: 3 +enum/ALS: + bit_size: 2 + variants: + - name: B_0x0 + description: 1.7 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.5 V + value: 2 + - name: B_0x3 + description: 2.8 V + value: 3 +enum/AVDO: + bit_size: 1 + variants: + - name: B_0x0 + description: "VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits." + value: 0 + - name: B_0x1 + description: "VDDA is lower than the AVD threshold selected with the ALS[2:0] bits." + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: B_0x0 + description: 1.95 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.25 V + value: 2 + - name: B_0x3 + description: 2.4 V + value: 3 + - name: B_0x4 + description: 2.55 V + value: 4 + - name: B_0x5 + description: 2.7 V + value: 5 + - name: B_0x6 + description: 2.85 V + value: 6 + - name: B_0x7 + description: PVD_IN pin + value: 7 +enum/PRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: Read and write to PWR secure functions can be done by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Read and write to PWR secure functions can be done by privileged access only. + value: 1 +enum/PVDO: + bit_size: 1 + variants: + - name: B_0x0 + description: "VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits." + value: 0 + - name: B_0x1 + description: "VDD is lower than the PVD threshold selected through the PLS[2:0] bits." + value: 1 +enum/SEC: + bit_size: 1 + variants: + - name: B_0x0 + description: PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access. + value: 0 + - name: B_0x1 + description: PWR_SCCR and PWR_VMCR can be read and written only with secure access. + value: 1 +enum/SVOS: + bit_size: 2 + variants: + - name: B_0x0 + description: reserved + value: 0 + - name: B_0x1 + description: SVOS5 scale 5 + value: 1 + - name: B_0x2 + description: SVOS4 scale 4 + value: 2 + - name: B_0x3 + description: SVOS3 scale 3 (default). + value: 3 +enum/VBRS: + bit_size: 1 + variants: + - name: B_0x0 + description: Charge VBAT through a 5 kΩ resistor. + value: 0 + - name: B_0x1 + description: Charge VBAT through a 1.5 kΩ resistor. + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: B_0x0 + description: scale 3 (default) + value: 0 + - name: B_0x1 + description: scale 2 + value: 1 + - name: B_0x2 + description: scale 1 + value: 2 + - name: B_0x3 + description: scale 0 + value: 3 +enum/WUPP: + bit_size: 1 + variants: + - name: B_0x0 + description: detection on high level (rising edge) + value: 0 + - name: B_0x1 + description: detection on low level (falling edge) + value: 1 +enum/WUPPUPD: + bit_size: 2 + variants: + - name: B_0x0 + description: no pull-up + value: 0 + - name: B_0x1 + description: pull-up + value: 1 + - name: B_0x2 + description: pull-down + value: 2 + - name: B_0x3 + description: reserved + value: 3 diff --git a/data/registers/pwr_h50.yaml b/data/registers/pwr_h50.yaml new file mode 100644 index 0000000..1b8e961 --- /dev/null +++ b/data/registers/pwr_h50.yaml @@ -0,0 +1,446 @@ +--- +block/PWR: + description: Power control + items: + - name: PMCR + description: PWR power mode control register + byte_offset: 0 + fieldset: PMCR + - name: PMSR + description: PWR status register + byte_offset: 4 + fieldset: PMSR + - name: VOSCR + description: PWR voltage scaling control register + byte_offset: 16 + fieldset: VOSCR + - name: VOSSR + description: PWR voltage scaling status register + byte_offset: 20 + fieldset: VOSSR + - name: BDCR + description: PWR Backup domain control register + byte_offset: 32 + fieldset: BDCR + - name: DBPCR + description: PWR disable backup protection control register + byte_offset: 36 + fieldset: DBPCR + - name: BDSR + description: PWR Backup domain status register + byte_offset: 40 + fieldset: BDSR + - name: SCCR + description: PWR supply configuration control register + byte_offset: 48 + fieldset: SCCR + - name: VMCR + description: PWR voltage monitor control register + byte_offset: 52 + fieldset: VMCR + - name: VMSR + description: PWR voltage monitor status register + byte_offset: 60 + fieldset: VMSR + - name: WUSCR + description: PWR wakeup status clear register + byte_offset: 64 + fieldset: WUSCR + - name: WUSR + description: PWR wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUCR + description: PWR wakeup configuration register + byte_offset: 72 + fieldset: WUCR + - name: IORETR + description: PWR I/O retention register + byte_offset: 80 + fieldset: IORETR + - name: PRIVCFGR + description: PWR privilege configuration register + byte_offset: 260 + fieldset: PRIVCFGR +fieldset/BDCR: + description: PWR Backup domain control register + fields: + - name: BREN + description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: Backup domain voltage and temperature monitoring enable + bit_offset: 1 + bit_size: 1 + - name: VBE + description: "VBAT charging enable\r Note: Reset only by POR,." + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + enum: VBRS +fieldset/BDSR: + description: PWR Backup domain status register + fields: + - name: BRRDY + description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/DBPCR: + description: PWR disable backup protection control register + fields: + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." + bit_offset: 0 + bit_size: 1 +fieldset/IORETR: + description: PWR I/O retention register + fields: + - name: IORETEN + description: "IO retention enable:\r When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." + bit_offset: 0 + bit_size: 1 + - name: JTAGIORETEN + description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode" + bit_offset: 16 + bit_size: 1 +fieldset/PMCR: + description: PWR power mode control register + fields: + - name: LPMS + description: "low-power mode selection\r This bit defines the Deepsleep mode." + bit_offset: 0 + bit_size: 1 + - name: SVOS + description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." + bit_offset: 2 + bit_size: 2 + enum: SVOS + - name: CSSF + description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." + bit_offset: 7 + bit_size: 1 + - name: FLPS + description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." + bit_offset: 9 + bit_size: 1 + - name: BOOSTE + description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." + bit_offset: 12 + bit_size: 1 + - name: AVD_READY + description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." + bit_offset: 13 + bit_size: 1 + - name: SRAM2SO + description: AHB SRAM2 shut-off in Stop mode. + bit_offset: 25 + bit_size: 1 + - name: SRAM1SO + description: AHB SRAM1 shut-off in Stop mode + bit_offset: 26 + bit_size: 1 +fieldset/PMSR: + description: PWR status register + fields: + - name: STOPF + description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." + bit_offset: 5 + bit_size: 1 + - name: SBF + description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." + bit_offset: 6 + bit_size: 1 +fieldset/PRIVCFGR: + description: PWR privilege configuration register + fields: + - name: NSPRIV + description: "PWR functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access." + bit_offset: 1 + bit_size: 1 + enum: PRIV +fieldset/SCCR: + description: PWR supply configuration control register + fields: + - name: BYPASS + description: power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." + bit_offset: 8 + bit_size: 1 +fieldset/VMCR: + description: PWR voltage monitor control register + fields: + - name: PVDE + description: PVD enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: AVDEN + description: peripheral voltage monitor on VDDA enable + bit_offset: 8 + bit_size: 1 + - name: ALS + description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." + bit_offset: 9 + bit_size: 2 + enum: ALS +fieldset/VMSR: + description: PWR voltage monitor status register + fields: + - name: AVDO + description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." + bit_offset: 19 + bit_size: 1 + enum: AVDO + - name: VDDIO2RDY + description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." + bit_offset: 20 + bit_size: 1 + - name: PVDO + description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." + bit_offset: 22 + bit_size: 1 + enum: PVDO +fieldset/VOSCR: + description: PWR voltage scaling control register + fields: + - name: VOS + description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." + bit_offset: 4 + bit_size: 2 + enum: VOS +fieldset/VOSSR: + description: PWR voltage scaling status register + fields: + - name: VOSRDY + description: Ready bit for VCORE voltage scaling output selection. + bit_offset: 3 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 14 + bit_size: 2 + enum: ACTVOS +fieldset/WUCR: + description: PWR wakeup configuration register + fields: + - name: WUPEN + description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: WUPP + description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." + bit_offset: 8 + bit_size: 1 + array: + len: 5 + stride: 1 + enum: WUPP + - name: WUPPUPD + description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." + bit_offset: 16 + bit_size: 2 + array: + len: 5 + stride: 2 + enum: WUPPUPD +fieldset/WUSCR: + description: PWR wakeup status clear register + fields: + - name: CWUF + description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 +fieldset/WUSR: + description: PWR wakeup status register + fields: + - name: WUF + description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 +enum/ACTVOS: + bit_size: 2 + variants: + - name: B_0x0 + description: VOS3 (lowest power) + value: 0 + - name: B_0x1 + description: VOS2 + value: 1 + - name: B_0x2 + description: VOS1 + value: 2 + - name: B_0x3 + description: VOS0 (highest frequency) + value: 3 +enum/ALS: + bit_size: 2 + variants: + - name: B_0x0 + description: 1.7 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.5 V + value: 2 + - name: B_0x3 + description: 2.8 V + value: 3 +enum/AVDO: + bit_size: 1 + variants: + - name: B_0x0 + description: "VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits." + value: 0 + - name: B_0x1 + description: "VDDA is lower than the AVD threshold selected with the ALS[2:0] bits." + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: B_0x0 + description: 1.95 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.25 V + value: 2 + - name: B_0x3 + description: 2.4 V + value: 3 + - name: B_0x4 + description: 2.55 V + value: 4 + - name: B_0x5 + description: 2.7 V + value: 5 + - name: B_0x6 + description: 2.85 V + value: 6 + - name: B_0x7 + description: PVD_IN pin + value: 7 +enum/PRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: Read and write to PWR functions can be done by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Read and write to PWR functions can be done by privileged access only. + value: 1 +enum/PVDO: + bit_size: 1 + variants: + - name: B_0x0 + description: "VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits." + value: 0 + - name: B_0x1 + description: "VDD is lower than the PVD threshold selected through the PLS[2:0] bits." + value: 1 +enum/SVOS: + bit_size: 2 + variants: + - name: B_0x0 + description: reserved + value: 0 + - name: B_0x1 + description: SVOS5 scale 5 + value: 1 + - name: B_0x2 + description: SVOS4 scale 4 + value: 2 + - name: B_0x3 + description: SVOS3 scale 3 (default). + value: 3 +enum/VBRS: + bit_size: 1 + variants: + - name: B_0x0 + description: Charge VBAT through a 5 kΩ resistor. + value: 0 + - name: B_0x1 + description: Charge VBAT through a 1.5 kΩ resistor. + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: B_0x0 + description: scale 3 (default) + value: 0 + - name: B_0x1 + description: scale 2 + value: 1 + - name: B_0x2 + description: scale 1 + value: 2 + - name: B_0x3 + description: scale 0 + value: 3 +enum/WUPP: + bit_size: 1 + variants: + - name: B_0x0 + description: detection on high level (rising edge) + value: 0 + - name: B_0x1 + description: detection on low level (falling edge) + value: 1 +enum/WUPPUPD: + bit_size: 2 + variants: + - name: B_0x0 + description: no pull-up + value: 0 + - name: B_0x1 + description: pull-up + value: 1 + - name: B_0x2 + description: pull-down + value: 2 + - name: B_0x3 + description: reserved + value: 3 diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml new file mode 100644 index 0000000..f6c6d70 --- /dev/null +++ b/data/registers/rcc_h5.yaml @@ -0,0 +1,2754 @@ +--- +block/RCC: + description: Reset and clock controller + items: + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI calibration register + byte_offset: 16 + fieldset: HSICFGR + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI calibration register + byte_offset: 24 + fieldset: CSICFGR + - name: CFGR + description: RCC clock configuration register + byte_offset: 28 + fieldset: CFGR + - name: CFGR2 + description: RCC CPU domain clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: PLLCFGR + description: RCC PLL clock source selection register + array: + len: 3 + stride: 4 + byte_offset: 40 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 dividers register + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL1 fractional divider register + array: + len: 3 + stride: 8 + byte_offset: 56 + fieldset: PLLFRACR + - name: CIER + description: RCC clock source interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock source interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock source interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register + byte_offset: 100 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 peripheral reset register + byte_offset: 108 + fieldset: AHB4RSTR + - name: APB1LRSTR + description: RCC APB1 peripheral low reset register + byte_offset: 116 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 peripheral high reset register + byte_offset: 120 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB3RSTR + description: RCC APB4 peripheral reset register + byte_offset: 128 + fieldset: APB3RSTR + - name: AHB1ENR + description: RCC AHB1 peripherals clock register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 peripheral clock register + byte_offset: 140 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 peripheral clock register + byte_offset: 148 + fieldset: AHB4ENR + - name: APB1LENR + description: RCC APB1 peripheral clock register + byte_offset: 156 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 peripheral clock register + byte_offset: 160 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 peripheral clock register + byte_offset: 164 + fieldset: APB2ENR + - name: APB3ENR + description: RCC APB4 peripheral clock register + byte_offset: 168 + fieldset: APB3ENR + - name: AHB1LPENR + description: RCC AHB1 sleep clock register + byte_offset: 176 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 sleep clock register + byte_offset: 180 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 sleep clock register + byte_offset: 188 + fieldset: AHB4LPENR + - name: APB1LLPENR + description: RCC APB1 sleep clock register + byte_offset: 196 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 sleep clock register + byte_offset: 200 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 sleep clock register + byte_offset: 204 + fieldset: APB2LPENR + - name: APB3LPENR + description: RCC APB4 sleep clock register + byte_offset: 208 + fieldset: APB3LPENR + - name: CCIPR1 + description: RCC kernel clock configuration register + byte_offset: 216 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC kernel clock configuration register + byte_offset: 220 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC kernel clock configuration register + byte_offset: 224 + fieldset: CCIPR3 + - name: CCIPR4 + description: RCC kernel clock configuration register + byte_offset: 228 + fieldset: CCIPR4 + - name: CCIPR5 + description: RCC kernel clock configuration register + byte_offset: 232 + fieldset: CCIPR5 + - name: BDCR + description: RCC Backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: RSR + description: RCC reset status register + byte_offset: 244 + fieldset: RSR + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 272 + fieldset: SECCFGR + - name: PRIVCFGR + description: RCC privilege configuration register + byte_offset: 276 + fieldset: PRIVCFGR +fieldset/AHB1ENR: + description: RCC AHB1 peripherals clock register + fields: + - name: GPDMA1EN + description: "GPDMA1 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2EN + description: "GPDMA2 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFEN + description: "Flash interface clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: CORDICEN + description: "CORDIC clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: FMACEN + description: "FMAC clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: ETHEN + description: "ETH clock enable\r Set and reset by software" + bit_offset: 19 + bit_size: 1 + - name: ETHTXEN + description: "ETHTX clock enable\r Set and reset by software" + bit_offset: 20 + bit_size: 1 + - name: ETHRXEN + description: "ETHRX clock enable\r Set and reset by software" + bit_offset: 21 + bit_size: 1 + - name: TZSC1EN + description: "TZSC1 clock enable\r Set and reset by software" + bit_offset: 24 + bit_size: 1 + - name: BKPRAMEN + description: "BKPRAM clock enable\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: DCACHEEN + description: "DCACHE clock enable\r Set and reset by software" + bit_offset: 30 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/AHB1LPENR: + description: RCC AHB1 sleep clock register + fields: + - name: GPDMA1LPEN + description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2LPEN + description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFLPEN + description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCLPEN + description: "CRC clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: CORDICLPEN + description: "CORDIC clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: FMACLPEN + description: "FMAC clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: RAMCFGLPEN + description: "RAMCFG clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: ETHLPEN + description: "ETH clock enable during Sleep mode\r Set and reset by software" + bit_offset: 19 + bit_size: 1 + - name: ETHTXLPEN + description: "ETHTX clock enable during sleep mode\r Set and reset by software" + bit_offset: 20 + bit_size: 1 + - name: ETHRXLPEN + description: "ETHRX clock enable during sleep mode\r Set and reset by software" + bit_offset: 21 + bit_size: 1 + - name: TZSC1LPEN + description: "TZSC1 clock enable during sleep mode\r Set and reset by software" + bit_offset: 24 + bit_size: 1 + - name: BKPRAMLPEN + description: "BKPRAM clock enable during sleep mode\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: ICACHELPEN + description: "ICACHE clock enable during sleep mode\r Set and reset by software" + bit_offset: 29 + bit_size: 1 + - name: DCACHELPEN + description: "DCACHE clock enable during sleep mode\r Set and reset by software" + bit_offset: 30 + bit_size: 1 + - name: SRAM1LPEN + description: "SRAM1 clock enable during sleep mode\r Set and reset by software" + bit_offset: 31 + bit_size: 1 +fieldset/AHB1RSTR: + description: RCC AHB1 reset register + fields: + - name: GPDMA1RST + description: "GPDMA1 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2RST + description: "GPDMA2 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: CRCRST + description: CRC block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: CORDICRST + description: "CORDIC block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: FMACRST + description: "FMAC block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: RAMCFGRST + description: "RAMCFG block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: ETHRST + description: "ETHRST block reset\r Set and reset by software" + bit_offset: 19 + bit_size: 1 + - name: TZSC1RST + description: "TZSC1 reset\r Set and reset by software" + bit_offset: 24 + bit_size: 1 +fieldset/AHB2ENR: + description: RCC AHB2 peripheral clock register + fields: + - name: GPIOAEN + description: "GPIOA clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "GPIOB clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "GPIOC clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "GPIOD clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: "GPIOE clock enable\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: "GPIOF clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: "GPIOG clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: "GPIOH clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: "GPIOI clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: ADC12EN + description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12EN + description: "DAC clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: DCMI_PSSIEN + description: "digital camera interface clock enable (DCMI or PSSI depending which interface is active)\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: AESEN + description: "AES clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: "HASH clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: PKAEN + description: "PKA clock enable\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SAESEN + description: "SAES clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SRAM3EN + description: "SRAM3 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/AHB2LPENR: + description: RCC AHB2 sleep clock register + fields: + - name: GPIOALPEN + description: "GPIOA clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: "GPIOB clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: "GPIOC clock enable during sleep mode\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: "GPIOD clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: "GPIOE clock enable during sleep mode\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: "GPIOF clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: "GPIOG clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: "GPIOH clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: "GPIOI clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: ADC12LPEN + description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12LPEN + description: "DAC clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: DCMI_PSSILPEN + description: "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active)\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: AESLPEN + description: "AES clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: HASHLPEN + description: "HASH clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGLPEN + description: "RNG clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: PKALPEN + description: "PKA clock enable during sleep mode\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SAESLPEN + description: "SAES clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SRAM2LPEN + description: "SRAM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: "SRAM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/AHB2RSTR: + description: RCC AHB2 peripheral reset register + fields: + - name: GPIOARST + description: "GPIOA block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "GPIOB block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "GPIOC block reset\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "GPIOD block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: "GPIOE block reset\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: "GPIOF block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: "GPIOG block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: "GPIOH block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: "GPIOI block reset\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: ADC12RST + description: "ADC1 and 2 blocks reset\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12RST + description: "DAC block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: DCMI_PSSIRST + description: "digital camera interface block reset (DCMI or PSSI depending which interface is active)\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: AESRST + description: "AES block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: "HASH block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "RNG block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: PKARST + description: "PKA block reset\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SAESRST + description: "SAES block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 +fieldset/AHB4ENR: + description: RCC AHB4 peripheral clock register + fields: + - name: OTFDEC1EN + description: "OTFDEC1 clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 delay peripheral clock enable reset + bit_offset: 11 + bit_size: 1 + - name: SDMMC2EN + description: "SDMMC2 and SDMMC2 delay peripheral clock enabled\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: FMCEN + description: "FMC clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI1EN + description: "OCTOSPI1 clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 +fieldset/AHB4LPENR: + description: RCC AHB4 sleep clock register + fields: + - name: OTFDEC1LPEN + description: "OTFDEC1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: SDMMC1LPEN + description: "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode\r Set and reset by software" + bit_offset: 11 + bit_size: 1 + - name: SDMMC2LPEN + description: "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: FMCLPEN + description: "FMC clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI1LPEN + description: "OCTOSPI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 +fieldset/AHB4RSTR: + description: RCC AHB4 peripheral reset register + fields: + - name: OTFDEC1RST + description: "OTFDEC1 block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: SDMMC1RST + description: "SDMMC1 and SDMMC1 delay blocks reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SDMMC2RST + description: "SDMMC2 and SDMMC2 delay blocks reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: FMCRST + description: "FMC block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI1RST + description: "OCTOSPI1 block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 +fieldset/APB1HENR: + description: RCC APB1 peripheral clock register + fields: + - name: UART9EN + description: "UART9 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: UART12EN + description: "UART12 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: DTSEN + description: "DTS clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2EN + description: "LPTIM2 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN12EN + description: "FDCAN1 and FDCAN2 peripheral clock enable\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: UCPDEN + description: "UCPD clock enable\r Set and reset by software." + bit_offset: 23 + bit_size: 1 +fieldset/APB1HLPENR: + description: RCC APB1 sleep clock register + fields: + - name: UART9LPEN + description: "UART9 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: UART12LPEN + description: "UART12 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: DTSLPEN + description: "DTS clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2LPEN + description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN12LPEN + description: "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: UCPDLPEN + description: "UCPD clock enable during sleep mode\r Set and reset by software." + bit_offset: 23 + bit_size: 1 +fieldset/APB1HRSTR: + description: RCC APB1 peripheral high reset register + fields: + - name: UART9RST + description: "UART9 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: UART12RST + description: "UART12 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: DTSRST + description: "DTS block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2RST + description: "LPTIM2 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN12RST + description: "FDCAN1 and FDCAN2 blocks reset\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: UCPDRST + description: "UCPD block reset\r Set and reset by software." + bit_offset: 23 + bit_size: 1 +fieldset/APB1LENR: + description: RCC APB1 peripheral clock register + fields: + - name: TIM2EN + description: "TIM2 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: "TIM4 clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: "TIM5 clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: "TIM6 clock enable\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: "TIM7 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: "TIM12 clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: "TIM13 clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: "TIM14 clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: "SPI2 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: "SPI3 clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: "USART3 clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: "UART4 clock enable\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: "UART5 clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: "I2C2 clock enable\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1EN + description: "I3C1 clock enable\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: "CRS clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: USART6EN + description: "USART6 clock enable\r Set and reset by software." + bit_offset: 25 + bit_size: 1 + - name: USART10EN + description: "USART10 clock enable\r Set and reset by software." + bit_offset: 26 + bit_size: 1 + - name: USART11EN + description: USART11 clock enable + bit_offset: 27 + bit_size: 1 + - name: CECEN + description: "HDMI-CEC clock enable\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: UART7EN + description: "UART7 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: "UART8 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/APB1LLPENR: + description: RCC APB1 sleep clock register + fields: + - name: TIM2LPEN + description: "TIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: "TIM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: "TIM4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: "TIM5 clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: "TIM6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: "TIM7 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: "TIM12 clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: "TIM13 clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: "TIM14 clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: WWDGLPEN + description: "WWDG clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: "SPI2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: "SPI3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: USART2LPEN + description: "USART2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: "USART3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: "UART4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: "UART5 clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: "I2C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: "I2C2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1LPEN + description: "I3C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSLPEN + description: "CRS clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: USART6LPEN + description: "USART6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 25 + bit_size: 1 + - name: USART10LPEN + description: "USART10 clock enable during sleep mode\r Set and reset by software." + bit_offset: 26 + bit_size: 1 + - name: USART11LPEN + description: "USART11 clock enable during sleep mode\r Set and reset by software." + bit_offset: 27 + bit_size: 1 + - name: CECLPEN + description: "HDMI-CEC clock enable during sleep mode\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: UART7LPEN + description: "UART7 clock enable during sleep mode\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: "UART8 clock enable during sleep mode\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/APB1LRSTR: + description: RCC APB1 peripheral low reset register + fields: + - name: TIM2RST + description: "TIM2 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: "TIM4 block reset\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: "TIM5 block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: "TIM6 block reset\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: "TIM7 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: "TIM12 block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: "TIM13 block reset t\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: "TIM14 block reset\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: SPI2RST + description: "SPI2 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: "SPI3 block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: "USART2 block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: "USART3 block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: "UART4 block reset\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: "UART5 block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: "I2C1 block reset\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: "I2C2 block reset\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1RST + description: "I3C1 block reset\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: "CRS block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: USART6RST + description: "USART6 block reset\r Set and reset by software." + bit_offset: 25 + bit_size: 1 + - name: USART10RST + description: "USART10 block reset\r Set and reset by software." + bit_offset: 26 + bit_size: 1 + - name: USART11RST + description: "USART11 block reset\r Set and reset by software." + bit_offset: 27 + bit_size: 1 + - name: CECRST + description: "HDMI-CEC block reset\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: UART7RST + description: "UART7 block reset\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: "UART8 block reset\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/APB2ENR: + description: RCC APB2 peripheral clock register + fields: + - name: TIM1EN + description: "TIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: "TIM8 clock enable\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: "USART1 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: "TIM15 clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: "TIM16 clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM17 clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SPI4EN + description: "SPI4 clock enable\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SPI6EN + description: "SPI6 clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: "SAI1 clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: "SAI2 clock enable\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBFSEN + description: "USBFS clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB2LPENR: + description: RCC APB2 sleep clock register + fields: + - name: TIM1LPEN + description: "TIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: "SPI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8LPEN + description: "TIM8 clock enable during sleep mode\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: USART1LPEN + description: "USART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15LPEN + description: "TIM15 clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: "TIM16 clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: "TIM17 clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SPI4LPEN + description: "SPI4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SPI6LPEN + description: "SPI6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: "SAI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2LPEN + description: "SAI2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: USBFSLPEN + description: "USBFS clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB2RSTR: + description: RCC APB2 peripheral reset register + fields: + - name: TIM1RST + description: "TIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 block reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: "TIM8 block reset\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: "USART1 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: "TIM15 block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: "TIM16 block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM17 block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SPI4RST + description: "SPI4 block reset\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SPI6RST + description: "SPI6 block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: "SAI1 block reset\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: "SAI2 block reset\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: USBFSRST + description: "USBFS block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB3ENR: + description: RCC APB4 peripheral clock register + fields: + - name: SBSEN + description: "SBS clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: SPI5EN + description: "SPI5 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3EN + description: "I2C3 clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: I2C4EN + description: "I2C4 clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3EN + description: "LPTIM3 clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4EN + description: "LPTIM4 clock enable\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: LPTIM5EN + description: "LPTIM5 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: LPTIM6EN + description: "LPTIM6 clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VREFEN + description: "VREF clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBEN + description: "RTC APB interface clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 +fieldset/APB3LPENR: + description: RCC APB3 sleep clock register + fields: + - name: SBSLPEN + description: "SBS clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: SPI5LPEN + description: "SPI5 clock enable during Slsleepeep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1LPEN + description: "LPUART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3LPEN + description: "I2C3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: I2C4LPEN + description: "I2C4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3LPEN + description: "LPTIM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4LPEN + description: "LPTIM4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: LPTIM5LPEN + description: "LPTIM5 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: LPTIM6LPEN + description: "LPTIM6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VREFLPEN + description: "VREF clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBLPEN + description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 +fieldset/APB3RSTR: + description: RCC APB3 peripheral reset register + fields: + - name: SBSRST + description: "SBS block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: SPI5RST + description: "SPI5 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3RST + description: "I2C3 block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: I2C4RST + description: "I2C4 block reset\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3RST + description: "LPTIM3 block reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4RST + description: "LPTIM4 block reset\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: LPTIM5RST + description: "LPTIM5 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: LPTIM6RST + description: "LPTIM6 block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VREFRST + description: "VREF block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 +fieldset/BDCR: + description: RCC Backup domain control register + fields: + - name: LSEON + description: "LSE oscillator enabled\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." + bit_offset: 6 + bit_size: 1 + - name: LSEEXT + description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." + bit_offset: 7 + bit_size: 1 + enum: LSEEXT + - name: RTCSEL + description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: "RTC clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VSWRST + description: "VSwitch domain software reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." + bit_offset: 27 + bit_size: 1 +fieldset/CCIPR1: + description: RCC kernel clock configuration register + fields: + - name: USART1SEL + description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: USARTSEL + - name: USART3SEL + description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: USARTSEL + - name: UART4SEL + description: "UART4 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 9 + bit_size: 3 + enum: UARTSEL + - name: UART5SEL + description: "UART5 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: UARTSEL + - name: USART6SEL + description: "USART6 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 15 + bit_size: 3 + enum: USARTSEL + - name: UART7SEL + description: "UART7 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 18 + bit_size: 3 + enum: UARTSEL + - name: UART8SEL + description: "UART8 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 21 + bit_size: 3 + enum: UARTSEL + - name: UART9SEL + description: "UART9 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: UARTSEL + - name: USART10SEL + description: "USART10 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 27 + bit_size: 3 + enum: USARTSEL + - name: TIMICSEL + description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software." + bit_offset: 31 + bit_size: 1 + enum: TIMICSEL +fieldset/CCIPR2: + description: RCC kernel clock configuration register + fields: + - name: USART11SEL + description: "USART11 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: USARTSEL + - name: USART12SEL + description: "USART12 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 4 + bit_size: 3 + enum: USARTSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 8 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM2SEL + description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM3SEL + description: "LPTIM3 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 16 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM4SEL + description: "LPTIM4 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 20 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM5SEL + description: "LPTIM5 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM6SEL + description: "LPTIM6 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 28 + bit_size: 3 + enum: LPTIMSEL +fieldset/CCIPR3: + description: RCC kernel clock configuration register + fields: + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: SPI1SEL + - name: SPI2SEL + description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: SPI2SEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: SPI3SEL + - name: SPI4SEL + description: "SPI4 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 9 + bit_size: 3 + enum: SPI4SEL + - name: SPI5SEL + description: "SPI5 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: SPI5SEL + - name: SPI6SEL + description: "SPI6 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 15 + bit_size: 3 + enum: SPI6SEL + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: LPUARTSEL +fieldset/CCIPR4: + description: RCC kernel clock configuration register + fields: + - name: OCTOSPI1SEL + description: "OCTOSPI1 kernel clock source selection\r Set and reset by software." + bit_offset: 0 + bit_size: 2 + enum: OCTOSPISEL + - name: SYSTICKSEL + description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." + bit_offset: 2 + bit_size: 2 + enum: SYSTICKSEL + - name: USBFSSEL + description: USBFS kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: USBFSSEL + - name: SDMMC1SEL + description: SDMMC1 kernel clock source selection + bit_offset: 6 + bit_size: 1 + enum: SDMMCSEL + - name: SDMMC2SEL + description: SDMMC2 kernel clock source selection + bit_offset: 7 + bit_size: 1 + enum: SDMMCSEL + - name: I2C1SEL + description: I2C1 kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: I2C2 kernel clock source selection + bit_offset: 18 + bit_size: 2 + enum: ICSEL + - name: I2C3SEL + description: I2C3 kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: ICSEL + - name: I2C4SEL + description: I2C4 kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: ICSEL + - name: I3C1SEL + description: I3C1 kernel clock source selection + bit_offset: 24 + bit_size: 2 + enum: ICSEL +fieldset/CCIPR5: + description: RCC kernel clock configuration register + fields: + - name: ADCDACSEL + description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: ADCDACSEL + - name: DACSEL + description: DAC hold clock + bit_offset: 3 + bit_size: 1 + enum: DACSEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: RNGSEL + - name: CECSEL + description: HSMI-CEC kernel clock source selection + bit_offset: 6 + bit_size: 2 + enum: CECSEL + - name: FDCAN12SEL + description: FDCAN1 and FDCAN2 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: FDCANSEL + - name: SAI1SEL + description: "SAI1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 16 + bit_size: 3 + enum: SAISEL + - name: SAI2SEL + description: "SAI2 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 19 + bit_size: 3 + enum: SAISEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 30 + bit_size: 2 + enum: CKPERSEL +fieldset/CFGR: + description: RCC clock configuration register + fields: + - name: SW + description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." + bit_offset: 7 + bit_size: 1 + enum: STOPKERWUCK + - name: RTCPRE + description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." + bit_offset: 8 + bit_size: 6 + - name: TIMPRE + description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 29 + bit_size: 3 + enum: MCO2 +fieldset/CFGR2: + description: RCC CPU domain clock configuration register 2 + fields: + - name: HPRE + description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE3 + description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" + bit_offset: 12 + bit_size: 3 + enum: PPRE + - name: AHB1DIS + description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" + bit_offset: 16 + bit_size: 1 + - name: AHB2DIS + description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" + bit_offset: 17 + bit_size: 1 + - name: AHB4DIS + description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" + bit_offset: 19 + bit_size: 1 + - name: APB1DIS + description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" + bit_offset: 20 + bit_size: 1 + - name: APB2DIS + description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" + bit_offset: 21 + bit_size: 1 + - name: APB3DIS + description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" + bit_offset: 22 + bit_size: 1 +fieldset/CICR: + description: RCC clock source interrupt clear register + fields: + - name: LSIRDYC + description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: HSECSSC + description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: RCC clock source interrupt enable register + fields: + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYIE + description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 +fieldset/CIFR: + description: RCC clock source interrupt flag register + fields: + - name: LSIRDYF + description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYF + description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: HSECSSF + description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: RCC clock control register + fields: + - name: HSION + description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." + bit_offset: 1 + bit_size: 1 + - name: HSIKERON + description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." + bit_offset: 5 + bit_size: 1 + - name: CSION + description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 8 + bit_size: 1 + - name: CSIRDY + description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." + bit_offset: 9 + bit_size: 1 + - name: CSIKERON + description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." + bit_offset: 10 + bit_size: 1 + - name: HSI48ON + description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." + bit_offset: 13 + bit_size: 1 + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: HSECSSON + description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." + bit_offset: 19 + bit_size: 1 + - name: HSEEXT + description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." + bit_offset: 20 + bit_size: 1 + enum: HSEEXT + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 +fieldset/CRRCR: + description: RCC clock recovery RC register + fields: + - name: HSI48CAL + description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." + bit_offset: 0 + bit_size: 10 +fieldset/CSICFGR: + description: RCC CSI calibration register + fields: + - name: CSICAL + description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." + bit_offset: 0 + bit_size: 8 + - name: CSITRIM + description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." + bit_offset: 16 + bit_size: 6 +fieldset/HSICFGR: + description: RCC HSI calibration register + fields: + - name: HSICAL + description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." + bit_offset: 16 + bit_size: 7 +fieldset/PLLCFGR: + description: RCC PLL clock source selection register + fields: + - name: PLLSRC + description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." + bit_offset: 4 + bit_size: 1 + - name: PLLVCOSEL + description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 5 + bit_size: 1 + enum: PLLVCOSEL + - name: DIVM + description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." + bit_offset: 8 + bit_size: 6 + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 +fieldset/PLLDIVR: + description: RCC PLL1 dividers register + fields: + - name: PLLN + description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 +fieldset/PLLFRACR: + description: RCC PLL1 fractional divider register + fields: + - name: PLLFRACN + description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" + bit_offset: 3 + bit_size: 13 +fieldset/PRIVCFGR: + description: RCC privilege configuration register + fields: + - name: SPRIV + description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: SPRIV + - name: NSPRIV + description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: NSPRIV +fieldset/RSR: + description: RCC reset status register + fields: + - name: RMVF + description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." + bit_offset: 23 + bit_size: 1 + - name: PINRSTF + description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 +fieldset/SECCFGR: + description: RCC secure configuration register + fields: + - name: HSISEC + description: "HSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + enum: SEC + - name: HSESEC + description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + enum: SEC + - name: CSISEC + description: "CSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + enum: SEC + - name: LSISEC + description: "LSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + enum: SEC + - name: LSESEC + description: "LSE clock configuration and status bits security\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + enum: SEC + - name: SYSCLKSEC + description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + enum: SEC + - name: PRESCSEC + description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + enum: SEC + - name: PLLSEC + description: "PLL1 clock configuration and status bits security\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: SEC + - name: HSI48SEC + description: "HSI48 clock configuration and status bits security\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + enum: SEC + - name: RMVFSEC + description: "Remove reset flag security\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: CKPERSELSEC + description: "per_ck selection security\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + enum: SEC +enum/ADCDACSEL: + bit_size: 3 + variants: + - name: HCLK + description: rcc_hclk selected as kernel clock (default after reset) + value: 0 + - name: SYSCLK + description: sys_ck selected as kernel clock + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 2 + - name: HSE + description: hse_ck selected as kernel clock + value: 3 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 4 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 5 +enum/CECSEL: + bit_size: 2 + variants: + - name: LSE + description: lse_ck selected as kernel clock (default after reset) + value: 0 + - name: LSI_KER + description: lsi_ker_ck selected as kernel clock + value: 1 + - name: CSI_KER_DIV_122 + description: csi_ker_ck/122 selected as kernel clock + value: 2 +enum/CKPERSEL: + bit_size: 2 + variants: + - name: HSI + description: hsi_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: CSI + description: csi_ker_ck selected as kernel clock + value: 1 + - name: HSE + description: hse_ck selected as kernel clock + value: 2 +enum/DACSEL: + bit_size: 1 + variants: + - name: DAC_HOLD + description: dac_hold_ck selected as kernel clock (default after reset) + value: 0 + - name: DAC_HOLD_2 + description: dac_hold_ck selected as kernel clock + value: 1 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: hse_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 2 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 +enum/HSEEXT: + bit_size: 1 + variants: + - name: Analog + description: HSE in analog mode (default after reset) + value: 0 + - name: Digital + description: HSE in digital mode + value: 1 +enum/HSIDIV: + bit_size: 2 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 +enum/ICSEL: + bit_size: 2 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 +enum/LPTIMSEL: + bit_size: 3 + variants: + - name: RCC_PCLK3 + description: rcc_pclk3 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPUARTSEL: + bit_size: 3 + variants: + - name: RCC_PCLK3 + description: rcc_pclk3 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 1 + - name: PLL3_1 + description: pll3_q_ck selected as kernel clock + value: 2 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 3 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 4 + - name: LSE + description: lse_ck selected as kernel clock + value: 5 +enum/LSCOSEL: + bit_size: 1 + variants: + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 +enum/LSEEXT: + bit_size: 1 + variants: + - name: Analog + description: LSE in analog mode (default after Backup domain reset) + value: 0 + - name: Digital + description: LSE in digital mode (do not use if RTC is active). + value: 1 +enum/MCO1: + bit_size: 3 + variants: + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 +enum/MCO2: + bit_size: 3 + variants: + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 +enum/NSPRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Read and write to RCC non-secure functions can be done by privileged access only + value: 1 +enum/OCTOSPISEL: + bit_size: 2 + variants: + - name: RCC_HCLK4 + description: rcc_hclk4 selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 2 + - name: PER_CLK + description: per_ck selected as kernel clock + value: 3 +enum/PLLRGE: + bit_size: 2 + variants: + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 +enum/PLLSRC: + bit_size: 2 + variants: + - name: None + description: no clock send to DIVMx divider and PLLs (default after reset) + value: 0 + - name: HSI + description: HSI selected as PLL clock (hsi_ck) + value: 1 + - name: CSI + description: CSI selected as PLL clock (csi_ck) + value: 2 + - name: HSE + description: HSE selected as PLL clock (hse_ck) + value: 3 +enum/PLLVCOSEL: + bit_size: 1 + variants: + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div2 + description: rcc_pclk3 = rcc_hclk1 / 2 + value: 4 + - name: Div4 + description: rcc_pclk3 = rcc_hclk1 / 4 + value: 5 + - name: Div8 + description: rcc_pclk3 = rcc_hclk1 / 8 + value: 6 + - name: Div16 + description: rcc_pclk3 = rcc_hclk1 / 16 + value: 7 +enum/RNGSEL: + bit_size: 2 + variants: + - name: HSI48_KER + description: hsi48_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: LSE + description: lse_ck selected as kernel clock + value: 2 + - name: LSI_KER + description: lsi_ker_ck selected as kernel clock + value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: None + description: no clock (default after Backup domain reset) + value: 0 + - name: LSE + description: LSE selected as RTC clock + value: 1 + - name: LSI + description: LSI selected as RTC clock + value: 2 + - name: HSE_DIV_RTCPRE + description: HSE divided by RTCPRE value selected as RTC clock + value: 3 +enum/SAISEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 +enum/SDMMCSEL: + bit_size: 1 + variants: + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 1 +enum/SEC: + bit_size: 1 + variants: + - name: NonSecure + description: non secure + value: 0 + - name: Secure + description: secure + value: 1 +enum/SPI1SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 +enum/SPI2SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 +enum/SPI3SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 +enum/SPI4SEL: + bit_size: 3 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/SPI5SEL: + bit_size: 3 + variants: + - name: RCC_PCLK3 + description: rcc_pclk3 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/SPI6SEL: + bit_size: 3 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/SPRIV: + bit_size: 1 + variants: + - name: Any + description: Read and write to RCC secure functions can be done by privileged or unprivileged access. + value: 0 + - name: Privileged + description: Read and write to RCC secure functions can be done by privileged access only + value: 1 +enum/STOPKERWUCK: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as wakeup clock from system Stop (default after reset) + value: 0 + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 +enum/SW: + bit_size: 3 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 +enum/SYSTICKSEL: + bit_size: 2 + variants: + - name: HCLK_DIV_8 + description: rcc_hclk/8 selected as clock source (default after reset) + value: 0 + - name: LSI_KER + description: "lsi_ker_ck[1] selected as clock source" + value: 1 + - name: LSE + description: "lse_ck[1] selected as clock source" + value: 2 +enum/TIMICSEL: + bit_size: 1 + variants: + - name: B_0x0 + description: No internal clock available for timers input capture (default after reset) + value: 0 + - name: B_0x1 + description: "hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture" + value: 1 +enum/TIMPRE: + bit_size: 1 + variants: + - name: DefaultX2 + description: "The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)" + value: 0 + - name: DefaultX4 + description: "The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2" + value: 1 +enum/UARTSEL: + bit_size: 3 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USARTSEL: + bit_size: 3 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USBFSSEL: + bit_size: 2 + variants: + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml new file mode 100644 index 0000000..c0bf504 --- /dev/null +++ b/data/registers/rcc_h50.yaml @@ -0,0 +1,1748 @@ +--- +block/RCC: + description: Reset and clock controller + items: + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI calibration register + byte_offset: 16 + fieldset: HSICFGR + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI calibration register + byte_offset: 24 + fieldset: CSICFGR + - name: CFGR + description: RCC clock configuration register + byte_offset: 28 + fieldset: CFGR + - name: CFGR2 + description: RCC CPU domain clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: PLLCFGR + description: RCC PLL clock source selection register + array: + len: 2 + stride: 4 + byte_offset: 40 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 dividers register + array: + len: 2 + stride: 8 + byte_offset: 52 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL1 fractional divider register + array: + len: 2 + stride: 8 + byte_offset: 56 + fieldset: PLLFRACR + - name: CIER + description: RCC clock source interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock source interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock source interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register + byte_offset: 100 + fieldset: AHB2RSTR + - name: APB1LRSTR + description: RCC APB1 peripheral low reset register + byte_offset: 116 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 peripheral high reset register + byte_offset: 120 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB3RSTR + description: RCC APB3 peripheral reset register + byte_offset: 128 + fieldset: APB3RSTR + - name: AHB1ENR + description: RCC AHB1 peripherals clock register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 peripheral clock register + byte_offset: 140 + fieldset: AHB2ENR + - name: APB1LENR + description: RCC APB1 peripheral clock register + byte_offset: 156 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 peripheral clock register + byte_offset: 160 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 peripheral clock register + byte_offset: 164 + fieldset: APB2ENR + - name: APB3ENR + description: RCC APB3 peripheral clock register + byte_offset: 168 + fieldset: APB3ENR + - name: AHB1LPENR + description: RCC AHB1 sleep clock register + byte_offset: 176 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 sleep clock register + byte_offset: 180 + fieldset: AHB2LPENR + - name: APB1LLPENR + description: RCC APB1 sleep clock register + byte_offset: 196 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 sleep clock register + byte_offset: 200 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 sleep clock register + byte_offset: 204 + fieldset: APB2LPENR + - name: APB3LPENR + description: RCC APB3 sleep clock register + byte_offset: 208 + fieldset: APB3LPENR + - name: CCIPR1 + description: RCC kernel clock configuration register + byte_offset: 216 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC kernel clock configuration register + byte_offset: 220 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC kernel clock configuration register + byte_offset: 224 + fieldset: CCIPR3 + - name: CCIPR4 + description: RCC kernel clock configuration register + byte_offset: 228 + fieldset: CCIPR4 + - name: CCIPR5 + description: RCC kernel clock configuration register + byte_offset: 232 + fieldset: CCIPR5 + - name: BDCR + description: RCC Backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: RSR + description: RCC reset status register + byte_offset: 244 + fieldset: RSR +fieldset/AHB1ENR: + description: RCC AHB1 peripherals clock register + fields: + - name: GPDMA1EN + description: "GPDMA1 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2EN + description: "GPDMA2 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFEN + description: "Flash interface clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: BKPRAMEN + description: "BKPRAM clock enable\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 +fieldset/AHB1LPENR: + description: RCC AHB1 sleep clock register + fields: + - name: GPDMA1LPEN + description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2LPEN + description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFLPEN + description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCLPEN + description: "CRC clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: RAMCFGLPEN + description: "RAMCFG clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: BKPRAMLPEN + description: "BKPRAM clock enable during sleep mode\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: ICACHELPEN + description: "ICACHE clock enable during sleep mode\r Set and reset by software" + bit_offset: 29 + bit_size: 1 + - name: SRAM1LPEN + description: "SRAM1 clock enable during sleep mode\r Set and reset by software" + bit_offset: 31 + bit_size: 1 +fieldset/AHB1RSTR: + description: RCC AHB1 reset register + fields: + - name: GPDMA1RST + description: "GPDMA1 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2RST + description: "GPDMA2 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: CRCRST + description: CRC block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: RAMCFGRST + description: "RAMCFG block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 +fieldset/AHB2ENR: + description: RCC AHB2 peripheral clock register + fields: + - name: GPIOAEN + description: "GPIOA clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "GPIOB clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "GPIOC clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "GPIOD clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOHEN + description: "GPIOH clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: ADC1EN + description: "ADC1 peripherals clock enabled\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12EN + description: "DAC clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: HASHEN + description: "HASH clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 +fieldset/AHB2LPENR: + description: RCC AHB2 sleep clock register + fields: + - name: GPIOALPEN + description: "GPIOA clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: "GPIOB clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: "GPIOC clock enable during sleep mode\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: "GPIOD clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOHLPEN + description: "GPIOH clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: ADC1LPEN + description: "ADC1 peripherals clock enable during sleep mode\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12LPEN + description: "DAC clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: HASHLPEN + description: "HASH clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGLPEN + description: "RNG clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SRAM2LPEN + description: "SRAM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 30 + bit_size: 1 +fieldset/AHB2RSTR: + description: RCC AHB2 peripheral reset register + fields: + - name: GPIOARST + description: "GPIOA block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "GPIOB block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "GPIOC block reset\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "GPIOD block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOHRST + description: "GPIOH block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: ADC1RST + description: "ADC1 block reset\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12RST + description: "DAC block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: HASHRST + description: "HASH block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "RNG block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 +fieldset/APB1HENR: + description: RCC APB1 peripheral clock register + fields: + - name: DTSEN + description: "DTS clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2EN + description: "LPTIM2 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN1EN + description: "FDCAN1 peripheral clock enable\r Set and reset by software." + bit_offset: 9 + bit_size: 1 +fieldset/APB1HLPENR: + description: RCC APB1 sleep clock register + fields: + - name: DTSLPEN + description: "DTS clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2LPEN + description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN1LPEN + description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software." + bit_offset: 9 + bit_size: 1 +fieldset/APB1HRSTR: + description: RCC APB1 peripheral high reset register + fields: + - name: DTSRST + description: "DTS block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2RST + description: "LPTIM2 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN1RST + description: "FDCAN1 block reset\r Set and reset by software." + bit_offset: 9 + bit_size: 1 +fieldset/APB1LENR: + description: RCC APB1 peripheral clock register + fields: + - name: TIM2EN + description: "TIM2 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: "TIM6 clock enable\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: "TIM7 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: OPAMPEN + description: "OPAMP clock enable\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: SPI2EN + description: "SPI2 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: "SPI3 clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: COMPEN + description: "COMP clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: "USART3 clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: "I2C2 clock enable\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1EN + description: "I3C1 clock enable\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: "CRS clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB1LLPENR: + description: RCC APB1 sleep clock register + fields: + - name: TIM2LPEN + description: "TIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: "TIM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM6LPEN + description: "TIM6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: "TIM7 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGLPEN + description: "WWDG clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: OPAMPLPEN + description: "OPAMP clock enable during sleep mode\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: SPI2LPEN + description: "SPI2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: "SPI3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: COMPLPEN + description: "COMP clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: "USART2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: "USART3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: I2C1LPEN + description: "I2C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: "I2C2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1LPEN + description: "I3C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSLPEN + description: "CRS clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB1LRSTR: + description: RCC APB1 peripheral low reset register + fields: + - name: TIM2RST + description: "TIM2 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: "TIM6 block reset\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: "TIM7 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: OPAMPRST + description: "OPAMP block reset\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: SPI2RST + description: "SPI2 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: "SPI3 block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: COMPRST + description: "COMP block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: "USART2 block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: "USART3 block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: I2C1RST + description: "I2C1 block reset\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: "I2C2 block reset\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1RST + description: "I3C1 block reset\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: "CRS block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB2ENR: + description: RCC APB2 peripheral clock register + fields: + - name: TIM1EN + description: "TIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: "USART1 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: USBFSEN + description: "USBFS clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB2LPENR: + description: RCC APB2 sleep clock register + fields: + - name: TIM1LPEN + description: "TIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: "SPI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: USART1LPEN + description: "USART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: USBFSLPEN + description: "USBFS clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB2RSTR: + description: RCC APB2 peripheral reset register + fields: + - name: TIM1RST + description: "TIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 block reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: "USART1 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: USBFSRST + description: "USBFS block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 +fieldset/APB3ENR: + description: RCC APB3 peripheral clock register + fields: + - name: SBSEN + description: "SBS clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I3C2EN + description: "I3C2EN clock enable\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: VREFEN + description: "VREF clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBEN + description: "RTC APB interface clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 +fieldset/APB3LPENR: + description: RCC APB3 sleep clock register + fields: + - name: SBSLPEN + description: "SBS clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: "LPUART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I3C2LPEN + description: "I3C2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: LPTIM1LPEN + description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: VREFLPEN + description: "VREF clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBLPEN + description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 +fieldset/APB3RSTR: + description: RCC APB3 peripheral reset register + fields: + - name: SBSRST + description: "SBS block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I3C2RST + description: "I3C2RST block reset\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: VREFRST + description: "VREF block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 +fieldset/BDCR: + description: RCC Backup domain control register + fields: + - name: LSEON + description: "LSE oscillator enabled\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." + bit_offset: 6 + bit_size: 1 + - name: LSEEXT + description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." + bit_offset: 7 + bit_size: 1 + enum: LSEEXT + - name: RTCSEL + description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: "RTC clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VSWRST + description: "VSwitch domain software reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." + bit_offset: 27 + bit_size: 1 +fieldset/CCIPR1: + description: RCC kernel clock configuration register + fields: + - name: USART1SEL + description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: USARTSEL + - name: USART3SEL + description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: USARTSEL + - name: TIMICSEL + description: "TIM2, TIM3 and LPTIM2 input capture source selection\r Set and reset by software." + bit_offset: 31 + bit_size: 1 + enum: TIMICSEL +fieldset/CCIPR2: + description: RCC kernel clock configuration register + fields: + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 8 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM2SEL + description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: LPTIMSEL +fieldset/CCIPR3: + description: RCC kernel clock configuration register + fields: + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: SPISEL + - name: SPI2SEL + description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: SPISEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: SPISEL + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: LPUARTSEL +fieldset/CCIPR4: + description: RCC kernel clock configuration register + fields: + - name: SYSTICKSEL + description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." + bit_offset: 2 + bit_size: 2 + enum: SYSTICKSEL + - name: USBFSSEL + description: USBFS kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: USBFSSEL + - name: I2C1SEL + description: I2C1 kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: I2C2 kernel clock source selection + bit_offset: 18 + bit_size: 2 + enum: ICSEL + - name: I3C1SEL + description: I3C1 kernel clock source selection + bit_offset: 24 + bit_size: 2 + enum: ICSEL + - name: I3C2SEL + description: I3C2 kernel clock source selection + bit_offset: 26 + bit_size: 2 + enum: ICSEL +fieldset/CCIPR5: + description: RCC kernel clock configuration register + fields: + - name: ADCDACSEL + description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: ADCDACSEL + - name: DACSEL + description: DAC hold clock + bit_offset: 3 + bit_size: 1 + enum: DACSEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: RNGSEL + - name: FDCAN1SEL + description: FDCAN1 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: FDCANSEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 30 + bit_size: 2 + enum: CKPERSEL +fieldset/CFGR: + description: RCC clock configuration register + fields: + - name: SW + description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." + bit_offset: 7 + bit_size: 1 + enum: STOPKERWUCK + - name: RTCPRE + description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." + bit_offset: 8 + bit_size: 6 + - name: TIMPRE + description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 29 + bit_size: 3 + enum: MCO2 +fieldset/CFGR2: + description: RCC CPU domain clock configuration register 2 + fields: + - name: HPRE + description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE3 + description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" + bit_offset: 12 + bit_size: 3 + enum: PPRE + - name: AHB1DIS + description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" + bit_offset: 16 + bit_size: 1 + - name: AHB2DIS + description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" + bit_offset: 17 + bit_size: 1 + - name: AHB4DIS + description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" + bit_offset: 19 + bit_size: 1 + - name: APB1DIS + description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" + bit_offset: 20 + bit_size: 1 + - name: APB2DIS + description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" + bit_offset: 21 + bit_size: 1 + - name: APB3DIS + description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" + bit_offset: 22 + bit_size: 1 +fieldset/CICR: + description: RCC clock source interrupt clear register + fields: + - name: LSIRDYC + description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." + bit_offset: 6 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: HSECSSC + description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: RCC clock source interrupt enable register + fields: + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYIE + description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." + bit_offset: 6 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/CIFR: + description: RCC clock source interrupt flag register + fields: + - name: LSIRDYF + description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYF + description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." + bit_offset: 6 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: HSECSSF + description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: RCC clock control register + fields: + - name: HSION + description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." + bit_offset: 1 + bit_size: 1 + - name: HSIKERON + description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." + bit_offset: 5 + bit_size: 1 + - name: CSION + description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 8 + bit_size: 1 + - name: CSIRDY + description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." + bit_offset: 9 + bit_size: 1 + - name: CSIKERON + description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." + bit_offset: 10 + bit_size: 1 + - name: HSI48ON + description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." + bit_offset: 13 + bit_size: 1 + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: HSECSSON + description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." + bit_offset: 19 + bit_size: 1 + - name: HSEEXT + description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." + bit_offset: 20 + bit_size: 1 + enum: HSEEXT + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." + bit_offset: 24 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." + bit_offset: 25 + bit_size: 1 + array: + len: 2 + stride: 2 +fieldset/CRRCR: + description: RCC clock recovery RC register + fields: + - name: HSI48CAL + description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." + bit_offset: 0 + bit_size: 10 +fieldset/CSICFGR: + description: RCC CSI calibration register + fields: + - name: CSICAL + description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." + bit_offset: 0 + bit_size: 8 + - name: CSITRIM + description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." + bit_offset: 16 + bit_size: 6 +fieldset/HSICFGR: + description: RCC HSI calibration register + fields: + - name: HSICAL + description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." + bit_offset: 16 + bit_size: 7 +fieldset/PLLCFGR: + description: RCC PLL clock source selection register + fields: + - name: PLLSRC + description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." + bit_offset: 4 + bit_size: 1 + - name: PLLVCOSEL + description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 5 + bit_size: 1 + enum: PLLVCOSEL + - name: DIVM + description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." + bit_offset: 8 + bit_size: 6 + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 +fieldset/PLLDIVR: + description: RCC PLL1 dividers register + fields: + - name: PLLN + description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 +fieldset/PLLFRACR: + description: RCC PLL1 fractional divider register + fields: + - name: PLLFRACN + description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" + bit_offset: 3 + bit_size: 13 +fieldset/RSR: + description: RCC reset status register + fields: + - name: RMVF + description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." + bit_offset: 23 + bit_size: 1 + - name: PINRSTF + description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 +enum/ADCDACSEL: + bit_size: 3 + variants: + - name: HCLK + description: rcc_hclk selected as kernel clock (default after reset) + value: 0 + - name: SYSCLK + description: sys_ck selected as kernel clock + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 2 + - name: HSE + description: hse_ck selected as kernel clock + value: 3 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 4 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 5 +enum/CKPERSEL: + bit_size: 2 + variants: + - name: HSI + description: hsi_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: CSI + description: csi_ker_ck selected as kernel clock + value: 1 + - name: HSE + description: hse_ck selected as kernel clock + value: 2 +enum/DACSEL: + bit_size: 1 + variants: + - name: DAC_HOLD + description: dac_hold_ck selected as kernel clock (default after reset) + value: 0 + - name: DAC_HOLD_2 + description: dac_hold_ck selected as kernel clock + value: 1 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: hse_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 2 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 +enum/HSEEXT: + bit_size: 1 + variants: + - name: Analog + description: HSE in analog mode (default after reset) + value: 0 + - name: Digital + description: HSE in digital mode + value: 1 +enum/HSIDIV: + bit_size: 2 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 +enum/ICSEL: + bit_size: 2 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 +enum/LPTIMSEL: + bit_size: 3 + variants: + - name: RCC_PCLK3 + description: rcc_pclk3 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPUARTSEL: + bit_size: 3 + variants: + - name: RCC_PCLK3 + description: rcc_pclk3 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 1 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 3 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 4 + - name: LSE + description: lse_ck selected as kernel clock + value: 5 +enum/LSCOSEL: + bit_size: 1 + variants: + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 +enum/LSEEXT: + bit_size: 1 + variants: + - name: Analog + description: LSE in analog mode (default after Backup domain reset) + value: 0 + - name: Digital + description: LSE in digital mode (do not use if RTC is active). + value: 1 +enum/MCO1: + bit_size: 3 + variants: + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 +enum/MCO2: + bit_size: 3 + variants: + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 +enum/PLLRGE: + bit_size: 2 + variants: + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 +enum/PLLSRC: + bit_size: 2 + variants: + - name: None + description: no clock send to DIVMx divider and PLLs (default after reset) + value: 0 + - name: HSI + description: HSI selected as PLL clock (hsi_ck) + value: 1 + - name: CSI + description: CSI selected as PLL clock (csi_ck) + value: 2 + - name: HSE + description: HSE selected as PLL clock (hse_ck) + value: 3 +enum/PLLVCOSEL: + bit_size: 1 + variants: + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div2 + description: rcc_pclk3 = rcc_hclk1 / 2 + value: 4 + - name: Div4 + description: rcc_pclk3 = rcc_hclk1 / 4 + value: 5 + - name: Div8 + description: rcc_pclk3 = rcc_hclk1 / 8 + value: 6 + - name: Div16 + description: rcc_pclk3 = rcc_hclk1 / 16 + value: 7 +enum/RNGSEL: + bit_size: 2 + variants: + - name: HSI48_KER + description: hsi48_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: LSE + description: lse_ck selected as kernel clock + value: 2 + - name: LSI_KER + description: lsi_ker_ck selected as kernel clock + value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: None + description: no clock (default after Backup domain reset) + value: 0 + - name: LSE + description: LSE selected as RTC clock + value: 1 + - name: LSI + description: LSI selected as RTC clock + value: 2 + - name: HSE_DIV_RTCPRE + description: HSE divided by RTCPRE value selected as RTC clock + value: 3 +enum/SPISEL: + bit_size: 3 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 +enum/STOPKERWUCK: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as wakeup clock from system Stop (default after reset) + value: 0 + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 +enum/SW: + bit_size: 3 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 +enum/SYSTICKSEL: + bit_size: 2 + variants: + - name: HCLK_DIV_8 + description: rcc_hclk/8 selected as clock source (default after reset) + value: 0 + - name: LSI_KER + description: "lsi_ker_ck[1] selected as clock source" + value: 1 + - name: LSE + description: "lse_ck[1] selected as clock source" + value: 2 +enum/TIMICSEL: + bit_size: 1 + variants: + - name: B_0x0 + description: No internal clock available for timers input capture (default after reset) + value: 0 + - name: B_0x1 + description: "hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture" + value: 1 +enum/TIMPRE: + bit_size: 1 + variants: + - name: Mul1 + description: "The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)" + value: 0 + - name: Mul2 + description: "The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2" + value: 1 +enum/USARTSEL: + bit_size: 3 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USBFSSEL: + bit_size: 2 + variants: + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 diff --git a/data/registers/sbs_h5.yaml b/data/registers/sbs_h5.yaml new file mode 100644 index 0000000..7155467 --- /dev/null +++ b/data/registers/sbs_h5.yaml @@ -0,0 +1,410 @@ +--- +block/SBS: + description: SBS register block + items: + - name: HDPLCR + description: "SBS temporal isolation control register " + byte_offset: 16 + fieldset: HDPLCR + - name: HDPLSR + description: "SBS temporal isolation status register " + byte_offset: 20 + fieldset: HDPLSR + - name: NEXTHDPLCR + description: "SBS next HDPL control register " + byte_offset: 24 + fieldset: NEXTHDPLCR + - name: DBGCR + description: "SBS debug control register " + byte_offset: 32 + fieldset: DBGCR + - name: DBGLOCKR + description: "SBS debug lock register " + byte_offset: 36 + fieldset: DBGLOCKR + - name: RSSCMDR + description: "SBS RSS command register " + byte_offset: 52 + fieldset: RSSCMDR + - name: EPOCHSELCR + description: "SBS EPOCH selection control register " + byte_offset: 160 + fieldset: EPOCHSELCR + - name: SECCFGR + description: "SBS security mode configuration control register " + byte_offset: 192 + fieldset: SECCFGR + - name: PMCR + description: "SBS product mode and configuration register " + byte_offset: 256 + fieldset: PMCR + - name: FPUIMR + description: "SBS FPU interrupt mask register " + byte_offset: 260 + fieldset: FPUIMR + - name: MESR + description: "SBS memory erase status register " + byte_offset: 264 + fieldset: MESR + - name: CCCSR + description: "SBS compensation cell for I/Os control and status register\t" + byte_offset: 272 + fieldset: CCCSR + - name: CCVALR + description: "SBS compensation cell for I/Os value register " + byte_offset: 276 + fieldset: CCVALR + - name: CCSWCR + description: "SBS compensation cell for I/Os software code register\t" + byte_offset: 280 + fieldset: CCSWCR + - name: CFGR2 + description: "SBS Class B register " + byte_offset: 288 + fieldset: CFGR2 + - name: CNSLCKR + description: "SBS CPU non-secure lock register " + byte_offset: 324 + fieldset: CNSLCKR + - name: CSLCKR + description: "SBS CPU secure lock register " + byte_offset: 328 + fieldset: CSLCKR + - name: ECCNMIR + description: "SBS flift ECC NMI mask register " + byte_offset: 332 + fieldset: ECCNMIR +fieldset/CCCSR: + description: "SBS compensation cell for I/Os control and status register\t" + fields: + - name: EN + description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: RDY + description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CS + description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 2 + enum: CS +fieldset/CCSWCR: + description: "SBS compensation cell for I/Os software code register\t" + fields: + - name: SW_ANSRC1 + description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 0 + bit_size: 4 + - name: SW_APSRC1 + description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 4 + bit_size: 4 + - name: SW_ANSRC2 + description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 8 + bit_size: 4 + - name: SW_APSRC2 + description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 12 + bit_size: 4 +fieldset/CCVALR: + description: "SBS compensation cell for I/Os value register " + fields: + - name: ANSRC1 + description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 0 + bit_size: 4 + - name: APSRC1 + description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 4 + bit_size: 4 + - name: ANSRC2 + description: "Compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 8 + bit_size: 4 + - name: APSRC2 + description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 12 + bit_size: 4 +fieldset/CFGR2: + description: "SBS Class B register " + fields: + - name: CLL + description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs." + bit_offset: 0 + bit_size: 1 + - name: SEL + description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17." + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs." + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17." + bit_offset: 3 + bit_size: 1 +fieldset/CNSLCKR: + description: "SBS CPU non-secure lock register " + fields: + - name: LOCKNSVTOR + description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "non-secure MPU register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." + bit_offset: 1 + bit_size: 1 +fieldset/CSLCKR: + description: "SBS CPU secure lock register " + fields: + - name: LOCKSVTAIRCR + description: "VTOR_S and AIRCR register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register." + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: "secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers." + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers." + bit_offset: 2 + bit_size: 1 +fieldset/DBGCR: + description: "SBS debug control register " + fields: + - name: AP_UNLOCK + description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." + bit_offset: 0 + bit_size: 8 + - name: DBG_UNLOCK + description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register." + bit_offset: 8 + bit_size: 8 + - name: DBG_AUTH_HDPL + description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens." + bit_offset: 16 + bit_size: 8 + enum: DBG_AUTH_HDPL + - name: DBG_AUTH_SEC + description: "control debug opening secure/non-secure\r Write 0xB4 to this bitfield to open debug for secure and non-secure.\r Writing any other values only open non-secure." + bit_offset: 24 + bit_size: 8 +fieldset/DBGLOCKR: + description: "SBS debug lock register " + fields: + - name: DBGCFG_LOCK + description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" + bit_offset: 0 + bit_size: 8 + enum: DBGCFG_LOCK +fieldset/ECCNMIR: + description: "SBS flift ECC NMI mask register " + fields: + - name: ECCNMI_MASK_EN + description: NMI behavior setup when a double ECC error occurs on flitf data part + bit_offset: 0 + bit_size: 1 +fieldset/EPOCHSELCR: + description: "SBS EPOCH selection control register " + fields: + - name: EPOCH_SEL + description: "select EPOCH value to be sent to the SAES\r 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time)" + bit_offset: 0 + bit_size: 2 + enum: EPOCH_SEL +fieldset/FPUIMR: + description: "SBS FPU interrupt mask register " + fields: + - name: FPU_IE + description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" + bit_offset: 0 + bit_size: 6 +fieldset/HDPLCR: + description: "SBS temporal isolation control register " + fields: + - name: INCR_HDPL + description: "increment HDPL value\r Other: all other values allow a HDPL level increment." + bit_offset: 0 + bit_size: 8 + enum: INCR_HDPL +fieldset/HDPLSR: + description: "SBS temporal isolation status register " + fields: + - name: HDPL + description: "temporal isolation level\r This bitfield returns the current temporal isolation level." + bit_offset: 0 + bit_size: 8 + enum: HDPL +fieldset/MESR: + description: "SBS memory erase status register " + fields: + - name: MCLR + description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software" + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: "end-of-erase status for ICACHE and PKA RAM\r This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software." + bit_offset: 16 + bit_size: 1 +fieldset/NEXTHDPLCR: + description: "SBS next HDPL control register " + fields: + - name: NEXTHDPL + description: "index to point to a higher HDPL than the current one\r Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details." + bit_offset: 0 + bit_size: 2 +fieldset/PMCR: + description: "SBS product mode and configuration register " + fields: + - name: BOOSTEN + description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches." + bit_offset: 9 + bit_size: 1 + - name: PB6_FMPLUS + description: Fast-mode Plus command on PB(6) + bit_offset: 16 + bit_size: 1 + - name: PB7_FMPLUS + description: Fast-mode Plus command on PB(7) + bit_offset: 17 + bit_size: 1 + - name: PB8_FMPLUS + description: Fast-mode Plus command on PB(8) + bit_offset: 18 + bit_size: 1 + - name: PB9_FMPLUS + description: Fast-mode Plus command on PB(9) + bit_offset: 19 + bit_size: 1 + - name: ETH_SEL_PHY + description: "Ethernet PHY interface selection\r Other: reserved" + bit_offset: 21 + bit_size: 3 + enum: ETH_SEL_PHY +fieldset/RSSCMDR: + description: "SBS RSS command register " + fields: + - name: RSSCMD + description: "RSS command\r The application can use this bitfield to pass on a command to the RSS, executed at the next reset.\r When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value." + bit_offset: 0 + bit_size: 16 +fieldset/SECCFGR: + description: "SBS security mode configuration control register " + fields: + - name: SBSSEC + description: "SBS clock control, memory-erase status register and compensation cell register security enable" + bit_offset: 0 + bit_size: 1 + enum: SEC + - name: CLASSBSEC + description: ClassB security enable + bit_offset: 1 + bit_size: 1 + enum: SEC + - name: FPUSEC + description: "FPU security enable\r Note: This bit can only be written through privilege transaction." + bit_offset: 3 + bit_size: 1 + enum: SEC + - name: SDCE_SEC_EN + description: control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR + bit_offset: 31 + bit_size: 1 +enum/CS: + bit_size: 1 + variants: + - name: Cell + description: Code from the cell (available in the SBS_CCVR) + value: 0 + - name: Software + description: "Code from SBS_CCCR " + value: 1 +enum/DBGCFG_LOCK: + bit_size: 8 + variants: + - name: B_0xB4 + description: Writes to SBS_DBGCR allowed (default) + value: 180 +enum/DBG_AUTH_HDPL: + bit_size: 8 + variants: + - name: B_0x51 + description: HDPL1 + value: 81 + - name: B_0x6F + description: HDPL3 + value: 111 + - name: B_0x8A + description: HDPL2 + value: 138 +enum/EPOCH_SEL: + bit_size: 2 + variants: + - name: B_0x0 + description: SEC_EPOCH counter input selected + value: 0 + - name: B_0x1 + description: NS_EPOCH (non-secure) input selected + value: 1 +enum/ETH_SEL_PHY: + bit_size: 3 + variants: + - name: B_0x0 + description: GMII or MII + value: 0 + - name: B_0x1 + description: reserved (RGMII) + value: 1 + - name: B_0x4 + description: RMII + value: 4 +enum/HDPL: + bit_size: 8 + variants: + - name: B_0x51 + description: "HDPL1, iRoT" + value: 81 + - name: B_0x6F + description: "HDPL3, application (secure/non-secure)" + value: 111 + - name: B_0x8A + description: "HDPL2, uRoT" + value: 138 + - name: B_0xB4 + description: "HDPL0, RSS" + value: 180 +enum/INCR_HDPL: + bit_size: 8 + variants: + - name: B_0x6A + description: recommended value to increment HDPL level by one + value: 106 + - name: B_0xB4 + description: no increment + value: 180 +enum/SEC: + bit_size: 1 + variants: + - name: B_0x0 + description: SBS_CFGR2 register accessible through secure or non-secure transaction + value: 0 + - name: B_0x1 + description: SBS_CFGR2 register only accessible through secure transaction + value: 1 diff --git a/data/registers/sbs_h50.yaml b/data/registers/sbs_h50.yaml new file mode 100644 index 0000000..94d4214 --- /dev/null +++ b/data/registers/sbs_h50.yaml @@ -0,0 +1,288 @@ +--- +block/SBS: + description: "System configuration, boot and security" + items: + - name: HDPLCR + description: SBS temporal isolation control register + byte_offset: 16 + fieldset: HDPLCR + - name: HDPLSR + description: SBS temporal isolation status register + byte_offset: 20 + fieldset: HDPLSR + - name: DBGCR + description: SBS debug control register + byte_offset: 32 + fieldset: DBGCR + - name: DBGLOCKR + description: SBS debug lock register + byte_offset: 36 + fieldset: DBGLOCKR + - name: PMCR + description: SBS product mode and configuration register + byte_offset: 256 + fieldset: PMCR + - name: FPUIMR + description: SBS FPU interrupt mask register + byte_offset: 260 + fieldset: FPUIMR + - name: MESR + description: SBS memory erase status register + byte_offset: 264 + fieldset: MESR + - name: CCCSR + description: SBS compensation cell for I/Os control and status register + byte_offset: 272 + fieldset: CCCSR + - name: CCVALR + description: SBS compensation cell for I/Os value register + byte_offset: 276 + fieldset: CCVALR + - name: CCSWCR + description: SBS compensation cell for I/Os software code register + byte_offset: 280 + fieldset: CCSWCR + - name: CFGR2 + description: SBS Class B register + byte_offset: 288 + fieldset: CFGR2 + - name: CNSLCKR + description: SBS CPU lock register + byte_offset: 324 + fieldset: CNSLCKR + - name: ECCNMIR + description: SBS flift ECC NMI mask register + byte_offset: 332 + fieldset: ECCNMIR +fieldset/CCCSR: + description: SBS compensation cell for I/Os control and status register + fields: + - name: RDY + description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CS + description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 2 + enum: CS + - name: EN + description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 2 +fieldset/CCSWCR: + description: SBS compensation cell for I/Os software code register + fields: + - name: SW_ANSRC1 + description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 0 + bit_size: 4 + - name: SW_APSRC1 + description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 4 + bit_size: 4 + - name: SW_ANSRC2 + description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 8 + bit_size: 4 + - name: SW_APSRC2 + description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 12 + bit_size: 4 +fieldset/CCVALR: + description: SBS compensation cell for I/Os value register + fields: + - name: ANSRC1 + description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 0 + bit_size: 4 + - name: APSRC1 + description: "compensation value for the PMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 4 + bit_size: 4 + - name: ANSRC2 + description: "Compensation value for the NMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 8 + bit_size: 4 + - name: APSRC2 + description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 12 + bit_size: 4 +fieldset/CFGR2: + description: SBS Class B register + fields: + - name: CLL + description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs." + bit_offset: 0 + bit_size: 1 + - name: SEL + description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1." + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs." + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1." + bit_offset: 3 + bit_size: 1 +fieldset/CNSLCKR: + description: SBS CPU lock register + fields: + - name: LOCKNSVTOR + description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "MPU register lock \r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." + bit_offset: 1 + bit_size: 1 +fieldset/DBGCR: + description: SBS debug control register + fields: + - name: AP_UNLOCK + description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." + bit_offset: 0 + bit_size: 8 + - name: DBG_UNLOCK + description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register." + bit_offset: 8 + bit_size: 8 + - name: DBG_AUTH_HDPL + description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens." + bit_offset: 16 + bit_size: 8 + enum: DBG_AUTH_HDPL +fieldset/DBGLOCKR: + description: SBS debug lock register + fields: + - name: DBGCFG_LOCK + description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" + bit_offset: 0 + bit_size: 8 + enum: DBGCFG_LOCK +fieldset/ECCNMIR: + description: SBS flift ECC NMI mask register + fields: + - name: ECCNMI_MASK_EN + description: NMI behavior setup when a double ECC error occurs on flitf data part + bit_offset: 0 + bit_size: 1 +fieldset/FPUIMR: + description: SBS FPU interrupt mask register + fields: + - name: FPU_IE + description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" + bit_offset: 0 + bit_size: 6 +fieldset/HDPLCR: + description: SBS temporal isolation control register + fields: + - name: INCR_HDPL + description: "increment HDPL value\r Other: all other values allow a HDPL level increment." + bit_offset: 0 + bit_size: 8 + enum: INCR_HDPL +fieldset/HDPLSR: + description: SBS temporal isolation status register + fields: + - name: HDPL + description: "temporal isolation level\r This bitfield returns the current temporal isolation level." + bit_offset: 0 + bit_size: 8 + enum: HDPL +fieldset/MESR: + description: SBS memory erase status register + fields: + - name: MCLR + description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software" + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: "end-of-erase status for ICACHE\r This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software." + bit_offset: 16 + bit_size: 1 +fieldset/PMCR: + description: SBS product mode and configuration register + fields: + - name: BOOSTEN + description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r Note: When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches." + bit_offset: 9 + bit_size: 1 + - name: PB6_FMPLUS + description: Fast-mode Plus command on PB(6) + bit_offset: 16 + bit_size: 1 + - name: PB7_FMPLUS + description: Fast-mode Plus command on PB(7) + bit_offset: 17 + bit_size: 1 + - name: PB8_FMPLUS + description: Fast-mode Plus command on PB(8) + bit_offset: 18 + bit_size: 1 +enum/CS: + bit_size: 1 + variants: + - name: Cell + description: Code from the cell (available in SBS_CCVR) + value: 0 + - name: Software + description: Code from SBS_CCCR + value: 1 +enum/DBGCFG_LOCK: + bit_size: 8 + variants: + - name: B_0xB4 + description: Writes to SBS_DBGCR allowed (default) + value: 180 +enum/DBG_AUTH_HDPL: + bit_size: 8 + variants: + - name: B_0x51 + description: HDPL1 + value: 81 + - name: B_0x6F + description: HDPL3 + value: 111 + - name: B_0x8A + description: HDPL2 + value: 138 +enum/HDPL: + bit_size: 8 + variants: + - name: B_0x51 + description: "HDPL1, iRoT" + value: 81 + - name: B_0x6F + description: "HDPL3, application" + value: 111 + - name: B_0x8A + description: "HDPL2, uRoT" + value: 138 + - name: B_0xB4 + description: "HDPL0, RSS" + value: 180 +enum/INCR_HDPL: + bit_size: 8 + variants: + - name: B_0x6A + description: recommended value to increment HDPL level by one + value: 106 + - name: B_0xB4 + description: no increment + value: 180 diff --git a/stm32-data-gen/Cargo.toml b/stm32-data-gen/Cargo.toml index be71f5f..6d45f02 100644 --- a/stm32-data-gen/Cargo.toml +++ b/stm32-data-gen/Cargo.toml @@ -22,3 +22,5 @@ serde_json = "1.0.94" rayon = { version = "1.7.0", optional = true } stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" } ref_thread_local = "0.1.1" +log = "0.4.17" +pretty_env_logger = "0.4.0" diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index ff585d2..ef780af 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -84,6 +84,8 @@ fn chip_name_from_package_name(x: &str) -> String { (regex!("^(STM32L0....).xS$"), "$1"), (regex!("^(STM32H7....).xQ$"), "$1"), (regex!("^(STM32U5....).xQ$"), "$1"), + (regex!("^(STM32H5....).xQ$"), "$1"), + (regex!("^(STM32WBA....).x$"), "$1"), (regex!("^(STM32......).x$"), "$1"), ]; @@ -184,6 +186,8 @@ impl PeriMatcher { ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")), + ("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")), + ("STM32H5.*:SBS:.*", ("sbs", "h5", "SBS")), (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")), (".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")), (".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")), @@ -244,6 +248,8 @@ impl PeriMatcher { ("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")), ("STM32L5.*:RCC:.*", ("rcc", "l5", "RCC")), ("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")), + ("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")), + ("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")), ("STM32WB.*:RCC:.*", ("rcc", "wb", "RCC")), ("STM32WL5.*:RCC:.*", ("rcc", "wl5", "RCC")), ("STM32WLE.*:RCC:.*", ("rcc", "wle", "RCC")), @@ -276,6 +282,8 @@ impl PeriMatcher { ("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")), ("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")), ("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")), + ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")), + ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")), ("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")), ("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")), ("STM32F1.*:FLASH:.*", ("flash", "f1", "FLASH")), @@ -292,6 +300,8 @@ impl PeriMatcher { ("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")), ("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")), ("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")), + ("STM32H50.*:FLASH:.*", ("flash", "h50", "FLASH")), + ("STM32H5.*:FLASH:.*", ("flash", "h5", "FLASH")), ("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")), ("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")), ("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")), @@ -474,13 +484,13 @@ pub fn parse_groups() -> Result<(HashMap, Vec), anyhow: } static NOPELIST: &[&str] = &[ - // Not supported + // Not supported, not planned unless someone wants to do it. "STM32MP", + // Not supported yet, planned. + "STM32WBA", // Does not exist in ST website. No datasheet, no RM. "STM32GBK", "STM32L485", - "STM32U59", - "STM32U5A", // STM32WxM modules. These are based on a chip that's supported on its own, // not sure why we want a separate target for it. "STM32WL5M", @@ -687,10 +697,18 @@ fn process_core( if ["L5", "U5"].contains(&&chip_name[5..7]) { want_nvic_name = "NVIC2" } + if ["H56", "H57"].contains(&&chip_name[5..8]) { + want_nvic_name = "NVIC2" + } want_nvic_name }; - let chip_nvic = group.ips.values().find(|x| x.name == want_nvic_name).unwrap(); + let chip_nvic = group + .ips + .values() + .find(|x| x.name == want_nvic_name) + .ok_or_else(|| format!("couldn't find nvic. chip_name={chip_name} want_nvic_name={want_nvic_name}")) + .unwrap(); // With the current data sources, this value is always either 2 or 4, and never resolves to None let nvic_priority_bits = defines.0.get("__NVIC_PRIO_BITS").map(|bits| *bits as u8); @@ -778,7 +796,7 @@ fn process_core( const GHOST_PERIS: &[&str] = &[ "GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "DMA1", "DMA2", "BDMA", "DMAMUX", - "DMAMUX1", "DMAMUX2", "SYSCFG", "EXTI", "FLASH", "DBGMCU", "CRS", "PWR", "AFIO", "BKP", + "DMAMUX1", "DMAMUX2", "SBS", "SYSCFG", "EXTI", "FLASH", "DBGMCU", "CRS", "PWR", "AFIO", "BKP", ]; for pname in GHOST_PERIS { if let Entry::Vacant(entry) = peri_kinds.entry(pname.to_string()) { @@ -857,7 +875,7 @@ fn process_core( } if let Some(rcc_info) = peripheral_to_clock.match_peri_clock( - ( + &( rcc_block.0.to_string(), rcc_block.1.to_string(), rcc_block.2.to_string(), diff --git a/stm32-data-gen/src/dma.rs b/stm32-data-gen/src/dma.rs index cb89925..3360c78 100644 --- a/stm32-data-gen/src/dma.rs +++ b/stm32-data-gen/src/dma.rs @@ -292,52 +292,57 @@ impl DmaChannels { dma_channels.insert(ff, chip_dma); } - // STM32U5 + // GPDMA - let mut chip_dma = ChipDma { - peripherals: HashMap::new(), - channels: Vec::new(), - }; - - let parsed: HashMap = - serde_yaml::from_str(&std::fs::read_to_string("data/dmamux/U5_GPDMA1.yaml")?)?; - - for (request_name, request_num) in parsed { - let parts: Vec<_> = request_name.split('_').collect(); - let target_peri_name = parts[0]; - let request = { - if parts.len() < 2 { - target_peri_name - } else { - parts[1] - } + for (file, gpdmax, instance) in [ + ("data/dmamux/H5_GPDMA.yaml", "GPDMA1", "STM32H5_dma3_Cube"), + ("data/dmamux/H5_GPDMA.yaml", "GPDMA2", "Instance2_STM32H5_dma3_Cube"), + ("data/dmamux/U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube"), + ] { + let mut chip_dma = ChipDma { + peripherals: HashMap::new(), + channels: Vec::new(), }; - chip_dma - .peripherals - .entry(target_peri_name.to_string()) - .or_default() - .push(stm32_data_serde::chip::core::peripheral::DmaChannel { - signal: request.to_string(), - dma: Some("GPDMA1".to_string()), - channel: None, + + let parsed: HashMap = serde_yaml::from_str(&std::fs::read_to_string(file)?)?; + + for (request_name, request_num) in parsed { + let parts: Vec<_> = request_name.split('_').collect(); + let target_peri_name = parts[0]; + let request = { + if parts.len() < 2 { + target_peri_name + } else { + parts[1] + } + }; + chip_dma + .peripherals + .entry(target_peri_name.to_string()) + .or_default() + .push(stm32_data_serde::chip::core::peripheral::DmaChannel { + signal: request.to_string(), + dma: Some(gpdmax.to_string()), + channel: None, + dmamux: None, + request: Some(request_num), + }); + } + + for i in 0..16 { + chip_dma.channels.push(stm32_data_serde::chip::core::DmaChannels { + name: format!("{gpdmax}_CH{i}"), + dma: gpdmax.to_string(), + channel: i, dmamux: None, - request: Some(request_num), + dmamux_channel: None, + supports_2d: Some(i >= 12), }); - } + } - for i in 0..16 { - chip_dma.channels.push(stm32_data_serde::chip::core::DmaChannels { - name: format!("GPDMA1_CH{i}"), - dma: "GPDMA1".to_string(), - channel: i, - dmamux: None, - dmamux_channel: None, - supports_2d: Some(i >= 12), - }); + dma_channels.insert(instance.to_string(), chip_dma); } - dma_channels.insert("STM32U5_dma3_Cube".to_string(), chip_dma); - Ok(Self(dma_channels)) } } diff --git a/stm32-data-gen/src/interrupts.rs b/stm32-data-gen/src/interrupts.rs index 5773615..93d69f8 100644 --- a/stm32-data-gen/src/interrupts.rs +++ b/stm32-data-gen/src/interrupts.rs @@ -1,5 +1,7 @@ use std::collections::{HashMap, HashSet}; +use log::*; + use crate::regex; mod xml { @@ -48,6 +50,7 @@ impl ChipInterrupts { files.sort(); for f in files { + trace!("parsing {f:?}"); let mut irqs = HashMap::::new(); let file = std::fs::read_to_string(f)?; let parsed: xml::Ip = quick_xml::de::from_str(&file)?; @@ -57,6 +60,7 @@ impl ChipInterrupts { .filter(|param| param.name == "IRQn") .flat_map(|param| param.possible_values) { + trace!(" irq={irq:?}"); let parts = { let mut iter = irq.value.split(':'); let parts = [(); 5].map(|_| iter.next().unwrap()); @@ -64,17 +68,16 @@ impl ChipInterrupts { parts }; - let name = { - let name = parts[0].strip_suffix("_IRQn").unwrap(); + let mut name = parts[0].strip_suffix("_IRQn").unwrap().to_string(); - // Fix typo in STM32Lxx and L083 devices - let contains_rng = || parts[2..].iter().flat_map(|x| x.split(',')).any(|x| x == "RNG"); - if name == "AES_RNG_LPUART1" && !contains_rng() { - "AES_LPUART1" - } else { - name - } - }; + // Fix typo in STM32Lxx and L083 devices + let contains_rng = || parts[2..].iter().flat_map(|x| x.split(',')).any(|x| x == "RNG"); + if name == "AES_RNG_LPUART1" && !contains_rng() { + name = "AES_LPUART1".to_string() + } + + // More typos + let name = name.replace("USAR11", "USART11"); let entry = match irqs.entry(name.to_string()) { std::collections::hash_map::Entry::Occupied(_) => continue, @@ -105,6 +108,11 @@ impl ChipInterrupts { if parsed.version.starts_with("STM32F3") && irq.comment.contains("remap") { continue; } + // not supported + if name == "LSECSSD" { + continue; + } + let mut signals = HashSet::<(String, String)>::new(); if [ "NonMaskableInt", @@ -117,7 +125,7 @@ impl ChipInterrupts { "PendSV", "SysTick", ] - .contains(&name) + .contains(&name.as_str()) { // pass } else if flags @@ -171,7 +179,7 @@ impl ChipInterrupts { if name == "USBWakeUp" || name == "USBWakeUp_RMP" { "USB_WKUP" } else { - name.strip_suffix("_S").unwrap_or(name) + name.strip_suffix("_S").unwrap_or(&name) } }; @@ -205,6 +213,7 @@ impl ChipInterrupts { signals.insert(("RCC".to_string(), "CRS".to_string())); } else { let pp = match_peris(&peri_names, &part); + trace!(" part={part}, pp={pp:?}"); if !pp.is_empty() { curr_peris = pp; } else { @@ -230,7 +239,7 @@ impl ChipInterrupts { for s in ss { if !known.contains(&s.clone()) { - panic!("Unknown signal {s} for peri {p}, known={known:?}"); + panic!("Unknown signal {s} for peri {p}, known={known:?}, parts={parts:?}"); } signals.insert((p.clone(), s)); } @@ -282,7 +291,8 @@ impl ChipInterrupts { fn tokenize_name(name: &str) -> Vec { // Treat IRQ names are "tokens" separated by `_`, except some tokens // contain `_` themselves, such as `C1_RX`. - let r = regex!(r"(SPDIF_RX|EP\d+_(IN|OUT)|OTG_FS|OTG_HS|USB_FS|C1_RX|C1_TX|C2_RX|C2_TX|[A-Z0-9]+(_\d+)*)_*"); + let r = + regex!(r"(SPDIF_RX|EP\d+_(IN|OUT)|OTG_FS|OTG_HS|USB_DRD_FS|USB_FS|C1_RX|C1_TX|C2_RX|C2_TX|[A-Z0-9]+(_\d+)*)_*"); let name = name.to_ascii_uppercase(); r.captures_iter(&name) @@ -296,6 +306,7 @@ fn match_peris(peris: &[String], name: &str) -> Vec { ("OTG_HS", &["USB_OTG_HS"]), ("OTG_FS", &["USB_OTG_FS"]), ("USB", &["USB_DRD_FS"]), + ("USB_DRD_FS", &["USB"]), ("UCPD1_2", &["UCPD1", "UCPD2"]), ("ADC1", &["ADC"]), ("CEC", &["HDMI_CEC"]), @@ -348,6 +359,7 @@ fn valid_signals(peri: &str) -> Vec { ("CAN", &["TX", "RX0", "RX1", "SCE"]), ("FDCAN", &["IT0", "IT1", "CAL"]), ("I2C", &["ER", "EV"]), + ("I3C", &["ER", "EV"]), ("FMPI2C", &["ER", "EV"]), ("TIM", &["BRK", "UP", "TRG", "COM", "CC"]), // ("HRTIM", &["Master", "TIMA", "TIMB", "TIMC", "TIMD", "TIME", "TIMF"]), @@ -368,7 +380,7 @@ fn valid_signals(peri: &str) -> Vec { &["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"], ), ("MDF", &["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"]), - ("PWR", &["S3WU"]), + ("PWR", &["S3WU", "WKUP"]), ("GTZC", &["GLOBAL", "ILA"]), ("WWDG", &["GLOBAL", "RST"]), ("USB_OTG_FS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]), diff --git a/stm32-data-gen/src/main.rs b/stm32-data-gen/src/main.rs index dd74901..4e5657a 100644 --- a/stm32-data-gen/src/main.rs +++ b/stm32-data-gen/src/main.rs @@ -56,6 +56,8 @@ impl Stopwatch { } fn main() -> anyhow::Result<()> { + pretty_env_logger::init(); + let mut stopwatch = Stopwatch::new(); stopwatch.section("Parsing headers"); diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index a16a3ae..d4e17c6 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -73,14 +73,23 @@ impl PeripheralToClock { pub fn match_peri_clock( &self, - rcc_block: (String, String, String), + rcc_block: &(String, String, String), peri_name: &str, ) -> Option<&stm32_data_serde::chip::core::peripheral::Rcc> { - let clocks = self.0.get(&rcc_block)?; + const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])]; + + let clocks = self.0.get(rcc_block)?; if let Some(res) = clocks.get(peri_name) { Some(res) } else if let Some(peri_name) = peri_name.strip_suffix('1') { self.match_peri_clock(rcc_block, peri_name) + } else if let Some((_, rename)) = PERI_OVERRIDE.iter().find(|(n, _)| *n == peri_name) { + for n in *rename { + if let Some(res) = self.match_peri_clock(rcc_block, n) { + return Some(res); + } + } + None } else { None }