Arrayfied IER, ICR, ISR and MISR

IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS

data/registers/hsem_v1.yaml

@@ -16,42 +16,36 @@ block/HSEM:
     byte_offset: 128
     access: Read
     fieldset: RLR
-  - name: C1IER
+  - name: IER
     description: HSEM Interrupt enable register.
     byte_offset: 256
     fieldset: IER
-  - name: C1ICR
+    array:
+      len: 2
+      stride: 16
+  - name: ICR
     description: HSEM Interrupt clear register.
     byte_offset: 260
     fieldset: ICR
-  - name: C1ISR
+    array:
+      len: 2
+      stride: 16
+  - name: ISR
     description: HSEM Interrupt status register.
     byte_offset: 264
     access: Read
     fieldset: ISR
-  - name: C1MISR
+    array:
+      len: 2
+      stride: 16
+  - name: MISR
     description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-  - name: C2IER
+    array:
-    description: HSEM Interrupt enable register.
+      len: 2
-    byte_offset: 272
+      stride: 16
-    fieldset: IER
-  - name: C2ICR
-    description: HSEM Interrupt clear register.
-    byte_offset: 276
-    fieldset: ICR
-  - name: C2ISR
-    description: HSEM Interrupt status register.
-    byte_offset: 280
-    access: Read
-    fieldset: ISR
-  - name: C2MISR
-    description: HSEM Masked interrupt status register.
-    byte_offset: 284
-    access: Read
-    fieldset: MISR
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320

data/registers/hsem_v2.yaml

@@ -20,21 +20,33 @@ block/HSEM:
     description: HSEM Interrupt enable register.
     byte_offset: 256
     fieldset: IER
+    array:
+      len: 1
+      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
     byte_offset: 260
     access: Read
     fieldset: ICR
+    array:
+      len: 1
+      stride: 16
   - name: ISR
     description: HSEM Interrupt status register.
     byte_offset: 264
     access: Read
     fieldset: ISR
+    array:
+      len: 1
+      stride: 16
   - name: MISR
     description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
+    array:
+      len: 1
+      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320

data/registers/hsem_v3.yaml

@@ -16,42 +16,36 @@ block/HSEM:
     byte_offset: 128
     access: Read
     fieldset: RLR
-  - name: C1IER
+  - name: IER
     description: HSEM Interrupt enable register.
     byte_offset: 256
     fieldset: IER
-  - name: C1ICR
+    array:
+      len: 2
+      stride: 16
+  - name: ICR
     description: HSEM Interrupt clear register.
     byte_offset: 260
     fieldset: ICR
-  - name: C1ISR
+    array:
+      len: 2
+      stride: 16
+  - name: ISR
     description: HSEM Interrupt status register.
     byte_offset: 264
     access: Read
     fieldset: ISR
-  - name: C1MISR
+    array:
+      len: 2
+      stride: 16
+  - name: MISR
     description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-  - name: C2IER
+    array:
-    description: HSEM Interrupt enable register.
+      len: 2
-    byte_offset: 272
+      stride: 16
-    fieldset: IER
-  - name: C2ICR
-    description: HSEM Interrupt clear register.
-    byte_offset: 276
-    fieldset: ICR
-  - name: C2ISR
-    description: HSEM Interrupt status register.
-    byte_offset: 280
-    access: Read
-    fieldset: ISR
-  - name: C2MISR
-    description: HSEM Masked interrupt status register.
-    byte_offset: 284
-    access: Read
-    fieldset: MISR
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320

data/registers/hsem_v4.yaml

@@ -16,24 +16,36 @@ block/HSEM:
     byte_offset: 128
     access: Read
     fieldset: RLR
-  - name: C1IER
+  - name: IER
     description: HSEM Interrupt enable register.
     byte_offset: 256
-    fieldset: C1IER
+    fieldset: IER
-  - name: C1ICR
+    array:
+      len: 1
+      stride: 16
+  - name: ICR
     description: HSEM Interrupt clear register.
     byte_offset: 260
-    fieldset: C1ICR
+    fieldset: ICR
-  - name: C1ISR
+    array:
+      len: 1
+      stride: 16
+  - name: ISR
     description: HSEM Interrupt status register.
     byte_offset: 264
     access: Read
-    fieldset: C1ISR
+    fieldset: ISR
-  - name: C1MISR
+    array:
+      len: 1
+      stride: 16
+  - name: MISR
     description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
-    fieldset: C1MISR
+    fieldset: MISR
+    array:
+      len: 1
+      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -43,7 +55,7 @@ block/HSEM:
     description: HSEM Interrupt clear register.
     byte_offset: 324
     fieldset: KEYR
-fieldset/C1ICR:
+fieldset/ICR:
   description: HSEM Interrupt clear register.
   fields:
   - name: ISC
@@ -53,7 +65,7 @@ fieldset/C1ICR:
     array:
       len: 16
       stride: 1
-fieldset/C1IER:
+fieldset/IER:
   description: HSEM Interrupt enable register.
   fields:
   - name: ISE
@@ -63,7 +75,7 @@ fieldset/C1IER:
     array:
       len: 16
       stride: 1
-fieldset/C1ISR:
+fieldset/ISR:
   description: HSEM Interrupt status register.
   fields:
   - name: ISF
@@ -73,7 +85,7 @@ fieldset/C1ISR:
     array:
       len: 16
       stride: 1
-fieldset/C1MISR:
+fieldset/MISR:
   description: HSEM Masked interrupt status register.
   fields:
   - name: MISF

stm32-data-gen/src/chips.rs

@@ -1056,6 +1056,7 @@ fn process_core(
         "USBRAM",
         "VREFINTCAL",
         "UID",
+        "HSEM",
     ];
     for pname in GHOST_PERIS {
         if let Entry::Vacant(entry) = peri_kinds.entry(pname.to_string()) {