rcc: add missing enums to wb, wl.

2023-10-23 00:27:20 +02:00 · 2023-10-23 00:27:20 +02:00 · b59a5c1812
commit b59a5c1812
parent ee64389697
4 changed files with 206 additions and 2 deletions
--- a/data/registers/rcc_wb.yaml
+++ b/data/registers/rcc_wb.yaml
@ -1110,42 +1110,52 @@ fieldset/CCIPR:
    description: USART1 clock source selection
    bit_offset: 0
    bit_size: 2
+    enum: USART1SEL
  - name: LPUART1SEL
    description: LPUART1 clock source selection
    bit_offset: 10
    bit_size: 2
+    enum: LPUART1SEL
  - name: I2C1SEL
    description: I2C1 clock source selection
    bit_offset: 12
    bit_size: 2
+    enum: I2C1SEL
  - name: I2C3SEL
    description: I2C3 clock source selection
    bit_offset: 16
    bit_size: 2
+    enum: I2C3SEL
  - name: LPTIM1SEL
    description: Low power timer 1 clock source selection
    bit_offset: 18
    bit_size: 2
+    enum: LPTIM1SEL
  - name: LPTIM2SEL
    description: Low power timer 2 clock source selection
    bit_offset: 20
    bit_size: 2
+    enum: LPTIM2SEL
  - name: SAI1SEL
    description: SAI1 clock source selection
    bit_offset: 22
    bit_size: 2
+    enum: SAI1SEL
  - name: CLK48SEL
    description: 48 MHz clock source selection
    bit_offset: 26
    bit_size: 2
+    enum: CLK48SEL
  - name: ADCSEL
    description: ADCs clock source selection
    bit_offset: 28
    bit_size: 2
+    enum: ADCSEL
  - name: RNGSEL
    description: RNG clock source selection
    bit_offset: 30
    bit_size: 2
+    enum: RNGSEL
 fieldset/CFGR:
  description: Clock configuration register
  fields:
@ -1657,6 +1667,34 @@ fieldset/SMPSCR:
    description: Step Down converter clock switch status
    bit_offset: 8
    bit_size: 2
+enum/ADCSEL:
+  bit_size: 2
+  variants:
+  - name: DISABLE
+    description: No clock selected
+    value: 0
+  - name: PLLSAI1_R
+    value: 1
+  - name: PLL1_P
+    value: 2
+  - name: SYS
+    description: SYSCLK clock selected
+    value: 3
+enum/CLK48SEL:
+  bit_size: 2
+  variants:
+  - name: HSI48
+    description: HSI48 clock selected
+    value: 0
+  - name: PLLSAI1_Q
+    description: PLLSAI1_Q aka PLL48M1CLK clock selected
+    value: 1
+  - name: PLL1_Q
+    description: PLL_Q aka PLL48M2CLK clock selected
+    value: 2
+  - name: MSI
+    description: MSI clock selected
+    value: 3
 enum/HPRE:
  bit_size: 4
  variants:
@ -1709,6 +1747,74 @@ enum/HSEPRE:
    value: 0
  - name: Div2
    value: 1
+enum/I2C1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: PCLK clock selected
+    value: 0
+  - name: SYS
+    description: SYSCLK clock selected
+    value: 1
+  - name: HSI
+    description: HSI clock selected
+    value: 2
+enum/I2C3SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: PCLK clock selected
+    value: 0
+  - name: SYS
+    description: SYSCLK clock selected
+    value: 1
+  - name: HSI
+    description: HSI clock selected
+    value: 2
+enum/LPTIM1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: PCLK clock selected
+    value: 0
+  - name: LSI
+    description: LSI clock selected
+    value: 1
+  - name: HSI
+    description: HSI clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/LPTIM2SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: PCLK clock selected
+    value: 0
+  - name: LSI
+    description: LSI clock selected
+    value: 1
+  - name: HSI
+    description: HSI clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/LPUART1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: PCLK clock selected
+    value: 0
+  - name: SYS
+    description: SYSCLK clock selected
+    value: 1
+  - name: HSI
+    description: HSI clock selected
+    value: 2
+  - name: HSE
+    value: 3
 enum/LSEDRV:
  bit_size: 2
  variants:
@ -2170,6 +2276,18 @@ enum/PPRE:
  - name: Div16
    description: HCLK divided by 16
    value: 7
+enum/RNGSEL:
+  bit_size: 2
+  variants:
+  - name: CLK48
+    description: CLK48
+    value: 0
+  - name: LSI
+    description: LSI clock selected
+    value: 1
+  - name: LSE
+    description: LSE clock selected
+    value: 2
 enum/RTCSEL:
  bit_size: 2
  variants:
@ -2185,6 +2303,17 @@ enum/RTCSEL:
  - name: HSE
    description: HSE oscillator clock divided by 32 selected
    value: 3
+enum/SAI1SEL:
+  bit_size: 2
+  variants:
+  - name: PLLSAI1_P
+    value: 0
+  - name: PLL1_P
+    value: 1
+  - name: HSI
+    value: 2
+  - name: SAI1_EXTCLK
+    value: 3
 enum/SW:
  bit_size: 2
  variants:
@ -2196,3 +2325,17 @@ enum/SW:
    value: 2
  - name: PLL1_R
    value: 3
+enum/USART1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: PCLK clock selected
+    value: 0
+  - name: SYS
+    description: SYSCLK clock selected
+    value: 1
+  - name: HSI
+    description: HSI clock selected
+    value: 2
+  - name: HSE
+    value: 3
--- a/data/registers/rcc_wl5.yaml
+++ b/data/registers/rcc_wl5.yaml
@ -1065,6 +1065,7 @@ fieldset/CCIPR:
    description: RNG clock source selection
    bit_offset: 30
    bit_size: 2
+    enum: RNGSEL
 fieldset/CFGR:
  description: Clock configuration register
  fields:
@ -1239,6 +1240,7 @@ fieldset/CR:
    description: MSI range control selection
    bit_offset: 3
    bit_size: 1
+    enum: MSIRGSEL
  - name: MSIRANGE
    description: MSI clock ranges
    bit_offset: 4
@ -1280,6 +1282,7 @@ fieldset/CR:
    description: HSE sysclk prescaler
    bit_offset: 20
    bit_size: 1
+    enum: HSEPRE
  - name: HSEBYPPWR
    description: Enable HSE VDDTCXO output on package pin PB0-VDDTCXO.
    bit_offset: 21
@ -1497,6 +1500,13 @@ enum/HPRE:
  - name: Div512
    description: hclk = SYSCLK divided by 256
    value: 15
+enum/HSEPRE:
+  bit_size: 1
+  variants:
+  - name: Div1
+    value: 0
+  - name: Div2
+    value: 1
 enum/LSEDRV:
  bit_size: 2
  variants:
@ -1548,7 +1558,7 @@ enum/MCOSEL:
  - name: HSE
    description: HSE oscillator clock selected
    value: 4
-  - name: PLLRCLK
+  - name: PLL1_R
    description: Main PLLRCLK clock selected
    value: 5
  - name: LSI
@ -1560,7 +1570,7 @@ enum/MCOSEL:
  - name: PLL1_P
    description: Main PLLCLK oscillator clock selected
    value: 13
-  - name: PLLQCLK
+  - name: PLL1_Q
    description: Main PLLQCLK oscillator clock selected
    value: 14
 enum/MSIRANGE:
@ -1602,6 +1612,15 @@ enum/MSIRANGE:
  - name: Range48M
    description: range 11 around 48 MHz
    value: 11
+enum/MSIRGSEL:
+  bit_size: 1
+  variants:
+  - name: CSR
+    description: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register
+    value: 0
+  - name: CR
+    description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register
+    value: 1
 enum/PLLM:
  bit_size: 3
  variants:
@ -1994,6 +2013,17 @@ enum/PPRE:
  - name: Div16
    description: HCLK divided by 16
    value: 7
+enum/RNGSEL:
+  bit_size: 2
+  variants:
+  - name: PLL1_Q
+    value: 0
+  - name: LSI
+    value: 1
+  - name: LSE
+    value: 2
+  - name: MSI
+    value: 3
 enum/RTCSEL:
  bit_size: 2
  variants:
--- a/data/registers/rcc_wle.yaml
+++ b/data/registers/rcc_wle.yaml
@ -695,6 +695,7 @@ fieldset/CCIPR:
    description: RNG clock source selection
    bit_offset: 30
    bit_size: 2
+    enum: RNGSEL
 fieldset/CFGR:
  description: Clock configuration register
  fields:
@ -869,6 +870,7 @@ fieldset/CR:
    description: MSI range control selection
    bit_offset: 3
    bit_size: 1
+    enum: MSIRGSEL
  - name: MSIRANGE
    description: MSI clock ranges
    bit_offset: 4
@ -910,6 +912,7 @@ fieldset/CR:
    description: HSE sysclk prescaler
    bit_offset: 20
    bit_size: 1
+    enum: HSEPRE
  - name: HSEBYPPWR
    description: Enable HSE VDDTCXO output on package pin PB0-VDDTCXO.
    bit_offset: 21
@ -1118,6 +1121,13 @@ enum/HPRE:
  - name: Div512
    description: hclk = SYSCLK divided by 256
    value: 15
+enum/HSEPRE:
+  bit_size: 1
+  variants:
+  - name: Div1
+    value: 0
+  - name: Div2
+    value: 1
 enum/LSEDRV:
  bit_size: 2
  variants:
@ -1223,6 +1233,15 @@ enum/MSIRANGE:
  - name: Range48M
    description: range 11 around 48 MHz
    value: 11
+enum/MSIRGSEL:
+  bit_size: 1
+  variants:
+  - name: CSR
+    description: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register
+    value: 0
+  - name: CR
+    description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register
+    value: 1
 enum/PLLM:
  bit_size: 3
  variants:
@ -1615,6 +1634,17 @@ enum/PPRE:
  - name: Div16
    description: HCLK divided by 16
    value: 7
+enum/RNGSEL:
+  bit_size: 2
+  variants:
+  - name: PLL1_Q
+    value: 0
+  - name: LSI
+    value: 1
+  - name: LSE
+    value: 2
+  - name: MSI
+    value: 3
 enum/RTCSEL:
  bit_size: 2
  variants:
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@ -90,6 +90,7 @@ impl PeripheralToClock {
            "LSE",
            "AUDIOCLK",
            "PER",
+            "CLK48",
            // TODO: variants to cleanup
            "SAI1_EXTCLK",
            "SAI2_EXTCLK",