Add missing fmc for STM32F4[0123], F1, F2, and L1
For now this is called v0. The files are renamed in the next commit.
This commit is contained in:
Rasmus Melchior Jacobsen
parent
c75d213953
commit
b4c8bf0be7
@ -1,4 +1,11 @@
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# stm32f405
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# stm32f407
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# stm32f427
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# stm32f429
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# stm32f415
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# stm32f417
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# stm32f437
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# stm32f439
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---
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block/FMC:
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description: Flexible memory controller
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225
data/registers/fsmc_v0x1.yaml
Normal file
225
data/registers/fsmc_v0x1.yaml
Normal file
@ -0,0 +1,225 @@
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# stm32f100
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---
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block/FSMC:
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description: Flexible static memory controller
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items:
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- name: BCR
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description: SRAM/NOR-Flash chip-select control register 1-4
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array:
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len: 4
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stride: 8
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byte_offset: 0
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fieldset: BCR
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- name: BTR
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description: SRAM/NOR-Flash chip-select timing register 1-4
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array:
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len: 4
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stride: 8
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byte_offset: 4
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fieldset: BTR
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- name: BWTR
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description: SRAM/NOR-Flash write timing registers 1-4
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array:
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len: 4
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stride: 8
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byte_offset: 260
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fieldset: BWTR
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fieldset/BCR:
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description: SRAM/NOR-Flash chip-select control register
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fields:
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- name: MBKEN
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description: Memory bank enable bit
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bit_offset: 0
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bit_size: 1
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- name: MUXEN
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description: Address/data multiplexing enable bit
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bit_offset: 1
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bit_size: 1
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- name: MTYP
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description: Memory type
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bit_offset: 2
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bit_size: 2
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enum: MTYP
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- name: MWID
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description: Memory data bus width
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bit_offset: 4
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bit_size: 2
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enum: MWID
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- name: FACCEN
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description: Flash access enable
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bit_offset: 6
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bit_size: 1
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- name: BURSTEN
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description: Burst enable bit
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bit_offset: 8
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bit_size: 1
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- name: WAITPOL
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description: Wait signal polarity bit
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bit_offset: 9
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bit_size: 1
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enum: WAITPOL
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- name: WRAPMOD
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description: WRAPMOD
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bit_offset: 10
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bit_size: 1
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- name: WAITCFG
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description: Wait timing configuration
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bit_offset: 11
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bit_size: 1
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enum: WAITCFG
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- name: WREN
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description: Write enable bit
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bit_offset: 12
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bit_size: 1
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- name: WAITEN
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description: Wait enable bit
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bit_offset: 13
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bit_size: 1
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- name: EXTMOD
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description: Extended mode enable
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bit_offset: 14
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bit_size: 1
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- name: ASYNCWAIT
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description: Wait signal during asynchronous transfers
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bit_offset: 15
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bit_size: 1
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- name: CPSIZE
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description: CRAM page size
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bit_offset: 16
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bit_size: 3
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enum: CPSIZE
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- name: CBURSTRW
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description: Write burst enable
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bit_offset: 19
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bit_size: 1
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fieldset/BTR:
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description: SRAM/NOR-Flash chip-select timing register
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fields:
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- name: ADDSET
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description: Address setup phase duration
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bit_offset: 0
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bit_size: 4
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- name: ADDHLD
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description: Address-hold phase duration
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bit_offset: 4
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bit_size: 4
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- name: DATAST
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description: Data-phase duration
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bit_offset: 8
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bit_size: 8
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- name: BUSTURN
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description: Bus turnaround phase duration
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bit_offset: 16
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bit_size: 4
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- name: CLKDIV
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description: Clock divide ratio (for FMC_CLK signal)
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bit_offset: 20
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bit_size: 4
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- name: DATLAT
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description: Data latency for synchronous memory
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bit_offset: 24
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bit_size: 4
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- name: ACCMOD
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description: Access mode
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bit_offset: 28
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bit_size: 2
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enum: ACCMOD
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fieldset/BWTR:
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description: SRAM/NOR-Flash write timing registers
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fields:
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- name: ADDSET
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description: Address setup phase duration
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bit_offset: 0
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bit_size: 4
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- name: ADDHLD
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description: Address-hold phase duration
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bit_offset: 4
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bit_size: 4
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- name: DATAST
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description: Data-phase duration
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bit_offset: 8
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bit_size: 8
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- name: BUSTURN
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description: Bus turnaround phase duration
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bit_offset: 16
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bit_size: 4
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- name: ACCMOD
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description: Access mode
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bit_offset: 28
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bit_size: 2
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enum: ACCMOD
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enum/ACCMOD:
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bit_size: 2
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variants:
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- name: A
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description: Access mode A
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value: 0
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- name: B
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description: Access mode B
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value: 1
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- name: C
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description: Access mode C
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value: 2
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- name: D
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description: Access mode D
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value: 3
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enum/CPSIZE:
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bit_size: 3
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variants:
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- name: NoBurstSplit
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description: No burst split when crossing page boundary
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value: 0
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- name: Bytes128
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description: 128 bytes CRAM page size
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value: 1
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- name: Bytes256
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description: 256 bytes CRAM page size
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value: 2
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- name: Bytes512
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description: 512 bytes CRAM page size
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value: 3
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- name: Bytes1024
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description: 1024 bytes CRAM page size
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value: 4
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enum/MTYP:
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bit_size: 2
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variants:
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- name: SRAM
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description: SRAM memory type
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value: 0
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- name: PSRAM
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description: PSRAM (CRAM) memory type
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value: 1
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- name: Flash
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description: NOR Flash/OneNAND Flash
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value: 2
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enum/MWID:
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bit_size: 2
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variants:
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- name: Bits8
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description: Memory data bus width 8 bits
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value: 0
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- name: Bits16
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description: Memory data bus width 16 bits
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value: 1
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- name: Bits32
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description: Memory data bus width 32 bits
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value: 2
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enum/WAITCFG:
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bit_size: 1
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variants:
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- name: BeforeWaitState
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description: NWAIT signal is active one data cycle before wait state
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value: 0
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- name: DuringWaitState
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description: NWAIT signal is active during wait state
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value: 1
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enum/WAITPOL:
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bit_size: 1
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variants:
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- name: ActiveLow
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description: NWAIT active low
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value: 0
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- name: ActiveHigh
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description: NWAIT active high
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value: 1
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439
data/registers/fsmc_v0x3.yaml
Normal file
439
data/registers/fsmc_v0x3.yaml
Normal file
@ -0,0 +1,439 @@
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# stm32f101
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# stm32f102
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# stm32f103
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# stm32f105
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# stm32f107
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# stm32f2
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---
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block/FSMC:
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description: Flexible static memory controller
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items:
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- name: BCR
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description: SRAM/NOR-Flash chip-select control register 1-4
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array:
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len: 4
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stride: 8
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byte_offset: 0
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fieldset: BCR
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- name: BTR
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description: SRAM/NOR-Flash chip-select timing register 1-4
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array:
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len: 4
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stride: 8
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byte_offset: 4
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fieldset: BTR
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- name: BWTR
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description: SRAM/NOR-Flash write timing registers 1-4
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array:
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len: 4
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stride: 8
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byte_offset: 260
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fieldset: BWTR
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- name: PCR
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description: PC Card/NAND Flash control register 2-4
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array:
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len: 3
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stride: 32
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byte_offset: 96
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fieldset: PCR
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- name: SR
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description: FIFO status and interrupt register 2-4
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array:
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len: 3
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stride: 32
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byte_offset: 100
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fieldset: SR
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- name: PMEM
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description: Common memory space timing register 2-4
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array:
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len: 3
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stride: 32
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byte_offset: 104
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fieldset: PMEM
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- name: PATT
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description: Attribute memory space timing register 2-4
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array:
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len: 3
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stride: 32
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byte_offset: 108
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fieldset: PATT
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- name: PIO4
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description: I/O space timing register 4
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byte_offset: 176
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fieldset: PIO4
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- name: ECCR
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description: ECC result register 2-3
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array:
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len: 2
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stride: 32
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byte_offset: 116
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access: Read
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fieldset: ECCR
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fieldset/BCR:
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description: SRAM/NOR-Flash chip-select control register
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fields:
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- name: MBKEN
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description: Memory bank enable bit
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bit_offset: 0
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bit_size: 1
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- name: MUXEN
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description: Address/data multiplexing enable bit
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bit_offset: 1
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bit_size: 1
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- name: MTYP
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description: Memory type
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bit_offset: 2
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bit_size: 2
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enum: MTYP
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- name: MWID
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description: Memory data bus width
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bit_offset: 4
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bit_size: 2
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enum: MWID
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- name: FACCEN
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description: Flash access enable
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bit_offset: 6
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bit_size: 1
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- name: BURSTEN
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description: Burst enable bit
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bit_offset: 8
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bit_size: 1
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- name: WAITPOL
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description: Wait signal polarity bit
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bit_offset: 9
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bit_size: 1
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enum: WAITPOL
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- name: WRAPMOD
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description: WRAPMOD
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bit_offset: 10
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bit_size: 1
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- name: WAITCFG
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description: Wait timing configuration
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bit_offset: 11
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bit_size: 1
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enum: WAITCFG
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- name: WREN
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description: Write enable bit
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bit_offset: 12
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bit_size: 1
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- name: WAITEN
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description: Wait enable bit
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bit_offset: 13
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bit_size: 1
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- name: EXTMOD
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description: Extended mode enable
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bit_offset: 14
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bit_size: 1
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- name: ASYNCWAIT
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description: Wait signal during asynchronous transfers
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bit_offset: 15
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bit_size: 1
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- name: CPSIZE
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description: CRAM page size
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bit_offset: 16
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bit_size: 3
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enum: CPSIZE
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- name: CBURSTRW
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description: Write burst enable
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bit_offset: 19
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bit_size: 1
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fieldset/BTR:
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description: SRAM/NOR-Flash chip-select timing register
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fields:
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- name: ADDSET
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description: Address setup phase duration
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bit_offset: 0
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bit_size: 4
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- name: ADDHLD
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description: Address-hold phase duration
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bit_offset: 4
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bit_size: 4
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- name: DATAST
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description: Data-phase duration
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bit_offset: 8
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bit_size: 8
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- name: BUSTURN
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description: Bus turnaround phase duration
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bit_offset: 16
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bit_size: 4
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- name: CLKDIV
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description: Clock divide ratio (for FMC_CLK signal)
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bit_offset: 20
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bit_size: 4
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- name: DATLAT
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description: Data latency for synchronous memory
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bit_offset: 24
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bit_size: 4
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- name: ACCMOD
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description: Access mode
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bit_offset: 28
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bit_size: 2
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enum: ACCMOD
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fieldset/BWTR:
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description: SRAM/NOR-Flash write timing registers
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fields:
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- name: ADDSET
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description: Address setup phase duration
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bit_offset: 0
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bit_size: 4
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- name: ADDHLD
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description: Address-hold phase duration
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bit_offset: 4
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bit_size: 4
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- name: DATAST
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description: Data-phase duration
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bit_offset: 8
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bit_size: 8
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- name: BUSTURN
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description: Bus turnaround phase duration
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bit_offset: 16
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bit_size: 4
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- name: ACCMOD
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description: Access mode
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bit_offset: 28
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bit_size: 2
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enum: ACCMOD
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fieldset/PCR:
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description: PC Card/NAND Flash control register
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fields:
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- name: PWAITEN
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description: Wait feature enable bit
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bit_offset: 1
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bit_size: 1
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- name: PBKEN
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description: NAND Flash memory bank enable bit
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bit_offset: 2
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bit_size: 1
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- name: PTYP
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description: Memory type
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bit_offset: 3
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bit_size: 1
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enum: PTYP
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- name: PWID
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description: Data bus width
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bit_offset: 4
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bit_size: 2
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enum: PWID
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- name: ECCEN
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description: ECC computation logic enable bit
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bit_offset: 6
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bit_size: 1
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- name: TCLR
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description: CLE to RE delay
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bit_offset: 9
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bit_size: 4
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- name: TAR
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description: ALE to RE delay
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bit_offset: 13
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bit_size: 4
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- name: ECCPS
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description: ECC page size
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bit_offset: 17
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bit_size: 3
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enum: ECCPS
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fieldset/SR:
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description: FIFO status and interrupt register
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fields:
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- name: IRS
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description: Interrupt rising edge status
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bit_offset: 0
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bit_size: 1
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- name: ILS
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description: Interrupt high-level status
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bit_offset: 1
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bit_size: 1
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- name: IFS
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description: Interrupt falling edge status
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bit_offset: 2
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bit_size: 1
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- name: IREN
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description: Interrupt rising edge detection enable bit
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bit_offset: 3
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bit_size: 1
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- name: ILEN
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description: Interrupt high-level detection enable bit
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bit_offset: 4
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bit_size: 1
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- name: IFEN
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description: Interrupt falling edge detection enable bit
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bit_offset: 5
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bit_size: 1
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- name: FEMPT
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description: FIFO empty status
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bit_offset: 6
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bit_size: 1
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fieldset/PMEM:
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description: Common memory space timing register
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fields:
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- name: MEMSET
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description: Common memory x setup time
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bit_offset: 0
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bit_size: 8
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- name: MEMWAIT
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description: Common memory wait time
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bit_offset: 8
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bit_size: 8
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- name: MEMHOLD
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description: Common memory hold time
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bit_offset: 16
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bit_size: 8
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- name: MEMHIZ
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description: Common memory x data bus Hi-Z time
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bit_offset: 24
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bit_size: 8
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fieldset/PATT:
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description: Attribute memory space timing register
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fields:
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- name: ATTSET
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description: Attribute memory setup time
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bit_offset: 0
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bit_size: 8
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- name: ATTWAIT
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description: Attribute memory wait time
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bit_offset: 8
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bit_size: 8
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- name: ATTHOLD
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description: Attribute memory hold time
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bit_offset: 16
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bit_size: 8
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- name: ATTHIZ
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description: Attribute memory data bus Hi-Z time
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bit_offset: 24
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bit_size: 8
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fieldset/PIO4:
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description: I/O space timing register 4
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fields:
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- name: IOSETx
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description: IOSETx
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bit_offset: 0
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bit_size: 8
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- name: IOWAITx
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description: IOWAITx
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bit_offset: 8
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bit_size: 8
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- name: IOHOLDx
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description: IOHOLDx
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bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: IOHIZx
|
||||
description: IOHIZx
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/ECCR:
|
||||
description: ECC result register
|
||||
fields:
|
||||
- name: ECC
|
||||
description: ECC computation result value
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/ACCMOD:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: A
|
||||
description: Access mode A
|
||||
value: 0
|
||||
- name: B
|
||||
description: Access mode B
|
||||
value: 1
|
||||
- name: C
|
||||
description: Access mode C
|
||||
value: 2
|
||||
- name: D
|
||||
description: Access mode D
|
||||
value: 3
|
||||
enum/CPSIZE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NoBurstSplit
|
||||
description: No burst split when crossing page boundary
|
||||
value: 0
|
||||
- name: Bytes128
|
||||
description: 128 bytes CRAM page size
|
||||
value: 1
|
||||
- name: Bytes256
|
||||
description: 256 bytes CRAM page size
|
||||
value: 2
|
||||
- name: Bytes512
|
||||
description: 512 bytes CRAM page size
|
||||
value: 3
|
||||
- name: Bytes1024
|
||||
description: 1024 bytes CRAM page size
|
||||
value: 4
|
||||
enum/ECCPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Bytes256
|
||||
description: ECC page size 256 bytes
|
||||
value: 0
|
||||
- name: Bytes512
|
||||
description: ECC page size 512 bytes
|
||||
value: 1
|
||||
- name: Bytes1024
|
||||
description: ECC page size 1024 bytes
|
||||
value: 2
|
||||
- name: Bytes2048
|
||||
description: ECC page size 2048 bytes
|
||||
value: 3
|
||||
- name: Bytes4096
|
||||
description: ECC page size 4096 bytes
|
||||
value: 4
|
||||
- name: Bytes8192
|
||||
description: ECC page size 8192 bytes
|
||||
value: 5
|
||||
enum/MTYP:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: SRAM
|
||||
description: SRAM memory type
|
||||
value: 0
|
||||
- name: PSRAM
|
||||
description: PSRAM (CRAM) memory type
|
||||
value: 1
|
||||
- name: Flash
|
||||
description: NOR Flash/OneNAND Flash
|
||||
value: 2
|
||||
enum/MWID:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: Memory data bus width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Memory data bus width 16 bits
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Memory data bus width 32 bits
|
||||
value: 2
|
||||
enum/PTYP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NANDFlash
|
||||
description: NAND Flash
|
||||
value: 1
|
||||
enum/PWID:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: External memory device width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: External memory device width 16 bits
|
||||
value: 1
|
||||
enum/WAITCFG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: BeforeWaitState
|
||||
description: NWAIT signal is active one data cycle before wait state
|
||||
value: 0
|
||||
- name: DuringWaitState
|
||||
description: NWAIT signal is active during wait state
|
||||
value: 1
|
||||
enum/WAITPOL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: ActiveLow
|
||||
description: NWAIT active low
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: NWAIT active high
|
||||
value: 1
|
||||
@ -294,12 +294,16 @@ impl PeriMatcher {
|
||||
("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")),
|
||||
("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")),
|
||||
(".*ETH:ethermac110_v3_0", ("eth", "v2", "ETH")),
|
||||
("STM32F429.*:FMC:.*", ("fmc", "v1x3", "FMC")),
|
||||
("STM32F4[0123].*:FMC:.*", ("fmc", "v1x3", "FMC")),
|
||||
("STM32F446.*:FMC:.*", ("fmc", "v2x1", "FMC")),
|
||||
("STM32F469.*:FMC:.*", ("fmc", "v2x1", "FMC")),
|
||||
("STM32F7.*:FMC:.*", ("fmc", "v2x1", "FMC")),
|
||||
("STM32H7.*:FMC:.*", ("fmc", "v3x1", "FMC")),
|
||||
("STM32F100.*:FSMC:.*", ("fsmc", "v0x1", "FSMC")),
|
||||
("STM32F10[12357].*:FSMC:.*", ("fsmc", "v0x3", "FSMC")),
|
||||
("STM32F2.*:FSMC:.*", ("fsmc", "v0x3", "FSMC")),
|
||||
("STM32F3.*:FSMC:.*", ("fsmc", "v1x3", "FSMC")),
|
||||
("STM32L1.*:FSMC:.*", ("fsmc", "v0x1", "FSMC")),
|
||||
("STM32L4.*:FSMC:.*", ("fsmc", "v2x1", "FSMC")),
|
||||
("STM32G4.*:FSMC:.*", ("fsmc", "v3x1", "FSMC")),
|
||||
("STM32L5.*:FSMC:.*", ("fsmc", "v3x1", "FSMC")),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user