From b4191f4d1cc560eaa4525f17dee575faf73a09b2 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sun, 28 Nov 2021 22:26:22 +0100 Subject: [PATCH] clocks: accept regs like xxENR1 (previously it'd only accept xxENR) This adds a few more `clock` entries. --- stm32data/__main__.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index c33ced9..872798a 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -1155,11 +1155,8 @@ def parse_rcc_regs(): y = yaml.load(yaml_file) for (key, body) in y.items(): if 'SMENR' in key: continue - if key.startswith("fieldset/A") and key.endswith("ENR"): - clock = removesuffix(key, "ENR") - clock = removeprefix(clock, "fieldset/") - clock = removesuffix(clock, "L") - clock = removesuffix(clock, "H") + if m := re.match('^fieldset/(A[PH]B\d?)ENR\d?$', key): + clock = m.group(1) for field in body['fields']: if field['name'].endswith('EN'): peri = removesuffix(field['name'], 'EN')