From b18d82e9412f226e04c58b55e2f24c2acfedc636 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 11 Jan 2024 00:11:22 +0800 Subject: [PATCH] apply transform on syscfg_f3 --- data/registers/syscfg_f3.yaml | 374 +++++++++------------------------- transforms/SYSCFG_F3.yaml | 28 +++ 2 files changed, 126 insertions(+), 276 deletions(-) diff --git a/data/registers/syscfg_f3.yaml b/data/registers/syscfg_f3.yaml index cba3ebd..7951bd3 100644 --- a/data/registers/syscfg_f3.yaml +++ b/data/registers/syscfg_f3.yaml @@ -37,115 +37,164 @@ fieldset/CFGR1: bit_size: 2 enum: MEM_MODE - name: USB_IT_RMP - description: USB interrupt remap + description: | + USB interrupt remap + 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively + 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively bit_offset: 5 bit_size: 1 - enum: USB_IT_RMP - name: TIM1_ITR3_RMP - description: Timer 1 ITR3 selection + description: | + Timer 1 ITR3 selection + 0: Not remapped + 1: TIM1_ITR3 = TIM17_OC bit_offset: 6 bit_size: 1 - enum: TIM1_ITR3_RMP - name: DAC1_TRIG_RMP - description: DAC trigger remap (when TSEL = 001) + description: | + DAC trigger remap (when TSEL = 001) + 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices + 1: DAC trigger is TIM3_TRGO bit_offset: 7 bit_size: 1 - enum: DAC1_TRIG_RMP - name: DAC_TRIG_RMP - description: DAC trigger remap (when TSEL = 001) + description: | + DAC trigger remap (when TSEL = 001) + 0: Not remapped + 1: DAC trigger is TIM3_TRGO bit_offset: 7 bit_size: 1 - enum: DAC_TRIG_RMP - name: ADC2_DMA_RMP - description: ADC24 DMA remapping bit + description: | + ADC24 DMA remapping bit + 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 + 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4 bit_offset: 8 bit_size: 1 - enum: ADC2_DMA_RMP_CFGR1 - name: TIM16_DMA_RMP - description: TIM16 DMA request remapping bit + description: | + TIM16 DMA request remapping bit + 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 + 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - enum: TIM16_DMA_RMP - name: TIM17_DMA_RMP - description: TIM17 DMA request remapping bit + description: | + TIM17 DMA request remapping bit + 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - enum: TIM17_DMA_RMP - name: TIM6_DAC1_CH1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit + description: | + TIM6 and DAC1 DMA request remapping bit + 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - enum: TIM6_DAC1_CH1_DMA_RMP - name: TIM6_DAC1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit + description: | + TIM6 and DAC1 DMA request remapping bit + 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - enum: TIM6_DAC1_DMA_RMP - name: TIM6_DAC1_OUT1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit + description: | + TIM6 and DAC1 DMA request remapping bit + 0: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 + 1: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - enum: TIM6_DAC1_OUT1_DMA_RMP - name: TIM7_DAC1_CH2_DMA_RMP - description: TIM7 and DAC2 DMA request remapping bit + description: | + TIM7 and DAC2 DMA request remapping bit + 0: Not remapped + 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 bit_offset: 14 bit_size: 1 - enum: TIM7_DAC1_CH2_DMA_RMP - name: TIM7_DAC1_OUT2_DMA_RMP - description: TIM7 and DAC2 DMA request remapping bit + description: | + TIM7 and DAC2 DMA request remapping bit + 0: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 + 1: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 bit_offset: 14 bit_size: 1 - enum: TIM7_DAC1_OUT2_DMA_RMP - name: DAC2_CH1_DMA_RMP - description: DAC2 channel1 DMA remap + description: | + DAC2 channel1 DMA remap + 0: Not remapped + 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5 bit_offset: 15 bit_size: 1 - enum: DAC2_CH1_DMA_RMP - name: TIM18_DAC2_OUT1_DMA_RMP - description: TIM18 and DAC2_OUT1 DMA request remapping bit + description: | + TIM18 and DAC2_OUT1 DMA request remapping bit + 0: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 + 1: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 bit_offset: 15 bit_size: 1 - enum: TIM18_DAC2_OUT1_DMA_RMP - name: I2C_PB6_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB6 pin operate in standard mode + 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed bit_offset: 16 bit_size: 1 - enum: I2C_PB6_FMP + enum: FMP - name: I2C_PB7_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB7 pin operate in standard mode + 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed bit_offset: 17 bit_size: 1 - enum: I2C_PB7_FMP + enum: FMP - name: I2C_PB8_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB8 pin operate in standard mode + 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed bit_offset: 18 bit_size: 1 - enum: I2C_PB8_FMP + enum: FMP - name: I2C_PB9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB9 pin operate in standard mode + 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed bit_offset: 19 bit_size: 1 - enum: I2C_PB9_FMP + enum: FMP - name: I2C1_FMP - description: I2C1 Fast Mode Plus + description: | + I2C1 Fast Mode Plus + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits bit_offset: 20 bit_size: 1 - enum: I2C1_FMP + enum: FMP - name: I2C2_FMP - description: I2C2 Fast Mode Plus + description: | + I2C2 Fast Mode Plus + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits bit_offset: 21 bit_size: 1 - enum: I2C2_FMP + enum: FMP - name: ENCODER_MODE description: Encoder mode bit_offset: 22 bit_size: 2 enum: ENCODER_MODE - name: I2C3_FMP - description: I2C3 Fast Mode Plus + description: | + I2C3 Fast Mode Plus + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits bit_offset: 24 bit_size: 1 - enum: I2C3_FMP + enum: FMP - name: VBAT_MON description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input bit_offset: 24 @@ -170,22 +219,18 @@ fieldset/CFGR2: description: Cortex-M0 LOCKUP bit enable bit bit_offset: 0 bit_size: 1 - enum: LOCKUP_LOCK - name: SRAM_PARITY_LOCK description: SRAM parity lock bit bit_offset: 1 bit_size: 1 - enum: SRAM_PARITY_LOCK - name: PVD_LOCK description: PVD lock enable bit bit_offset: 2 bit_size: 1 - enum: PVD_LOCK - name: BYP_ADDR_PAR description: Bypass address bit 29 in parity calculation bit_offset: 4 bit_size: 1 - enum: BYP_ADDR_PAR - name: SRAM_PEF description: SRAM parity flag bit_offset: 8 @@ -224,10 +269,12 @@ fieldset/CFGR3: bit_size: 1 enum: DAC1_TRIG3_RMP - name: DAC1_TRIG5_RMP - description: DAC1_CH1 / DAC1_CH2 Trigger remap + description: | + DAC1_CH1 / DAC1_CH2 Trigger remap + 0: Not remapped + 1: DAC trigger is HRTIM1_DAC1_TRIG2 bit_offset: 17 bit_size: 1 - enum: DAC1_TRIG5_RMP fieldset/CFGR4: description: configuration register 4 fields: @@ -393,15 +440,6 @@ enum/ADC12_JEXT6_RMP: - name: Tim20 description: Trigger source is TIM20_TRGO2 value: 1 -enum/ADC2_DMA_RMP_CFGR1: - bit_size: 1 - variants: - - name: NotRemapped - description: ADC24 DMA requests mapped on DMA2 channels 1 and 2 - value: 0 - - name: Remapped - description: ADC24 DMA requests mapped on DMA2 channels 3 and 4 - value: 1 enum/ADC2_DMA_RMP_CFGR3: bit_size: 2 variants: @@ -465,15 +503,6 @@ enum/ADC34_JEXT5_RMP: - name: Tim20 description: Trigger source is TIM20_TRGO value: 1 -enum/BYP_ADDR_PAR: - bit_size: 1 - variants: - - name: NoBypass - description: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated - value: 0 - - name: Bypass - description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated - value: 1 enum/DAC1_TRIG3_RMP: bit_size: 1 variants: @@ -483,42 +512,6 @@ enum/DAC1_TRIG3_RMP: - name: HrTim1 description: DAC trigger is HRTIM1_DAC1_TRIG1 value: 1 -enum/DAC1_TRIG5_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC trigger is HRTIM1_DAC1_TRIG2 - value: 1 -enum/DAC1_TRIG_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices - value: 0 - - name: Remapped - description: DAC trigger is TIM3_TRGO - value: 1 -enum/DAC2_CH1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC2_CH1 DMA requests mapped on DMA1 channel 5 - value: 1 -enum/DAC_TRIG_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC trigger is TIM3_TRGO - value: 1 enum/ENCODER_MODE: bit_size: 2 variants: @@ -531,14 +524,14 @@ enum/ENCODER_MODE: - name: MapTim3Tim15 description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively value: 2 -enum/I2C1_FMP: +enum/FMP: bit_size: 1 variants: - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only + description: PB6 pin operate in standard mode value: 0 - name: FMP - description: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits + description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed value: 1 enum/I2C1_RX_DMA_RMP: bit_size: 2 @@ -564,69 +557,6 @@ enum/I2C1_TX_DMA_RMP: - name: MapDma1Ch4 description: I2C1_TX mapped on DMA1 CH4 value: 2 -enum/I2C2_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits - value: 1 -enum/I2C3_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits - value: 1 -enum/I2C_PB6_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB6 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - value: 1 -enum/I2C_PB7_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB7 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - value: 1 -enum/I2C_PB8_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB8 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - value: 1 -enum/I2C_PB9_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - value: 1 -enum/LOCKUP_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT. - value: 0 - - name: Connected - description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 1 enum/MEM_MODE: bit_size: 2 variants: @@ -642,15 +572,6 @@ enum/MEM_MODE: - name: SRAM description: Embedded SRAM mapped at 0x0000_0000 value: 3 -enum/PVD_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: PVD interrupt disconnected from TIM15/16/17 Break input - value: 0 - - name: Connected - description: PVD interrupt connected to TIM15/16/17 Break input - value: 1 enum/SPI1_RX_DMA_RMP: bit_size: 2 variants: @@ -675,102 +596,3 @@ enum/SPI1_TX_DMA_RMP: - name: MapDma1Ch7 description: SPI1_TX mapped on DMA1 CH7 value: 2 -enum/SRAM_PARITY_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 0 - - name: Connected - description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 1 -enum/TIM16_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 - value: 0 - - name: Remapped - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 - value: 1 -enum/TIM17_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - value: 0 - - name: Remapped - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 - value: 1 -enum/TIM18_DAC2_OUT1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 - value: 0 - - name: Remapped - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 - value: 1 -enum/TIM1_ITR3_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: TIM1_ITR3 = TIM17_OC - value: 1 -enum/TIM6_DAC1_CH1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - value: 1 -enum/TIM6_DAC1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - value: 1 -enum/TIM6_DAC1_OUT1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 - value: 1 -enum/TIM7_DAC1_CH2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 - value: 1 -enum/TIM7_DAC1_OUT2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 - value: 0 - - name: Remapped - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 - value: 1 -enum/USB_IT_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively - value: 0 - - name: Remapped - description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively - value: 1 diff --git a/transforms/SYSCFG_F3.yaml b/transforms/SYSCFG_F3.yaml index 0d52e10..dbddfbc 100644 --- a/transforms/SYSCFG_F3.yaml +++ b/transforms/SYSCFG_F3.yaml @@ -7,3 +7,31 @@ transforms: fieldsets: CFGR1 from: FPU_IE\d to: FPU_IE + + - !DeleteEnums + from: ADC2_DMA_RMP_CFGR1 + bit_size: 1 + keep_desc: true + + - !DeleteEnums + from: (DAC1_TRIG5_RMP|DAC1_TRIG_RMP|DAC2_CH1_DMA_RMP|DAC_TRIG_RMP) + bit_size: 1 + keep_desc: true + + - !DeleteEnums + from: (TIM16_DMA_RMP|TIM17_DMA_RMP|TIM18_DAC2_OUT1_DMA_RMP|TIM1_ITR3_RMP|TIM6_DAC1_CH1_DMA_RMP|TIM6_DAC1_DMA_RMP|TIM6_DAC1_OUT1_DMA_RMP|TIM7_DAC1_CH2_DMA_RMP|TIM7_DAC1_OUT2_DMA_RMP) + bit_size: 1 + keep_desc: true + + - !DeleteEnums + from: USB_IT_RMP + bit_size: 1 + keep_desc: true + + - !MergeEnums + from: .*_FMP + to: FMP + keep_desc: true + + - !DeleteEnums + from: ^(BYP_ADDR_PAR|LOCKUP_LOCK|PVD_LOCK|SRAM_PARITY_LOCK)$