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Add missing RCC block for H7AB family

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This commit is contained in:
Ulf Lilleengen 2021-06-10 08:57:46 +02:00
parent 4837bee5df
commit af3e9e60a3
2 changed files with 3215 additions and 68 deletions
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136
data/registers/rcc_h7.yaml
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@ -1205,6 +1205,10 @@ fieldset/AHB1ENR:
bit_size: 1
description: ADC1/2 Peripheral Clocks Enable
name: ADC12EN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable
name: ARTEN
- bit_offset: 15
bit_size: 1
description: Ethernet MAC bus interface Clock Enable
@ -1237,10 +1241,6 @@ fieldset/AHB1ENR:
bit_size: 1
description: USB_PHY2 Clocks Enable
name: USB2ULPIEN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable
name: ARTEN
fieldset/AHB1LPENR:
description: RCC AHB1 Sleep Clock Register
fields:
@ -1256,6 +1256,10 @@ fieldset/AHB1LPENR:
bit_size: 1
description: ADC1/2 Peripheral Clocks Enable During CSleep Mode
name: ADC12LPEN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable During CSleep Mode
name: ARTLPEN
- bit_offset: 15
bit_size: 1
description: Ethernet MAC bus interface Clock Enable During CSleep Mode
@ -1276,6 +1280,10 @@ fieldset/AHB1LPENR:
bit_size: 1
description: USB_PHY1 clock enable during CSleep mode
name: USB1OTGHSULPILPEN
- bit_offset: 26
bit_size: 1
description: USB_PHY1 clock enable during CSleep mode
name: USB1ULPILPEN
- bit_offset: 27
bit_size: 1
description: USB2OTG peripheral clock enable during CSleep mode
@ -1284,14 +1292,6 @@ fieldset/AHB1LPENR:
bit_size: 1
description: USB_PHY2 clocks enable during CSleep mode
name: USB2OTGHSULPILPEN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable During CSleep Mode
name: ARTLPEN
- bit_offset: 26
bit_size: 1
description: USB_PHY1 clock enable during CSleep mode
name: USB1ULPILPEN
- bit_offset: 28
bit_size: 1
description: USB_PHY2 clocks enable during CSleep mode
@ -1311,6 +1311,10 @@ fieldset/AHB1RSTR:
bit_size: 1
description: ADC1&2 block reset
name: ADC12RST
- bit_offset: 14
bit_size: 1
description: ART block reset
name: ARTRST
- bit_offset: 15
bit_size: 1
description: ETH1MAC block reset
@ -1323,10 +1327,6 @@ fieldset/AHB1RSTR:
bit_size: 1
description: USB2OTG block reset
name: USB2OTGRST
- bit_offset: 14
bit_size: 1
description: ART block reset
name: ARTRST
fieldset/AHB2ENR:
description: RCC AHB2 Clock Register
fields:
@ -1482,6 +1482,10 @@ fieldset/AHB3LPENR:
bit_size: 1
description: FLITF Clock Enable During CSleep Mode
name: FLASHLPEN
- bit_offset: 8
bit_size: 1
description: FLITF Clock Enable During CSleep Mode
name: FLITFLPEN
- bit_offset: 12
bit_size: 1
description: FMC Peripheral Clocks Enable During CSleep Mode
@ -1510,10 +1514,6 @@ fieldset/AHB3LPENR:
bit_size: 1
description: AXISRAM Block Clock Enable During CSleep mode
name: AXISRAMLPEN
- bit_offset: 8
bit_size: 1
description: FLITF Clock Enable During CSleep Mode
name: FLITFLPEN
fieldset/AHB3RSTR:
description: RCC AHB3 Reset Register
fields:
@ -1854,6 +1854,10 @@ fieldset/APB1LENR:
bit_size: 1
description: LPTIM1 Peripheral Clocks Enable
name: LPTIM1EN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral clock enable
name: WWDG2EN
- bit_offset: 14
bit_size: 1
description: SPI2 Peripheral Clocks Enable
@ -1910,10 +1914,6 @@ fieldset/APB1LENR:
bit_size: 1
description: UART8 Peripheral Clocks Enable
name: UART8EN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral clock enable
name: WWDG2EN
fieldset/APB1LLPENR:
description: RCC APB1 Low Sleep Clock Register
fields:
@ -1957,6 +1957,10 @@ fieldset/APB1LLPENR:
bit_size: 1
description: LPTIM1 Peripheral Clocks Enable During CSleep Mode
name: LPTIM1LPEN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral Clocks Enable During CSleep Mode
name: WWDG2LPEN
- bit_offset: 14
bit_size: 1
description: SPI2 Peripheral Clocks Enable During CSleep Mode
@ -2013,10 +2017,6 @@ fieldset/APB1LLPENR:
bit_size: 1
description: UART8 Peripheral Clocks Enable During CSleep Mode
name: UART8LPEN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral Clocks Enable During CSleep Mode
name: WWDG2LPEN
fieldset/APB1LRSTR:
description: RCC APB1 Peripheral Reset Register
fields:
@ -2312,14 +2312,14 @@ fieldset/APB3ENR:
bit_size: 1
description: LTDC peripheral clock enable
name: LTDCEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable
name: WWDG1EN
- bit_offset: 4
bit_size: 1
description: DSI Peripheral clocks enable
name: DSIEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable
name: WWDG1EN
fieldset/APB3LPENR:
description: RCC APB3 Sleep Clock Register
fields:
@ -2327,14 +2327,14 @@ fieldset/APB3LPENR:
bit_size: 1
description: LTDC peripheral clock enable during CSleep mode
name: LTDCLPEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable During CSleep Mode
name: WWDG1LPEN
- bit_offset: 4
bit_size: 1
description: DSI Peripheral Clock Enable During CSleep Mode
name: DSILPEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable During CSleep Mode
name: WWDG1LPEN
fieldset/APB3RSTR:
description: RCC APB3 Peripheral Reset Register
fields:
@ -2554,6 +2554,10 @@ fieldset/C1_AHB1ENR:
bit_size: 1
description: ADC1/2 Peripheral Clocks Enable
name: ADC12EN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable
name: ARTEN
- bit_offset: 15
bit_size: 1
description: Ethernet MAC bus interface Clock Enable
@ -2582,10 +2586,6 @@ fieldset/C1_AHB1ENR:
bit_size: 1
description: USB_PHY2 Clocks Enable
name: USB2ULPIEN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable
name: ARTEN
fieldset/C1_AHB1LPENR:
description: RCC AHB1 Sleep Clock Register
fields:
@ -2601,6 +2601,10 @@ fieldset/C1_AHB1LPENR:
bit_size: 1
description: ADC1/2 Peripheral Clocks Enable During CSleep Mode
name: ADC12LPEN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable During CSleep Mode
name: ARTLPEN
- bit_offset: 15
bit_size: 1
description: Ethernet MAC bus interface Clock Enable During CSleep Mode
@ -2629,10 +2633,6 @@ fieldset/C1_AHB1LPENR:
bit_size: 1
description: USB_PHY2 clocks enable during CSleep mode
name: USB2ULPILPEN
- bit_offset: 14
bit_size: 1
description: ART Clock Enable During CSleep Mode
name: ARTLPEN
fieldset/C1_AHB2ENR:
description: RCC AHB2 Clock Register
fields:
@ -3000,6 +3000,10 @@ fieldset/C1_APB1LENR:
bit_size: 1
description: LPTIM1 Peripheral Clocks Enable
name: LPTIM1EN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral clock enable
name: WWDG2EN
- bit_offset: 14
bit_size: 1
description: SPI2 Peripheral Clocks Enable
@ -3056,10 +3060,6 @@ fieldset/C1_APB1LENR:
bit_size: 1
description: UART8 Peripheral Clocks Enable
name: UART8EN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral clock enable
name: WWDG2EN
fieldset/C1_APB1LLPENR:
description: RCC APB1 Low Sleep Clock Register
fields:
@ -3103,6 +3103,10 @@ fieldset/C1_APB1LLPENR:
bit_size: 1
description: LPTIM1 Peripheral Clocks Enable During CSleep Mode
name: LPTIM1LPEN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral Clocks Enable During CSleep Mode
name: WWDG2LPEN
- bit_offset: 14
bit_size: 1
description: SPI2 Peripheral Clocks Enable During CSleep Mode
@ -3159,10 +3163,6 @@ fieldset/C1_APB1LLPENR:
bit_size: 1
description: UART8 Peripheral Clocks Enable During CSleep Mode
name: UART8LPEN
- bit_offset: 11
bit_size: 1
description: WWDG2 peripheral Clocks Enable During CSleep Mode
name: WWDG2LPEN
fieldset/C1_APB2ENR:
description: RCC APB2 Clock Register
fields:
@ -3296,14 +3296,14 @@ fieldset/C1_APB3ENR:
bit_size: 1
description: LTDC peripheral clock enable
name: LTDCEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable
name: WWDG1EN
- bit_offset: 4
bit_size: 1
description: DSI Peripheral clocks enable
name: DSIEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable
name: WWDG1EN
fieldset/C1_APB3LPENR:
description: RCC APB3 Sleep Clock Register
fields:
@ -3311,14 +3311,14 @@ fieldset/C1_APB3LPENR:
bit_size: 1
description: LTDC peripheral clock enable during CSleep mode
name: LTDCLPEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable During CSleep Mode
name: WWDG1LPEN
- bit_offset: 4
bit_size: 1
description: DSI Peripheral Clock Enable During CSleep Mode
name: DSILPEN
- bit_offset: 6
bit_size: 1
description: WWDG1 Clock Enable During CSleep Mode
name: WWDG1LPEN
fieldset/C1_APB4ENR:
description: RCC APB4 Clock Register
fields:
@ -3806,6 +3806,10 @@ fieldset/D1CCIPR:
description: QUADSPI kernel clock source selection
enum: FMCSEL
name: QSPISEL
- bit_offset: 8
bit_size: 1
description: kernel clock source selection
name: DSISEL
- bit_offset: 16
bit_size: 1
description: SDMMC kernel clock source selection
@ -3816,10 +3820,6 @@ fieldset/D1CCIPR:
description: per_ck clock source selection
enum: CKPERSEL
name: CKPERSEL
- bit_offset: 8
bit_size: 1
description: kernel clock source selection
name: DSISEL
fieldset/D1CFGR:
description: RCC Domain 1 Clock Configuration Register
fields:
@ -3995,14 +3995,14 @@ fieldset/D3AMR:
bit_size: 1
description: Backup RAM Autonomous mode enable
name: BKPRAMAMEN
- bit_offset: 29
bit_size: 1
description: SRAM4 Autonomous mode enable
name: SRAM4AMEN
- bit_offset: 28
bit_size: 1
description: Backup RAM Autonomous mode enable
name: BKPSRAMAMEN
- bit_offset: 29
bit_size: 1
description: SRAM4 Autonomous mode enable
name: SRAM4AMEN
fieldset/D3CCIPR:
description: RCC Domain 3 Kernel Clock Configuration Register
fields:

3147
data/registers/rcc_h7ab.yaml Normal file
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