diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml
new file mode 100644
index 0000000..8a6fe68
--- /dev/null
+++ b/data/registers/rcc_f0.yaml
@@ -0,0 +1,1249 @@
+---
+block/RCC:
+  description: Reset and clock control
+  items:
+    - name: CR
+      description: Clock control register
+      byte_offset: 0
+      fieldset: CR
+    - name: CFGR
+      description: Clock configuration register (RCC_CFGR)
+      byte_offset: 4
+      fieldset: CFGR
+    - name: CIR
+      description: Clock interrupt register (RCC_CIR)
+      byte_offset: 8
+      fieldset: CIR
+    - name: APB2RSTR
+      description: APB2 peripheral reset register (RCC_APB2RSTR)
+      byte_offset: 12
+      fieldset: APB2RSTR
+    - name: APB1RSTR
+      description: APB1 peripheral reset register (RCC_APB1RSTR)
+      byte_offset: 16
+      fieldset: APB1RSTR
+    - name: AHBENR
+      description: AHB Peripheral Clock enable register (RCC_AHBENR)
+      byte_offset: 20
+      fieldset: AHBENR
+    - name: APB2ENR
+      description: APB2 peripheral clock enable register (RCC_APB2ENR)
+      byte_offset: 24
+      fieldset: APB2ENR
+    - name: APB1ENR
+      description: APB1 peripheral clock enable register (RCC_APB1ENR)
+      byte_offset: 28
+      fieldset: APB1ENR
+    - name: BDCR
+      description: Backup domain control register (RCC_BDCR)
+      byte_offset: 32
+      fieldset: BDCR
+    - name: CSR
+      description: Control/status register (RCC_CSR)
+      byte_offset: 36
+      fieldset: CSR
+    - name: AHBRSTR
+      description: AHB peripheral reset register
+      byte_offset: 40
+      fieldset: AHBRSTR
+    - name: CFGR2
+      description: Clock configuration register 2
+      byte_offset: 44
+      fieldset: CFGR2
+    - name: CFGR3
+      description: Clock configuration register 3
+      byte_offset: 48
+      fieldset: CFGR3
+    - name: CR2
+      description: Clock control register 2
+      byte_offset: 52
+      fieldset: CR2
+fieldset/AHBENR:
+  description: AHB Peripheral Clock enable register (RCC_AHBENR)
+  fields:
+    - name: DMAEN
+      description: DMA clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2EN
+      description: DMA2 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: SRAMEN
+      description: SRAM interface clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: FLITFEN
+      description: FLITF clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: CRCEN
+      description: CRC clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: IOPAEN
+      description: I/O port A clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: IOPBEN
+      description: I/O port B clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: IOPCEN
+      description: I/O port C clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: IOPDEN
+      description: I/O port D clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: IOPEEN
+      description: I/O port E clock enable
+      bit_offset: 21
+      bit_size: 1
+    - name: IOPFEN
+      description: I/O port F clock enable
+      bit_offset: 22
+      bit_size: 1
+    - name: TSCEN
+      description: Touch sensing controller clock enable
+      bit_offset: 24
+      bit_size: 1
+fieldset/AHBRSTR:
+  description: AHB peripheral reset register
+  fields:
+    - name: IOPARST
+      description: I/O port A reset
+      bit_offset: 17
+      bit_size: 1
+    - name: IOPBRST
+      description: I/O port B reset
+      bit_offset: 18
+      bit_size: 1
+    - name: IOPCRST
+      description: I/O port C reset
+      bit_offset: 19
+      bit_size: 1
+    - name: IOPDRST
+      description: I/O port D reset
+      bit_offset: 20
+      bit_size: 1
+    - name: IOPERST
+      description: I/O port E reset
+      bit_offset: 21
+      bit_size: 1
+    - name: IOPFRST
+      description: I/O port F reset
+      bit_offset: 22
+      bit_size: 1
+    - name: TSCRST
+      description: Touch sensing controller reset
+      bit_offset: 24
+      bit_size: 1
+fieldset/APB1ENR:
+  description: APB1 peripheral clock enable register (RCC_APB1ENR)
+  fields:
+    - name: TIM2EN
+      description: Timer 2 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: TIM3EN
+      description: Timer 3 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM6EN
+      description: Timer 6 clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM7EN
+      description: TIM7 timer clock enable
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM14EN
+      description: Timer 14 clock enable
+      bit_offset: 8
+      bit_size: 1
+    - name: WWDGEN
+      description: Window watchdog clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2EN
+      description: SPI 2 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: USART2EN
+      description: USART 2 clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: USART3EN
+      description: USART3 clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: USART4EN
+      description: USART4 clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: USART5EN
+      description: USART5 clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C1EN
+      description: I2C 1 clock enable
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C2EN
+      description: I2C 2 clock enable
+      bit_offset: 22
+      bit_size: 1
+    - name: USBEN
+      description: USB interface clock enable
+      bit_offset: 23
+      bit_size: 1
+    - name: CANEN
+      description: CAN interface clock enable
+      bit_offset: 25
+      bit_size: 1
+    - name: CRSEN
+      description: Clock Recovery System interface clock enable
+      bit_offset: 27
+      bit_size: 1
+    - name: PWREN
+      description: Power interface clock enable
+      bit_offset: 28
+      bit_size: 1
+    - name: DACEN
+      description: DAC interface clock enable
+      bit_offset: 29
+      bit_size: 1
+    - name: CECEN
+      description: HDMI CEC interface clock enable
+      bit_offset: 30
+      bit_size: 1
+fieldset/APB1RSTR:
+  description: APB1 peripheral reset register (RCC_APB1RSTR)
+  fields:
+    - name: TIM2RST
+      description: Timer 2 reset
+      bit_offset: 0
+      bit_size: 1
+    - name: TIM3RST
+      description: Timer 3 reset
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM6RST
+      description: Timer 6 reset
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM7RST
+      description: TIM7 timer reset
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM14RST
+      description: Timer 14 reset
+      bit_offset: 8
+      bit_size: 1
+    - name: WWDGRST
+      description: Window watchdog reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2RST
+      description: SPI2 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: USART2RST
+      description: USART 2 reset
+      bit_offset: 17
+      bit_size: 1
+    - name: USART3RST
+      description: USART3 reset
+      bit_offset: 18
+      bit_size: 1
+    - name: USART4RST
+      description: USART4 reset
+      bit_offset: 19
+      bit_size: 1
+    - name: USART5RST
+      description: USART5 reset
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C1RST
+      description: I2C1 reset
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C2RST
+      description: I2C2 reset
+      bit_offset: 22
+      bit_size: 1
+    - name: USBRST
+      description: USB interface reset
+      bit_offset: 23
+      bit_size: 1
+    - name: CANRST
+      description: CAN interface reset
+      bit_offset: 25
+      bit_size: 1
+    - name: CRSRST
+      description: Clock Recovery System interface reset
+      bit_offset: 27
+      bit_size: 1
+    - name: PWRRST
+      description: Power interface reset
+      bit_offset: 28
+      bit_size: 1
+    - name: DACRST
+      description: DAC interface reset
+      bit_offset: 29
+      bit_size: 1
+    - name: CECRST
+      description: HDMI CEC reset
+      bit_offset: 30
+      bit_size: 1
+fieldset/APB2ENR:
+  description: APB2 peripheral clock enable register (RCC_APB2ENR)
+  fields:
+    - name: SYSCFGEN
+      description: SYSCFG clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: USART6EN
+      description: USART6 clock enable
+      bit_offset: 5
+      bit_size: 1
+    - name: USART7EN
+      description: USART7 clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: USART8EN
+      description: USART8 clock enable
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCEN
+      description: ADC 1 interface clock enable
+      bit_offset: 9
+      bit_size: 1
+    - name: TIM1EN
+      description: TIM1 Timer clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1EN
+      description: SPI 1 clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1EN
+      description: USART1 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM15EN
+      description: TIM15 timer clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TIM16EN
+      description: TIM16 timer clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17EN
+      description: TIM17 timer clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: DBGMCUEN
+      description: MCU debug module clock enable
+      bit_offset: 22
+      bit_size: 1
+fieldset/APB2RSTR:
+  description: APB2 peripheral reset register (RCC_APB2RSTR)
+  fields:
+    - name: SYSCFGRST
+      description: SYSCFG and COMP reset
+      bit_offset: 0
+      bit_size: 1
+    - name: USART6RST
+      description: USART6 reset
+      bit_offset: 5
+      bit_size: 1
+    - name: USART7RST
+      description: USART7 reset
+      bit_offset: 6
+      bit_size: 1
+    - name: USART8RST
+      description: USART8 reset
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCRST
+      description: ADC interface reset
+      bit_offset: 9
+      bit_size: 1
+    - name: TIM1RST
+      description: TIM1 timer reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1RST
+      description: SPI 1 reset
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1RST
+      description: USART1 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM15RST
+      description: TIM15 timer reset
+      bit_offset: 16
+      bit_size: 1
+    - name: TIM16RST
+      description: TIM16 timer reset
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17RST
+      description: TIM17 timer reset
+      bit_offset: 18
+      bit_size: 1
+    - name: DBGMCURST
+      description: Debug MCU reset
+      bit_offset: 22
+      bit_size: 1
+fieldset/BDCR:
+  description: Backup domain control register (RCC_BDCR)
+  fields:
+    - name: LSEON
+      description: External Low Speed oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDY
+      description: External Low Speed oscillator ready
+      bit_offset: 1
+      bit_size: 1
+      enum_read: LSERDYR
+    - name: LSEBYP
+      description: External Low Speed oscillator bypass
+      bit_offset: 2
+      bit_size: 1
+      enum: LSEBYP
+    - name: LSEDRV
+      description: LSE oscillator drive capability
+      bit_offset: 3
+      bit_size: 2
+      enum: LSEDRV
+    - name: RTCSEL
+      description: RTC clock source selection
+      bit_offset: 8
+      bit_size: 2
+      enum: RTCSEL
+    - name: RTCEN
+      description: RTC clock enable
+      bit_offset: 15
+      bit_size: 1
+    - name: BDRST
+      description: Backup domain software reset
+      bit_offset: 16
+      bit_size: 1
+fieldset/CFGR:
+  description: Clock configuration register (RCC_CFGR)
+  fields:
+    - name: SW
+      description: System clock Switch
+      bit_offset: 0
+      bit_size: 2
+      enum: SW
+    - name: SWS
+      description: System Clock Switch Status
+      bit_offset: 2
+      bit_size: 2
+      enum_read: SWSR
+    - name: HPRE
+      description: AHB prescaler
+      bit_offset: 4
+      bit_size: 4
+      enum: HPRE
+    - name: PPRE
+      description: APB Low speed prescaler (APB1)
+      bit_offset: 8
+      bit_size: 3
+      enum: PPRE
+    - name: ADCPRE
+      description: APCPRE is deprecated. See ADC field in CFGR2 register.
+      bit_offset: 14
+      bit_size: 1
+    - name: PLLSRC
+      description: PLL input clock source
+      bit_offset: 15
+      bit_size: 2
+      enum: PLLSRC
+    - name: PLLXTPRE
+      description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning"
+      bit_offset: 17
+      bit_size: 1
+      enum: PLLXTPRE
+    - name: PLLMUL
+      description: PLL Multiplication Factor
+      bit_offset: 18
+      bit_size: 4
+      enum: PLLMUL
+    - name: MCO
+      description: Microcontroller clock output
+      bit_offset: 24
+      bit_size: 3
+      enum: MCO
+    - name: MCOPRE
+      description: Microcontroller Clock Output Prescaler
+      bit_offset: 28
+      bit_size: 3
+      enum: MCOPRE
+    - name: PLLNODIV
+      description: PLL clock not divided for MCO
+      bit_offset: 31
+      bit_size: 1
+      enum: PLLNODIV
+fieldset/CFGR2:
+  description: Clock configuration register 2
+  fields:
+    - name: PREDIV
+      description: PREDIV division factor
+      bit_offset: 0
+      bit_size: 4
+      enum: PREDIV
+fieldset/CFGR3:
+  description: Clock configuration register 3
+  fields:
+    - name: USART1SW
+      description: USART1 clock source selection
+      bit_offset: 0
+      bit_size: 2
+      enum: USARTSW
+    - name: I2C1SW
+      description: I2C1 clock source selection
+      bit_offset: 4
+      bit_size: 1
+      enum: ICSW
+    - name: CECSW
+      description: HDMI CEC clock source selection
+      bit_offset: 6
+      bit_size: 1
+      enum: CECSW
+    - name: USBSW
+      description: USB clock source selection
+      bit_offset: 7
+      bit_size: 1
+      enum: USBSW
+    - name: ADCSW
+      description: ADCSW is deprecated. See ADC field in CFGR2 register.
+      bit_offset: 8
+      bit_size: 1
+    - name: USART2SW
+      description: USART2 clock source selection
+      bit_offset: 16
+      bit_size: 2
+      enum: USARTSW
+    - name: USART3SW
+      description: USART3 clock source
+      bit_offset: 18
+      bit_size: 2
+      enum: USARTSW
+fieldset/CIR:
+  description: Clock interrupt register (RCC_CIR)
+  fields:
+    - name: LSIRDYF
+      description: LSI Ready Interrupt flag
+      bit_offset: 0
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: LSERDYF
+      description: LSE Ready Interrupt flag
+      bit_offset: 1
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSIRDYF
+      description: HSI Ready Interrupt flag
+      bit_offset: 2
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSERDYF
+      description: HSE Ready Interrupt flag
+      bit_offset: 3
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: PLLRDYF
+      description: PLL Ready Interrupt flag
+      bit_offset: 4
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSI14RDYF
+      description: HSI14 ready interrupt flag
+      bit_offset: 5
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSI48RDYF
+      description: HSI48 ready interrupt flag
+      bit_offset: 6
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: CSSF
+      description: Clock Security System Interrupt flag
+      bit_offset: 7
+      bit_size: 1
+      enum_read: CSSFR
+    - name: LSIRDYIE
+      description: LSI Ready Interrupt Enable
+      bit_offset: 8
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: LSERDYIE
+      description: LSE Ready Interrupt Enable
+      bit_offset: 9
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSIRDYIE
+      description: HSI Ready Interrupt Enable
+      bit_offset: 10
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSERDYIE
+      description: HSE Ready Interrupt Enable
+      bit_offset: 11
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: PLLRDYIE
+      description: PLL Ready Interrupt Enable
+      bit_offset: 12
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSI14RDYIE
+      description: HSI14 ready interrupt enable
+      bit_offset: 13
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSI48RDYIE
+      description: HSI48 ready interrupt enable
+      bit_offset: 14
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: LSIRDYC
+      description: LSI Ready Interrupt Clear
+      bit_offset: 16
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: LSERDYC
+      description: LSE Ready Interrupt Clear
+      bit_offset: 17
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSIRDYC
+      description: HSI Ready Interrupt Clear
+      bit_offset: 18
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSERDYC
+      description: HSE Ready Interrupt Clear
+      bit_offset: 19
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: PLLRDYC
+      description: PLL Ready Interrupt Clear
+      bit_offset: 20
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSI14RDYC
+      description: HSI 14 MHz Ready Interrupt Clear
+      bit_offset: 21
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSI48RDYC
+      description: HSI48 Ready Interrupt Clear
+      bit_offset: 22
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: CSSC
+      description: Clock security system interrupt clear
+      bit_offset: 23
+      bit_size: 1
+      enum_write: CSSCW
+fieldset/CR:
+  description: Clock control register
+  fields:
+    - name: HSION
+      description: Internal High Speed clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: HSIRDY
+      description: Internal High Speed clock ready flag
+      bit_offset: 1
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSITRIM
+      description: Internal High Speed clock trimming
+      bit_offset: 3
+      bit_size: 5
+    - name: HSICAL
+      description: Internal High Speed clock Calibration
+      bit_offset: 8
+      bit_size: 8
+    - name: HSEON
+      description: External High Speed clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: HSERDY
+      description: External High Speed clock ready flag
+      bit_offset: 17
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSEBYP
+      description: External High Speed clock Bypass
+      bit_offset: 18
+      bit_size: 1
+      enum: HSEBYP
+    - name: CSSON
+      description: Clock Security System enable
+      bit_offset: 19
+      bit_size: 1
+    - name: PLLON
+      description: PLL enable
+      bit_offset: 24
+      bit_size: 1
+    - name: PLLRDY
+      description: PLL clock ready flag
+      bit_offset: 25
+      bit_size: 1
+      enum_read: HSIRDYR
+fieldset/CR2:
+  description: Clock control register 2
+  fields:
+    - name: HSI14ON
+      description: HSI14 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: HSI14RDY
+      description: HR14 clock ready flag
+      bit_offset: 1
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSI14DIS
+      description: HSI14 clock request from ADC disable
+      bit_offset: 2
+      bit_size: 1
+      enum: HSIDIS
+    - name: HSI14TRIM
+      description: HSI14 clock trimming
+      bit_offset: 3
+      bit_size: 5
+    - name: HSI14CAL
+      description: HSI14 clock calibration
+      bit_offset: 8
+      bit_size: 8
+    - name: HSI48ON
+      description: HSI48 clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: HSI48RDY
+      description: HSI48 clock ready flag
+      bit_offset: 17
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSI48CAL
+      description: HSI48 factory clock calibration
+      bit_offset: 24
+      bit_size: 8
+fieldset/CSR:
+  description: Control/status register (RCC_CSR)
+  fields:
+    - name: LSION
+      description: Internal low speed oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSIRDY
+      description: Internal low speed oscillator ready
+      bit_offset: 1
+      bit_size: 1
+      enum_read: LSIRDYR
+    - name: V18PWRRSTF
+      description: 1.8 V domain reset flag
+      bit_offset: 23
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: RMVF
+      description: Remove reset flag
+      bit_offset: 24
+      bit_size: 1
+      enum_write: RMVFW
+    - name: OBLRSTF
+      description: Option byte loader reset flag
+      bit_offset: 25
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: PINRSTF
+      description: PIN reset flag
+      bit_offset: 26
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: PORRSTF
+      description: POR/PDR reset flag
+      bit_offset: 27
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: SFTRSTF
+      description: Software reset flag
+      bit_offset: 28
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: IWDGRSTF
+      description: Independent watchdog reset flag
+      bit_offset: 29
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: WWDGRSTF
+      description: Window watchdog reset flag
+      bit_offset: 30
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: LPWRRSTF
+      description: Low-power reset flag
+      bit_offset: 31
+      bit_size: 1
+      enum_read: OBLRSTFR
+enum/CECSW:
+  bit_size: 1
+  variants:
+    - name: HSI_Div244
+      description: HSI clock divided by 244 selected as CEC clock source
+      value: 0
+    - name: LSE
+      description: LSE clock selected as CEC clock source
+      value: 1
+enum/CSSCW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clear CSSF flag
+      value: 1
+enum/CSSFR:
+  bit_size: 1
+  variants:
+    - name: NotInterrupted
+      description: No clock security interrupt caused by HSE clock failure
+      value: 0
+    - name: Interrupted
+      description: Clock security interrupt caused by HSE clock failure
+      value: 1
+enum/HPRE:
+  bit_size: 4
+  variants:
+    - name: Div1
+      description: SYSCLK not divided
+      value: 0
+    - name: Div2
+      description: SYSCLK divided by 2
+      value: 8
+    - name: Div4
+      description: SYSCLK divided by 4
+      value: 9
+    - name: Div8
+      description: SYSCLK divided by 8
+      value: 10
+    - name: Div16
+      description: SYSCLK divided by 16
+      value: 11
+    - name: Div64
+      description: SYSCLK divided by 64
+      value: 12
+    - name: Div128
+      description: SYSCLK divided by 128
+      value: 13
+    - name: Div256
+      description: SYSCLK divided by 256
+      value: 14
+    - name: Div512
+      description: SYSCLK divided by 512
+      value: 15
+enum/HSEBYP:
+  bit_size: 1
+  variants:
+    - name: NotBypassed
+      description: HSE crystal oscillator not bypassed
+      value: 0
+    - name: Bypassed
+      description: HSE crystal oscillator bypassed with external clock
+      value: 1
+enum/HSIDIS:
+  bit_size: 1
+  variants:
+    - name: Allow
+      description: ADC can turn on the HSI14 oscillator
+      value: 0
+    - name: Disallow
+      description: ADC can not turn on the HSI14 oscillator
+      value: 1
+enum/HSIRDYR:
+  bit_size: 1
+  variants:
+    - name: NotReady
+      description: HSI48 oscillator ready
+      value: 0
+    - name: Ready
+      description: HSI48 oscillator ready
+      value: 1
+enum/ICSW:
+  bit_size: 1
+  variants:
+    - name: HSI
+      description: HSI clock selected as I2C clock source
+      value: 0
+    - name: SYSCLK
+      description: SYSCLK clock selected as I2C clock source
+      value: 1
+enum/LSEBYP:
+  bit_size: 1
+  variants:
+    - name: NotBypassed
+      description: LSE crystal oscillator not bypassed
+      value: 0
+    - name: Bypassed
+      description: LSE crystal oscillator bypassed with external clock
+      value: 1
+enum/LSEDRV:
+  bit_size: 2
+  variants:
+    - name: Low
+      description: Low drive capacity
+      value: 0
+    - name: MediumHigh
+      description: Medium-high drive capacity
+      value: 1
+    - name: MediumLow
+      description: Medium-low drive capacity
+      value: 2
+    - name: High
+      description: High drive capacity
+      value: 3
+enum/LSERDYR:
+  bit_size: 1
+  variants:
+    - name: NotReady
+      description: LSE oscillator not ready
+      value: 0
+    - name: Ready
+      description: LSE oscillator ready
+      value: 1
+enum/LSIRDYCW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clear interrupt flag
+      value: 1
+enum/LSIRDYFR:
+  bit_size: 1
+  variants:
+    - name: NotInterrupted
+      description: No clock ready interrupt
+      value: 0
+    - name: Interrupted
+      description: Clock ready interrupt
+      value: 1
+enum/LSIRDYIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Interrupt enabled
+      value: 1
+enum/LSIRDYR:
+  bit_size: 1
+  variants:
+    - name: NotReady
+      description: LSI oscillator not ready
+      value: 0
+    - name: Ready
+      description: LSI oscillator ready
+      value: 1
+enum/MCO:
+  bit_size: 3
+  variants:
+    - name: NoMCO
+      description: "MCO output disabled, no clock on MCO"
+      value: 0
+    - name: HSI14
+      description: Internal RC 14 MHz (HSI14) oscillator clock selected
+      value: 1
+    - name: LSI
+      description: Internal low speed (LSI) oscillator clock selected
+      value: 2
+    - name: LSE
+      description: External low speed (LSE) oscillator clock selected
+      value: 3
+    - name: SYSCLK
+      description: System clock selected
+      value: 4
+    - name: HSI
+      description: Internal RC 8 MHz (HSI) oscillator clock selected
+      value: 5
+    - name: HSE
+      description: External 4-32 MHz (HSE) oscillator clock selected
+      value: 6
+    - name: PLL
+      description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"
+      value: 7
+    - name: HSI48
+      description: Internal RC 48 MHz (HSI48) oscillator clock selected
+      value: 8
+enum/MCOPRE:
+  bit_size: 3
+  variants:
+    - name: Div1
+      description: MCO is divided by 1
+      value: 0
+    - name: Div2
+      description: MCO is divided by 2
+      value: 1
+    - name: Div4
+      description: MCO is divided by 4
+      value: 2
+    - name: Div8
+      description: MCO is divided by 8
+      value: 3
+    - name: Div16
+      description: MCO is divided by 16
+      value: 4
+    - name: Div32
+      description: MCO is divided by 32
+      value: 5
+    - name: Div64
+      description: MCO is divided by 64
+      value: 6
+    - name: Div128
+      description: MCO is divided by 128
+      value: 7
+enum/OBLRSTFR:
+  bit_size: 1
+  variants:
+    - name: NoReset
+      description: No reset has occured
+      value: 0
+    - name: Reset
+      description: A reset has occured
+      value: 1
+enum/PLLMUL:
+  bit_size: 4
+  variants:
+    - name: Mul2
+      description: PLL input clock x2
+      value: 0
+    - name: Mul3
+      description: PLL input clock x3
+      value: 1
+    - name: Mul4
+      description: PLL input clock x4
+      value: 2
+    - name: Mul5
+      description: PLL input clock x5
+      value: 3
+    - name: Mul6
+      description: PLL input clock x6
+      value: 4
+    - name: Mul7
+      description: PLL input clock x7
+      value: 5
+    - name: Mul8
+      description: PLL input clock x8
+      value: 6
+    - name: Mul9
+      description: PLL input clock x9
+      value: 7
+    - name: Mul10
+      description: PLL input clock x10
+      value: 8
+    - name: Mul11
+      description: PLL input clock x11
+      value: 9
+    - name: Mul12
+      description: PLL input clock x12
+      value: 10
+    - name: Mul13
+      description: PLL input clock x13
+      value: 11
+    - name: Mul14
+      description: PLL input clock x14
+      value: 12
+    - name: Mul15
+      description: PLL input clock x15
+      value: 13
+    - name: Mul16
+      description: PLL input clock x16
+      value: 14
+    - name: Mul16x
+      description: PLL input clock x16
+      value: 15
+enum/PLLNODIV:
+  bit_size: 1
+  variants:
+    - name: Div2
+      description: PLL is divided by 2 for MCO
+      value: 0
+    - name: Div1
+      description: PLL is not divided for MCO
+      value: 1
+enum/PLLSRC:
+  bit_size: 2
+  variants:
+    - name: HSI_Div2
+      description: HSI divided by 2 selected as PLL input clock
+      value: 0
+    - name: HSI_Div_PREDIV
+      description: HSI divided by PREDIV selected as PLL input clock
+      value: 1
+    - name: HSE_Div_PREDIV
+      description: HSE divided by PREDIV selected as PLL input clock
+      value: 2
+    - name: HSI48_Div_PREDIV
+      description: HSI48 divided by PREDIV selected as PLL input clock
+      value: 3
+enum/PLLXTPRE:
+  bit_size: 1
+  variants:
+    - name: Div1
+      description: HSE clock not divided
+      value: 0
+    - name: Div2
+      description: HSE clock divided by 2
+      value: 1
+enum/PPRE:
+  bit_size: 3
+  variants:
+    - name: Div1
+      description: HCLK not divided
+      value: 0
+    - name: Div2
+      description: HCLK divided by 2
+      value: 4
+    - name: Div4
+      description: HCLK divided by 4
+      value: 5
+    - name: Div8
+      description: HCLK divided by 8
+      value: 6
+    - name: Div16
+      description: HCLK divided by 16
+      value: 7
+enum/PREDIV:
+  bit_size: 4
+  variants:
+    - name: Div1
+      description: PREDIV input clock not divided
+      value: 0
+    - name: Div2
+      description: PREDIV input clock divided by 2
+      value: 1
+    - name: Div3
+      description: PREDIV input clock divided by 3
+      value: 2
+    - name: Div4
+      description: PREDIV input clock divided by 4
+      value: 3
+    - name: Div5
+      description: PREDIV input clock divided by 5
+      value: 4
+    - name: Div6
+      description: PREDIV input clock divided by 6
+      value: 5
+    - name: Div7
+      description: PREDIV input clock divided by 7
+      value: 6
+    - name: Div8
+      description: PREDIV input clock divided by 8
+      value: 7
+    - name: Div9
+      description: PREDIV input clock divided by 9
+      value: 8
+    - name: Div10
+      description: PREDIV input clock divided by 10
+      value: 9
+    - name: Div11
+      description: PREDIV input clock divided by 11
+      value: 10
+    - name: Div12
+      description: PREDIV input clock divided by 12
+      value: 11
+    - name: Div13
+      description: PREDIV input clock divided by 13
+      value: 12
+    - name: Div14
+      description: PREDIV input clock divided by 14
+      value: 13
+    - name: Div15
+      description: PREDIV input clock divided by 15
+      value: 14
+    - name: Div16
+      description: PREDIV input clock divided by 16
+      value: 15
+enum/RMVFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clears the reset flag
+      value: 1
+enum/RTCSEL:
+  bit_size: 2
+  variants:
+    - name: NoClock
+      description: No clock
+      value: 0
+    - name: LSE
+      description: LSE oscillator clock used as RTC clock
+      value: 1
+    - name: LSI
+      description: LSI oscillator clock used as RTC clock
+      value: 2
+    - name: HSE
+      description: HSE oscillator clock divided by a prescaler used as RTC clock
+      value: 3
+enum/SW:
+  bit_size: 2
+  variants:
+    - name: HSI
+      description: HSI selected as system clock
+      value: 0
+    - name: HSE
+      description: HSE selected as system clock
+      value: 1
+    - name: PLL
+      description: PLL selected as system clock
+      value: 2
+    - name: HSI48
+      description: HSI48 selected as system clock (when available)
+      value: 3
+enum/SWSR:
+  bit_size: 2
+  variants:
+    - name: HSI
+      description: HSI oscillator used as system clock
+      value: 0
+    - name: HSE
+      description: HSE oscillator used as system clock
+      value: 1
+    - name: PLL
+      description: PLL used as system clock
+      value: 2
+    - name: HSI48
+      description: HSI48 used as system clock (when avaiable)
+      value: 3
+enum/USARTSW:
+  bit_size: 2
+  variants:
+    - name: PCLK
+      description: PCLK selected as USART clock source
+      value: 0
+    - name: SYSCLK
+      description: SYSCLK selected as USART clock source
+      value: 1
+    - name: LSE
+      description: LSE selected as USART clock source
+      value: 2
+    - name: HSI
+      description: HSI selected as USART clock source
+      value: 3
+enum/USBSW:
+  bit_size: 1
+  variants:
+    - name: HSI48
+      description: HSI48 selected as USB clock source
+      value: 0
+    - name: PLLCLK
+      description: PLL clock selected as USB clock source
+      value: 1
diff --git a/data/registers/rcc_f0x0.yaml b/data/registers/rcc_f0x0.yaml
new file mode 100644
index 0000000..e68b7b4
--- /dev/null
+++ b/data/registers/rcc_f0x0.yaml
@@ -0,0 +1,1153 @@
+---
+block/RCC:
+  description: Reset and clock control
+  items:
+    - name: CR
+      description: Clock control register
+      byte_offset: 0
+      fieldset: CR
+    - name: CFGR
+      description: Clock configuration register (RCC_CFGR)
+      byte_offset: 4
+      fieldset: CFGR
+    - name: CIR
+      description: Clock interrupt register (RCC_CIR)
+      byte_offset: 8
+      fieldset: CIR
+    - name: APB2RSTR
+      description: APB2 peripheral reset register (RCC_APB2RSTR)
+      byte_offset: 12
+      fieldset: APB2RSTR
+    - name: APB1RSTR
+      description: APB1 peripheral reset register (RCC_APB1RSTR)
+      byte_offset: 16
+      fieldset: APB1RSTR
+    - name: AHBENR
+      description: AHB Peripheral Clock enable register (RCC_AHBENR)
+      byte_offset: 20
+      fieldset: AHBENR
+    - name: APB2ENR
+      description: APB2 peripheral clock enable register (RCC_APB2ENR)
+      byte_offset: 24
+      fieldset: APB2ENR
+    - name: APB1ENR
+      description: APB1 peripheral clock enable register (RCC_APB1ENR)
+      byte_offset: 28
+      fieldset: APB1ENR
+    - name: BDCR
+      description: Backup domain control register (RCC_BDCR)
+      byte_offset: 32
+      fieldset: BDCR
+    - name: CSR
+      description: Control/status register (RCC_CSR)
+      byte_offset: 36
+      fieldset: CSR
+    - name: AHBRSTR
+      description: AHB peripheral reset register
+      byte_offset: 40
+      fieldset: AHBRSTR
+    - name: CFGR2
+      description: Clock configuration register 2
+      byte_offset: 44
+      fieldset: CFGR2
+    - name: CFGR3
+      description: Clock configuration register 3
+      byte_offset: 48
+      fieldset: CFGR3
+    - name: CR2
+      description: Clock control register 2
+      byte_offset: 52
+      fieldset: CR2
+fieldset/AHBENR:
+  description: AHB Peripheral Clock enable register (RCC_AHBENR)
+  fields:
+    - name: DMAEN
+      description: DMA clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: SRAMEN
+      description: SRAM interface clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: FLITFEN
+      description: FLITF clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: CRCEN
+      description: CRC clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: IOPAEN
+      description: I/O port A clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: IOPBEN
+      description: I/O port B clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: IOPCEN
+      description: I/O port C clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: IOPDEN
+      description: I/O port D clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: IOPFEN
+      description: I/O port F clock enable
+      bit_offset: 22
+      bit_size: 1
+fieldset/AHBRSTR:
+  description: AHB peripheral reset register
+  fields:
+    - name: IOPARST
+      description: I/O port A reset
+      bit_offset: 17
+      bit_size: 1
+    - name: IOPBRST
+      description: I/O port B reset
+      bit_offset: 18
+      bit_size: 1
+    - name: IOPCRST
+      description: I/O port C reset
+      bit_offset: 19
+      bit_size: 1
+    - name: IOPDRST
+      description: I/O port D reset
+      bit_offset: 20
+      bit_size: 1
+    - name: IOPFRST
+      description: I/O port F reset
+      bit_offset: 22
+      bit_size: 1
+fieldset/APB1ENR:
+  description: APB1 peripheral clock enable register (RCC_APB1ENR)
+  fields:
+    - name: TIM3EN
+      description: Timer 3 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM6EN
+      description: Timer 6 clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM7EN
+      description: TIM7 timer clock enable
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM14EN
+      description: Timer 14 clock enable
+      bit_offset: 8
+      bit_size: 1
+    - name: WWDGEN
+      description: Window watchdog clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2EN
+      description: SPI 2 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: USART2EN
+      description: USART 2 clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: USART3EN
+      description: USART3 clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: USART4EN
+      description: USART4 clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: USART5EN
+      description: USART5 clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C1EN
+      description: I2C 1 clock enable
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C2EN
+      description: I2C 2 clock enable
+      bit_offset: 22
+      bit_size: 1
+    - name: USBEN
+      description: USB interface clock enable
+      bit_offset: 23
+      bit_size: 1
+    - name: PWREN
+      description: Power interface clock enable
+      bit_offset: 28
+      bit_size: 1
+fieldset/APB1RSTR:
+  description: APB1 peripheral reset register (RCC_APB1RSTR)
+  fields:
+    - name: TIM3RST
+      description: Timer 3 reset
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM6RST
+      description: Timer 6 reset
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM7RST
+      description: TIM7 timer reset
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM14RST
+      description: Timer 14 reset
+      bit_offset: 8
+      bit_size: 1
+    - name: WWDGRST
+      description: Window watchdog reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2RST
+      description: SPI2 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: USART2RST
+      description: USART 2 reset
+      bit_offset: 17
+      bit_size: 1
+    - name: USART3RST
+      description: USART3 reset
+      bit_offset: 18
+      bit_size: 1
+    - name: USART4RST
+      description: USART4 reset
+      bit_offset: 19
+      bit_size: 1
+    - name: USART5RST
+      description: USART5 reset
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C1RST
+      description: I2C1 reset
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C2RST
+      description: I2C2 reset
+      bit_offset: 22
+      bit_size: 1
+    - name: USBRST
+      description: USB interface reset
+      bit_offset: 23
+      bit_size: 1
+    - name: PWRRST
+      description: Power interface reset
+      bit_offset: 28
+      bit_size: 1
+fieldset/APB2ENR:
+  description: APB2 peripheral clock enable register (RCC_APB2ENR)
+  fields:
+    - name: SYSCFGEN
+      description: SYSCFG clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: USART6EN
+      description: USART6 clock enable
+      bit_offset: 5
+      bit_size: 1
+    - name: ADCEN
+      description: ADC 1 interface clock enable
+      bit_offset: 9
+      bit_size: 1
+    - name: TIM1EN
+      description: TIM1 Timer clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1EN
+      description: SPI 1 clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1EN
+      description: USART1 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM15EN
+      description: TIM15 timer clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TIM16EN
+      description: TIM16 timer clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17EN
+      description: TIM17 timer clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: DBGMCUEN
+      description: MCU debug module clock enable
+      bit_offset: 22
+      bit_size: 1
+fieldset/APB2RSTR:
+  description: APB2 peripheral reset register (RCC_APB2RSTR)
+  fields:
+    - name: SYSCFGRST
+      description: SYSCFG and COMP reset
+      bit_offset: 0
+      bit_size: 1
+    - name: USART6RST
+      description: USART6 reset
+      bit_offset: 5
+      bit_size: 1
+    - name: ADCRST
+      description: ADC interface reset
+      bit_offset: 9
+      bit_size: 1
+    - name: TIM1RST
+      description: TIM1 timer reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1RST
+      description: SPI 1 reset
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1RST
+      description: USART1 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM15RST
+      description: TIM15 timer reset
+      bit_offset: 16
+      bit_size: 1
+    - name: TIM16RST
+      description: TIM16 timer reset
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17RST
+      description: TIM17 timer reset
+      bit_offset: 18
+      bit_size: 1
+    - name: DBGMCURST
+      description: Debug MCU reset
+      bit_offset: 22
+      bit_size: 1
+fieldset/BDCR:
+  description: Backup domain control register (RCC_BDCR)
+  fields:
+    - name: LSEON
+      description: External Low Speed oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDY
+      description: External Low Speed oscillator ready
+      bit_offset: 1
+      bit_size: 1
+      enum_read: LSERDYR
+    - name: LSEBYP
+      description: External Low Speed oscillator bypass
+      bit_offset: 2
+      bit_size: 1
+      enum: LSEBYP
+    - name: LSEDRV
+      description: LSE oscillator drive capability
+      bit_offset: 3
+      bit_size: 2
+      enum: LSEDRV
+    - name: RTCSEL
+      description: RTC clock source selection
+      bit_offset: 8
+      bit_size: 2
+      enum: RTCSEL
+    - name: RTCEN
+      description: RTC clock enable
+      bit_offset: 15
+      bit_size: 1
+    - name: BDRST
+      description: Backup domain software reset
+      bit_offset: 16
+      bit_size: 1
+fieldset/CFGR:
+  description: Clock configuration register (RCC_CFGR)
+  fields:
+    - name: SW
+      description: System clock Switch
+      bit_offset: 0
+      bit_size: 2
+      enum: SW
+    - name: SWS
+      description: System Clock Switch Status
+      bit_offset: 2
+      bit_size: 2
+      enum_read: SWSR
+    - name: HPRE
+      description: AHB prescaler
+      bit_offset: 4
+      bit_size: 4
+      enum: HPRE
+    - name: PPRE
+      description: APB Low speed prescaler (APB1)
+      bit_offset: 8
+      bit_size: 3
+      enum: PPRE
+    - name: ADCPRE
+      description: APCPRE is deprecated. See ADC field in CFGR2 register.
+      bit_offset: 14
+      bit_size: 1
+    - name: PLLSRC
+      description: PLL input clock source
+      bit_offset: 16
+      bit_size: 1
+      enum: PLLSRC
+    - name: PLLXTPRE
+      description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning"
+      bit_offset: 17
+      bit_size: 1
+      enum: PLLXTPRE
+    - name: PLLMUL
+      description: PLL Multiplication Factor
+      bit_offset: 18
+      bit_size: 4
+      enum: PLLMUL
+    - name: MCO
+      description: Microcontroller clock output
+      bit_offset: 24
+      bit_size: 3
+      enum: MCO
+    - name: MCOPRE
+      description: Microcontroller Clock Output Prescaler
+      bit_offset: 28
+      bit_size: 3
+      enum: MCOPRE
+    - name: PLLNODIV
+      description: PLL clock not divided for MCO
+      bit_offset: 31
+      bit_size: 1
+      enum: PLLNODIV
+fieldset/CFGR2:
+  description: Clock configuration register 2
+  fields:
+    - name: PREDIV
+      description: PREDIV division factor
+      bit_offset: 0
+      bit_size: 4
+      enum: PREDIV
+fieldset/CFGR3:
+  description: Clock configuration register 3
+  fields:
+    - name: USART1SW
+      description: USART1 clock source selection
+      bit_offset: 0
+      bit_size: 2
+      enum: USARTSW
+    - name: I2C1SW
+      description: I2C1 clock source selection
+      bit_offset: 4
+      bit_size: 1
+      enum: ICSW
+    - name: USBSW
+      description: USB clock source selection
+      bit_offset: 7
+      bit_size: 1
+      enum: USBSW
+    - name: ADCSW
+      description: ADCSW is deprecated. See ADC field in CFGR2 register.
+      bit_offset: 8
+      bit_size: 1
+    - name: USART2SW
+      description: USART2 clock source selection
+      bit_offset: 16
+      bit_size: 2
+      enum: USARTSW
+    - name: USART3SW
+      description: USART3 clock source
+      bit_offset: 18
+      bit_size: 2
+      enum: USARTSW
+fieldset/CIR:
+  description: Clock interrupt register (RCC_CIR)
+  fields:
+    - name: LSIRDYF
+      description: LSI Ready Interrupt flag
+      bit_offset: 0
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: LSERDYF
+      description: LSE Ready Interrupt flag
+      bit_offset: 1
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSIRDYF
+      description: HSI Ready Interrupt flag
+      bit_offset: 2
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSERDYF
+      description: HSE Ready Interrupt flag
+      bit_offset: 3
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: PLLRDYF
+      description: PLL Ready Interrupt flag
+      bit_offset: 4
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSI14RDYF
+      description: HSI14 ready interrupt flag
+      bit_offset: 5
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: HSI48RDYF
+      description: HSI48 ready interrupt flag
+      bit_offset: 6
+      bit_size: 1
+      enum_read: LSIRDYFR
+    - name: CSSF
+      description: Clock Security System Interrupt flag
+      bit_offset: 7
+      bit_size: 1
+      enum_read: CSSFR
+    - name: LSIRDYIE
+      description: LSI Ready Interrupt Enable
+      bit_offset: 8
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: LSERDYIE
+      description: LSE Ready Interrupt Enable
+      bit_offset: 9
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSIRDYIE
+      description: HSI Ready Interrupt Enable
+      bit_offset: 10
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSERDYIE
+      description: HSE Ready Interrupt Enable
+      bit_offset: 11
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: PLLRDYIE
+      description: PLL Ready Interrupt Enable
+      bit_offset: 12
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSI14RDYIE
+      description: HSI14 ready interrupt enable
+      bit_offset: 13
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: HSI48RDYIE
+      description: HSI48 ready interrupt enable
+      bit_offset: 14
+      bit_size: 1
+      enum: LSIRDYIE
+    - name: LSIRDYC
+      description: LSI Ready Interrupt Clear
+      bit_offset: 16
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: LSERDYC
+      description: LSE Ready Interrupt Clear
+      bit_offset: 17
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSIRDYC
+      description: HSI Ready Interrupt Clear
+      bit_offset: 18
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSERDYC
+      description: HSE Ready Interrupt Clear
+      bit_offset: 19
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: PLLRDYC
+      description: PLL Ready Interrupt Clear
+      bit_offset: 20
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSI14RDYC
+      description: HSI 14 MHz Ready Interrupt Clear
+      bit_offset: 21
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: HSI48RDYC
+      description: HSI48 Ready Interrupt Clear
+      bit_offset: 22
+      bit_size: 1
+      enum_write: LSIRDYCW
+    - name: CSSC
+      description: Clock security system interrupt clear
+      bit_offset: 23
+      bit_size: 1
+      enum_write: CSSCW
+fieldset/CR:
+  description: Clock control register
+  fields:
+    - name: HSION
+      description: Internal High Speed clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: HSIRDY
+      description: Internal High Speed clock ready flag
+      bit_offset: 1
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSITRIM
+      description: Internal High Speed clock trimming
+      bit_offset: 3
+      bit_size: 5
+    - name: HSICAL
+      description: Internal High Speed clock Calibration
+      bit_offset: 8
+      bit_size: 8
+    - name: HSEON
+      description: External High Speed clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: HSERDY
+      description: External High Speed clock ready flag
+      bit_offset: 17
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSEBYP
+      description: External High Speed clock Bypass
+      bit_offset: 18
+      bit_size: 1
+      enum: HSEBYP
+    - name: CSSON
+      description: Clock Security System enable
+      bit_offset: 19
+      bit_size: 1
+    - name: PLLON
+      description: PLL enable
+      bit_offset: 24
+      bit_size: 1
+    - name: PLLRDY
+      description: PLL clock ready flag
+      bit_offset: 25
+      bit_size: 1
+      enum_read: HSIRDYR
+fieldset/CR2:
+  description: Clock control register 2
+  fields:
+    - name: HSI14ON
+      description: HSI14 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: HSI14RDY
+      description: HR14 clock ready flag
+      bit_offset: 1
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSI14DIS
+      description: HSI14 clock request from ADC disable
+      bit_offset: 2
+      bit_size: 1
+      enum: HSIDIS
+    - name: HSI14TRIM
+      description: HSI14 clock trimming
+      bit_offset: 3
+      bit_size: 5
+    - name: HSI14CAL
+      description: HSI14 clock calibration
+      bit_offset: 8
+      bit_size: 8
+    - name: HSI48ON
+      description: HSI48 clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: HSI48RDY
+      description: HSI48 clock ready flag
+      bit_offset: 17
+      bit_size: 1
+      enum_read: HSIRDYR
+    - name: HSI48CAL
+      description: HSI48 factory clock calibration
+      bit_offset: 24
+      bit_size: 8
+fieldset/CSR:
+  description: Control/status register (RCC_CSR)
+  fields:
+    - name: LSION
+      description: Internal low speed oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSIRDY
+      description: Internal low speed oscillator ready
+      bit_offset: 1
+      bit_size: 1
+      enum_read: LSIRDYR
+    - name: V18PWRRSTF
+      description: 1.8 V domain reset flag
+      bit_offset: 23
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: RMVF
+      description: Remove reset flag
+      bit_offset: 24
+      bit_size: 1
+      enum_write: RMVFW
+    - name: OBLRSTF
+      description: Option byte loader reset flag
+      bit_offset: 25
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: PINRSTF
+      description: PIN reset flag
+      bit_offset: 26
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: PORRSTF
+      description: POR/PDR reset flag
+      bit_offset: 27
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: SFTRSTF
+      description: Software reset flag
+      bit_offset: 28
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: IWDGRSTF
+      description: Independent watchdog reset flag
+      bit_offset: 29
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: WWDGRSTF
+      description: Window watchdog reset flag
+      bit_offset: 30
+      bit_size: 1
+      enum_read: OBLRSTFR
+    - name: LPWRRSTF
+      description: Low-power reset flag
+      bit_offset: 31
+      bit_size: 1
+      enum_read: OBLRSTFR
+enum/CSSCW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clear CSSF flag
+      value: 1
+enum/CSSFR:
+  bit_size: 1
+  variants:
+    - name: NotInterrupted
+      description: No clock security interrupt caused by HSE clock failure
+      value: 0
+    - name: Interrupted
+      description: Clock security interrupt caused by HSE clock failure
+      value: 1
+enum/HPRE:
+  bit_size: 4
+  variants:
+    - name: Div1
+      description: SYSCLK not divided
+      value: 0
+    - name: Div2
+      description: SYSCLK divided by 2
+      value: 8
+    - name: Div4
+      description: SYSCLK divided by 4
+      value: 9
+    - name: Div8
+      description: SYSCLK divided by 8
+      value: 10
+    - name: Div16
+      description: SYSCLK divided by 16
+      value: 11
+    - name: Div64
+      description: SYSCLK divided by 64
+      value: 12
+    - name: Div128
+      description: SYSCLK divided by 128
+      value: 13
+    - name: Div256
+      description: SYSCLK divided by 256
+      value: 14
+    - name: Div512
+      description: SYSCLK divided by 512
+      value: 15
+enum/HSEBYP:
+  bit_size: 1
+  variants:
+    - name: NotBypassed
+      description: HSE crystal oscillator not bypassed
+      value: 0
+    - name: Bypassed
+      description: HSE crystal oscillator bypassed with external clock
+      value: 1
+enum/HSIDIS:
+  bit_size: 1
+  variants:
+    - name: Allow
+      description: ADC can turn on the HSI14 oscillator
+      value: 0
+    - name: Disallow
+      description: ADC can not turn on the HSI14 oscillator
+      value: 1
+enum/HSIRDYR:
+  bit_size: 1
+  variants:
+    - name: NotReady
+      description: HSI14 oscillator not ready
+      value: 0
+    - name: Ready
+      description: HSI14 oscillator ready
+      value: 1
+enum/ICSW:
+  bit_size: 1
+  variants:
+    - name: HSI
+      description: HSI clock selected as I2C clock source
+      value: 0
+    - name: SYSCLK
+      description: SYSCLK clock selected as I2C clock source
+      value: 1
+enum/LSEBYP:
+  bit_size: 1
+  variants:
+    - name: NotBypassed
+      description: LSE crystal oscillator not bypassed
+      value: 0
+    - name: Bypassed
+      description: LSE crystal oscillator bypassed with external clock
+      value: 1
+enum/LSEDRV:
+  bit_size: 2
+  variants:
+    - name: Low
+      description: Low drive capacity
+      value: 0
+    - name: MediumHigh
+      description: Medium-high drive capacity
+      value: 1
+    - name: MediumLow
+      description: Medium-low drive capacity
+      value: 2
+    - name: High
+      description: High drive capacity
+      value: 3
+enum/LSERDYR:
+  bit_size: 1
+  variants:
+    - name: NotReady
+      description: LSE oscillator not ready
+      value: 0
+    - name: Ready
+      description: LSE oscillator ready
+      value: 1
+enum/LSIRDYCW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clear interrupt flag
+      value: 1
+enum/LSIRDYFR:
+  bit_size: 1
+  variants:
+    - name: NotInterrupted
+      description: No clock ready interrupt
+      value: 0
+    - name: Interrupted
+      description: Clock ready interrupt
+      value: 1
+enum/LSIRDYIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Interrupt enabled
+      value: 1
+enum/LSIRDYR:
+  bit_size: 1
+  variants:
+    - name: NotReady
+      description: LSI oscillator not ready
+      value: 0
+    - name: Ready
+      description: LSI oscillator ready
+      value: 1
+enum/MCO:
+  bit_size: 3
+  variants:
+    - name: NoMCO
+      description: "MCO output disabled, no clock on MCO"
+      value: 0
+    - name: HSI14
+      description: Internal RC 14 MHz (HSI14) oscillator clock selected
+      value: 1
+    - name: LSI
+      description: Internal low speed (LSI) oscillator clock selected
+      value: 2
+    - name: LSE
+      description: External low speed (LSE) oscillator clock selected
+      value: 3
+    - name: SYSCLK
+      description: System clock selected
+      value: 4
+    - name: HSI
+      description: Internal RC 8 MHz (HSI) oscillator clock selected
+      value: 5
+    - name: HSE
+      description: External 4-32 MHz (HSE) oscillator clock selected
+      value: 6
+    - name: PLL
+      description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"
+      value: 7
+    - name: HSI48
+      description: Internal RC 48 MHz (HSI48) oscillator clock selected
+      value: 8
+enum/MCOPRE:
+  bit_size: 3
+  variants:
+    - name: Div1
+      description: MCO is divided by 1
+      value: 0
+    - name: Div2
+      description: MCO is divided by 2
+      value: 1
+    - name: Div4
+      description: MCO is divided by 4
+      value: 2
+    - name: Div8
+      description: MCO is divided by 8
+      value: 3
+    - name: Div16
+      description: MCO is divided by 16
+      value: 4
+    - name: Div32
+      description: MCO is divided by 32
+      value: 5
+    - name: Div64
+      description: MCO is divided by 64
+      value: 6
+    - name: Div128
+      description: MCO is divided by 128
+      value: 7
+enum/OBLRSTFR:
+  bit_size: 1
+  variants:
+    - name: NoReset
+      description: No reset has occured
+      value: 0
+    - name: Reset
+      description: A reset has occured
+      value: 1
+enum/PLLMUL:
+  bit_size: 4
+  variants:
+    - name: Mul2
+      description: PLL input clock x2
+      value: 0
+    - name: Mul3
+      description: PLL input clock x3
+      value: 1
+    - name: Mul4
+      description: PLL input clock x4
+      value: 2
+    - name: Mul5
+      description: PLL input clock x5
+      value: 3
+    - name: Mul6
+      description: PLL input clock x6
+      value: 4
+    - name: Mul7
+      description: PLL input clock x7
+      value: 5
+    - name: Mul8
+      description: PLL input clock x8
+      value: 6
+    - name: Mul9
+      description: PLL input clock x9
+      value: 7
+    - name: Mul10
+      description: PLL input clock x10
+      value: 8
+    - name: Mul11
+      description: PLL input clock x11
+      value: 9
+    - name: Mul12
+      description: PLL input clock x12
+      value: 10
+    - name: Mul13
+      description: PLL input clock x13
+      value: 11
+    - name: Mul14
+      description: PLL input clock x14
+      value: 12
+    - name: Mul15
+      description: PLL input clock x15
+      value: 13
+    - name: Mul16
+      description: PLL input clock x16
+      value: 14
+    - name: Mul16x
+      description: PLL input clock x16
+      value: 15
+enum/PLLNODIV:
+  bit_size: 1
+  variants:
+    - name: Div2
+      description: PLL is divided by 2 for MCO
+      value: 0
+    - name: Div1
+      description: PLL is not divided for MCO
+      value: 1
+enum/PLLSRC:
+  bit_size: 1
+  variants:
+    - name: HSI_Div2
+      description: HSI divided by 2 selected as PLL input clock
+      value: 0
+    - name: HSE_Div_PREDIV
+      description: HSE divided by PREDIV selected as PLL input clock
+      value: 1
+enum/PLLXTPRE:
+  bit_size: 1
+  variants:
+    - name: Div1
+      description: HSE clock not divided
+      value: 0
+    - name: Div2
+      description: HSE clock divided by 2
+      value: 1
+enum/PPRE:
+  bit_size: 3
+  variants:
+    - name: Div1
+      description: HCLK not divided
+      value: 0
+    - name: Div2
+      description: HCLK divided by 2
+      value: 4
+    - name: Div4
+      description: HCLK divided by 4
+      value: 5
+    - name: Div8
+      description: HCLK divided by 8
+      value: 6
+    - name: Div16
+      description: HCLK divided by 16
+      value: 7
+enum/PREDIV:
+  bit_size: 4
+  variants:
+    - name: Div1
+      description: PREDIV input clock not divided
+      value: 0
+    - name: Div2
+      description: PREDIV input clock divided by 2
+      value: 1
+    - name: Div3
+      description: PREDIV input clock divided by 3
+      value: 2
+    - name: Div4
+      description: PREDIV input clock divided by 4
+      value: 3
+    - name: Div5
+      description: PREDIV input clock divided by 5
+      value: 4
+    - name: Div6
+      description: PREDIV input clock divided by 6
+      value: 5
+    - name: Div7
+      description: PREDIV input clock divided by 7
+      value: 6
+    - name: Div8
+      description: PREDIV input clock divided by 8
+      value: 7
+    - name: Div9
+      description: PREDIV input clock divided by 9
+      value: 8
+    - name: Div10
+      description: PREDIV input clock divided by 10
+      value: 9
+    - name: Div11
+      description: PREDIV input clock divided by 11
+      value: 10
+    - name: Div12
+      description: PREDIV input clock divided by 12
+      value: 11
+    - name: Div13
+      description: PREDIV input clock divided by 13
+      value: 12
+    - name: Div14
+      description: PREDIV input clock divided by 14
+      value: 13
+    - name: Div15
+      description: PREDIV input clock divided by 15
+      value: 14
+    - name: Div16
+      description: PREDIV input clock divided by 16
+      value: 15
+enum/RMVFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clears the reset flag
+      value: 1
+enum/RTCSEL:
+  bit_size: 2
+  variants:
+    - name: NoClock
+      description: No clock
+      value: 0
+    - name: LSE
+      description: LSE oscillator clock used as RTC clock
+      value: 1
+    - name: LSI
+      description: LSI oscillator clock used as RTC clock
+      value: 2
+    - name: HSE
+      description: HSE oscillator clock divided by a prescaler used as RTC clock
+      value: 3
+enum/SW:
+  bit_size: 2
+  variants:
+    - name: HSI
+      description: HSI selected as system clock
+      value: 0
+    - name: HSE
+      description: HSE selected as system clock
+      value: 1
+    - name: PLL
+      description: PLL selected as system clock
+      value: 2
+    - name: HSI48
+      description: HSI48 selected as system clock (when available)
+      value: 3
+enum/SWSR:
+  bit_size: 2
+  variants:
+    - name: HSI
+      description: HSI oscillator used as system clock
+      value: 0
+    - name: HSE
+      description: HSE oscillator used as system clock
+      value: 1
+    - name: PLL
+      description: PLL used as system clock
+      value: 2
+    - name: HSI48
+      description: HSI48 used as system clock (when avaiable)
+      value: 3
+enum/USARTSW:
+  bit_size: 2
+  variants:
+    - name: PCLK
+      description: PCLK selected as USART clock source
+      value: 0
+    - name: SYSCLK
+      description: SYSCLK selected as USART clock source
+      value: 1
+    - name: LSE
+      description: LSE selected as USART clock source
+      value: 2
+    - name: HSI
+      description: HSI selected as USART clock source
+      value: 3
+enum/USBSW:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: USB clock disabled
+      value: 0
+    - name: PLLCLK
+      description: PLL clock selected as USB clock source
+      value: 1
diff --git a/parse.py b/parse.py
index 3e0d585..4003b19 100644
--- a/parse.py
+++ b/parse.py
@@ -321,6 +321,8 @@ perimap = [
     ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
     ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
     ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'),
+    ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
+    ('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
     ('.*:STM32H7AB_rcc_v1_0', ''),  # rcc_h7ab/RCC
     ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
     ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),