From ad6f5a5434337364251402d71b87cc2c92a4a67b Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Sun, 1 May 2022 14:25:38 -0500 Subject: [PATCH] Clean up rcc_f1cl.yaml --- data/registers/rcc_f1cl.yaml | 183 +---------------------------------- 1 file changed, 3 insertions(+), 180 deletions(-) diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index ff4bbf3..bcdb5e9 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -73,14 +73,6 @@ fieldset/AHBENR: description: CRC clock enable bit_offset: 6 bit_size: 1 - - name: FSMCEN - description: FSMC clock enable - bit_offset: 8 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 10 - bit_size: 1 - name: USB_OTG_FSEN description: USB OTG FS clock enable bit_offset: 12 @@ -135,18 +127,6 @@ fieldset/APB1ENR: description: Timer 7 clock enable bit_offset: 5 bit_size: 1 - - name: TIM12EN - description: Timer 12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: Timer 13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 @@ -183,18 +163,10 @@ fieldset/APB1ENR: description: I2C 2 clock enable bit_offset: 22 bit_size: 1 - - name: USBEN - description: USB clock enable - bit_offset: 23 - bit_size: 1 - name: CAN1EN description: CAN1 clock enable bit_offset: 25 bit_size: 1 - - name: CANEN - description: CAN clock enable - bit_offset: 25 - bit_size: 1 - name: CAN2EN description: CAN2 clock enable bit_offset: 26 @@ -211,10 +183,6 @@ fieldset/APB1ENR: description: DAC interface clock enable bit_offset: 29 bit_size: 1 - - name: CECEN - description: CEC clock enable - bit_offset: 30 - bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: @@ -242,18 +210,6 @@ fieldset/APB1RSTR: description: Timer 7 reset bit_offset: 5 bit_size: 1 - - name: TIM12RST - description: Timer 12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: Timer 13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - name: WWDGRST description: Window watchdog reset bit_offset: 11 @@ -290,18 +246,10 @@ fieldset/APB1RSTR: description: I2C2 reset bit_offset: 22 bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - name: CAN1RST description: CAN1 reset bit_offset: 25 bit_size: 1 - - name: CANRST - description: CAN reset - bit_offset: 25 - bit_size: 1 - name: CAN2RST description: CAN2 reset bit_offset: 26 @@ -318,10 +266,6 @@ fieldset/APB1RSTR: description: DAC interface reset bit_offset: 29 bit_size: 1 - - name: CECRST - description: CEC reset - bit_offset: 30 - bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: @@ -349,14 +293,6 @@ fieldset/APB2ENR: description: I/O port E clock enable bit_offset: 6 bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOGEN - description: I/O port G clock enable - bit_offset: 8 - bit_size: 1 - name: ADC1EN description: ADC 1 interface clock enable bit_offset: 9 @@ -373,42 +309,10 @@ fieldset/APB2ENR: description: SPI 1 clock enable bit_offset: 12 bit_size: 1 - - name: TIM8EN - description: TIM8 Timer clock enable - bit_offset: 13 - bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 14 bit_size: 1 - - name: ADC3EN - description: ADC3 interface clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM15EN - description: TIM15 Timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 Timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 Timer clock enable - bit_offset: 18 - bit_size: 1 - - name: TIM9EN - description: TIM9 Timer clock enable - bit_offset: 19 - bit_size: 1 - - name: TIM10EN - description: TIM10 Timer clock enable - bit_offset: 20 - bit_size: 1 - - name: TIM11EN - description: TIM11 Timer clock enable - bit_offset: 21 - bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: @@ -436,14 +340,6 @@ fieldset/APB2RSTR: description: IO port E reset bit_offset: 6 bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 7 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 8 - bit_size: 1 - name: ADC1RST description: ADC 1 interface reset bit_offset: 9 @@ -460,42 +356,10 @@ fieldset/APB2RSTR: description: SPI 1 reset bit_offset: 12 bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - - name: ADC3RST - description: ADC 3 interface reset - bit_offset: 15 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: TIM9RST - description: TIM9 timer reset - bit_offset: 19 - bit_size: 1 - - name: TIM10RST - description: TIM10 timer reset - bit_offset: 20 - bit_size: 1 - - name: TIM11RST - description: TIM11 timer reset - bit_offset: 21 - bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: @@ -525,7 +389,7 @@ fieldset/BDCR: bit_offset: 16 bit_size: 1 fieldset/CFGR: - description: Clock configuration register (RCC_3FGR) + description: Clock configuration register (RCC_CFGR) fields: - name: SW description: System clock Switch @@ -572,11 +436,6 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: OTGFSPRE - description: USB OTG FS prescaler - bit_offset: 22 - bit_size: 1 - enum: OTGFSPRE - name: USBPRE description: USB prescaler bit_offset: 22 @@ -902,15 +761,6 @@ enum/MCO: - name: PLL3 description: PLL3 clock selected value: 11 -enum/OTGFSPRE: - bit_size: 1 - variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 enum/PLL2MUL: bit_size: 4 variants: @@ -944,12 +794,6 @@ enum/PLL2MUL: enum/PLLMUL: bit_size: 4 variants: - - name: Mul2 - description: PLL input clock x2 - value: 0 - - name: Mul3 - description: PLL input clock x3 - value: 1 - name: Mul4 description: PLL input clock x4 value: 2 @@ -968,30 +812,9 @@ enum/PLLMUL: - name: Mul9 description: PLL input clock x9 value: 7 - - name: Mul10 - description: PLL input clock x10 - value: 8 - - name: Mul11 - description: PLL input clock x11 - value: 9 - - name: Mul12 - description: PLL input clock x12 - value: 10 - - name: Mul13 - description: PLL input clock x13 - value: 11 - - name: Mul14 - description: PLL input clock x14 - value: 12 - - name: Mul15 - description: PLL input clock x15 + - name: Mul6_5 + description: PLL input clock x6.5 value: 13 - - name: Mul16 - description: PLL input clock x16 - value: 14 - - name: Mul16x - description: PLL input clock x16 - value: 15 enum/PLLSRC: bit_size: 1 variants: