Merge pull request #329 from eZioPan/syscfg-cleanup

syscfg-cleanup
2024-01-01 20:56:56 +00:00 · 2024-01-01 20:56:56 +00:00 · ad5c88c0b5
commit ad5c88c0b5
parent 746f90d563 45efe8a301
2 changed files with 26 additions and 180 deletions
--- a/data/registers/syscfg_f3.yaml
+++ b/data/registers/syscfg_f3.yaml
@ -147,40 +147,22 @@ fieldset/CFGR1:
    bit_size: 1
    enum: I2C3_FMP
  - name: VBAT_MON
-    description: VBAT monitoring enable
+    description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
    bit_offset: 24
    bit_size: 1
-    enum: VBAT_MON
-  - name: FPU_IE0
-    description: Invalid operation interrupt enable
+  - name: FPU_IE
+    description: |-
+      Idx 0: Invalid operation interrupt enable;
+      Idx 1: Devide-by-zero interrupt enable;
+      Idx 2: Underflow interrupt enable;
+      Idx 3: Overflow interrupt enable;
+      Idx 4: Input denormal interrupt enable;
+      Idx 5: Inexact interrupt enable
    bit_offset: 26
    bit_size: 1
-    enum: FPU_IE0
-  - name: FPU_IE1
-    description: Devide-by-zero interrupt enable
-    bit_offset: 27
-    bit_size: 1
-    enum: FPU_IE1
-  - name: FPU_IE2
-    description: Underflow interrupt enable
-    bit_offset: 28
-    bit_size: 1
-    enum: FPU_IE2
-  - name: FPU_IE3
-    description: Overflow interrupt enable
-    bit_offset: 29
-    bit_size: 1
-    enum: FPU_IE3
-  - name: FPU_IE4
-    description: Input denormal interrupt enable
-    bit_offset: 30
-    bit_size: 1
-    enum: FPU_IE4
-  - name: FPU_IE5
-    description: Inexact interrupt enable
-    bit_offset: 31
-    bit_size: 1
-    enum: FPU_IE5
+    array:
+      len: 6
+      stride: 1
 fieldset/CFGR2:
  description: configuration register 2
  fields:
@ -332,86 +314,13 @@ fieldset/EXTICR:
 fieldset/RCR:
  description: CCM SRAM protection register
  fields:
-  - name: PAGE0_WP
-    description: CCM SRAM page write protection bit
+  - name: PAGE_WP
+    description: CCM SRAM page x write protection enabled
    bit_offset: 0
    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE1_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 1
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE2_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 2
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE3_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 3
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE4_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 4
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE5_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 5
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE6_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 6
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE7_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 7
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE8_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 8
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE9_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 9
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE10_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 10
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE11_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 11
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE12_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 12
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE13_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 13
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE14_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 14
-    bit_size: 1
-    enum: PAGE0_WP
-  - name: PAGE15_WP
-    description: CCM SRAM page write protection bit
-    bit_offset: 15
-    bit_size: 1
-    enum: PAGE0_WP
+    array:
+      len: 16
+      stride: 1
 enum/ADC12_EXT13_RMP:
  bit_size: 1
  variants:
@ -616,60 +525,6 @@ enum/ENCODER_MODE:
  - name: MapTim3Tim15
    description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
    value: 2
-enum/FPU_IE0:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Invalid operation interrupt disable
-    value: 0
-  - name: Enabled
-    description: Invalid operation interrupt enable
-    value: 1
-enum/FPU_IE1:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Devide-by-zero interrupt disable
-    value: 0
-  - name: Enabled
-    description: Devide-by-zero interrupt enable
-    value: 1
-enum/FPU_IE2:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Underflow interrupt disable
-    value: 0
-  - name: Enabled
-    description: Underflow interrupt enable
-    value: 1
-enum/FPU_IE3:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Overflow interrupt disable
-    value: 0
-  - name: Enabled
-    description: Overflow interrupt enable
-    value: 1
-enum/FPU_IE4:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Input denormal interrupt disable
-    value: 0
-  - name: Enabled
-    description: Input denormal interrupt enable
-    value: 1
-enum/FPU_IE5:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Inexact interrupt disable
-    value: 0
-  - name: Enabled
-    description: Inexact interrupt enable
-    value: 1
 enum/I2C1_FMP:
  bit_size: 1
  variants:
@ -781,15 +636,6 @@ enum/MEM_MODE:
  - name: SRAM
    description: Embedded SRAM mapped at 0x0000_0000
    value: 3
-enum/PAGE0_WP:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Write protection of pagex is disabled
-    value: 0
-  - name: Enabled
-    description: Write protection of pagex is enabled
-    value: 1
 enum/PVD_LOCK:
  bit_size: 1
  variants:
@ -922,12 +768,3 @@ enum/USB_IT_RMP:
  - name: Remapped
    description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively
    value: 1
-enum/VBAT_MON:
-  bit_size: 1
-  variants:
-  - name: Disable
-    description: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input
-    value: 0
-  - name: Enable
-    description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
-    value: 1
--- a/transforms/SYSCFG_F3.yaml
+++ b/transforms/SYSCFG_F3.yaml
@ -0,0 +1,9 @@
+transforms:
+  - !MakeFieldArray
+    fieldsets: RCR
+    from: PAGE\d+_WP
+    to: PAGE_WP
+  - !MakeFieldArray
+    fieldsets: CFGR1
+    from: FPU_IE\d
+    to: FPU_IE