diff --git a/data/registers/bdma_v1.yaml b/data/registers/bdma_v1.yaml index be9ae13..224d1ec 100644 --- a/data/registers/bdma_v1.yaml +++ b/data/registers/bdma_v1.yaml @@ -13,11 +13,11 @@ block/DMA: byte_offset: 4 reset_value: 0 access: Write - fieldset: IFCR + fieldset: ISR - name: CH description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" array: - len: 7 + len: 8 stride: 20 byte_offset: 8 block: CH @@ -101,37 +101,6 @@ fieldset/CR: bit_offset: 14 bit_size: 1 enum: MEMMEM -fieldset/IFCR: - description: DMA interrupt flag clear register (DMA_IFCR) - fields: - - name: CGIF - description: Channel 1 Global interrupt clear - bit_offset: 0 - bit_size: 1 - array: - len: 7 - stride: 4 - - name: CTCIF - description: Channel 1 Transfer Complete clear - bit_offset: 1 - bit_size: 1 - array: - len: 7 - stride: 4 - - name: CHTIF - description: Channel 1 Half Transfer clear - bit_offset: 2 - bit_size: 1 - array: - len: 7 - stride: 4 - - name: CTEIF - description: Channel 1 Transfer Error clear - bit_offset: 3 - bit_size: 1 - array: - len: 7 - stride: 4 fieldset/ISR: description: DMA interrupt status register (DMA_ISR) fields: @@ -140,28 +109,28 @@ fieldset/ISR: bit_offset: 0 bit_size: 1 array: - len: 7 + len: 8 stride: 4 - name: TCIF description: Channel 1 Transfer Complete flag bit_offset: 1 bit_size: 1 array: - len: 7 + len: 8 stride: 4 - name: HTIF description: Channel 1 Half Transfer Complete flag bit_offset: 2 bit_size: 1 array: - len: 7 + len: 8 stride: 4 - name: TEIF description: Channel 1 Transfer Error flag bit_offset: 3 bit_size: 1 array: - len: 7 + len: 8 stride: 4 fieldset/NDTR: description: DMA channel 1 number of data register diff --git a/data/registers/bdma_v2.yaml b/data/registers/bdma_v2.yaml new file mode 100644 index 0000000..83ed231 --- /dev/null +++ b/data/registers/bdma_v2.yaml @@ -0,0 +1,218 @@ +--- +block/DMA: + description: DMA controller + items: + - name: ISR + description: DMA interrupt status register (DMA_ISR) + byte_offset: 0 + reset_value: 0 + access: Read + fieldset: ISR + - name: IFCR + description: DMA interrupt flag clear register (DMA_IFCR) + byte_offset: 4 + reset_value: 0 + access: Write + fieldset: ISR + - name: CH + description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" + array: + len: 8 + stride: 20 + byte_offset: 8 + block: CH + - name: CSELR + description: channel selection register + byte_offset: 168 + fieldset: CSELR +block/CH: + description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" + items: + - name: CR + description: DMA channel configuration register (DMA_CCR) + byte_offset: 0 + reset_value: 0 + fieldset: CR + - name: NDTR + description: DMA channel 1 number of data register + byte_offset: 4 + reset_value: 0 + fieldset: NDTR + - name: PAR + description: DMA channel 1 peripheral address register + byte_offset: 8 + reset_value: 0 + - name: MAR + description: DMA channel 1 memory address register + byte_offset: 12 + reset_value: 0 +fieldset/CR: + description: DMA channel configuration register (DMA_CCR) + fields: + - name: EN + description: Channel enable + bit_offset: 0 + bit_size: 1 + - name: TCIE + description: Transfer complete interrupt enable + bit_offset: 1 + bit_size: 1 + - name: HTIE + description: Half Transfer interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TEIE + description: Transfer error interrupt enable + bit_offset: 3 + bit_size: 1 + - name: DIR + description: Data transfer direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CIRC + description: Circular mode + bit_offset: 5 + bit_size: 1 + enum: CIRC + - name: PINC + description: Peripheral increment mode + bit_offset: 6 + bit_size: 1 + enum: INC + - name: MINC + description: Memory increment mode + bit_offset: 7 + bit_size: 1 + enum: INC + - name: PSIZE + description: Peripheral size + bit_offset: 8 + bit_size: 2 + enum: SIZE + - name: MSIZE + description: Memory size + bit_offset: 10 + bit_size: 2 + enum: SIZE + - name: PL + description: Channel Priority level + bit_offset: 12 + bit_size: 2 + enum: PL + - name: MEM2MEM + description: Memory to memory mode + bit_offset: 14 + bit_size: 1 + enum: MEMMEM +fieldset/CSELR: + description: channel selection register + fields: + - name: CS + description: DMA channel selection + bit_offset: 0 + bit_size: 4 + array: + len: 8 + stride: 4 +fieldset/ISR: + description: DMA interrupt status register (DMA_ISR) + fields: + - name: GIF + description: Channel 1 Global interrupt flag + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 4 + - name: TCIF + description: Channel 1 Transfer Complete flag + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 4 + - name: HTIF + description: Channel 1 Half Transfer Complete flag + bit_offset: 2 + bit_size: 1 + array: + len: 8 + stride: 4 + - name: TEIF + description: Channel 1 Transfer Error flag + bit_offset: 3 + bit_size: 1 + array: + len: 8 + stride: 4 +fieldset/NDTR: + description: DMA channel 1 number of data register + fields: + - name: NDT + description: Number of data to transfer + bit_offset: 0 + bit_size: 16 +enum/CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled + value: 0 + - name: Enabled + description: Circular buffer enabled + value: 1 +enum/DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral + value: 0 + - name: FromMemory + description: Read from memory + value: 1 +enum/MEMMEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled + value: 0 + - name: Enabled + description: Memory to memory mode enabled + value: 1 +enum/INC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled + value: 0 + - name: Enabled + description: Increment mode enabled + value: 1 +enum/PL: + bit_size: 2 + variants: + - name: Low + description: Low priority + value: 0 + - name: Medium + description: Medium priority + value: 1 + - name: High + description: High priority + value: 2 + - name: VeryHigh + description: Very high priority + value: 3 +enum/SIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size + value: 0 + - name: Bits16 + description: 16-bit size + value: 1 + - name: Bits32 + description: 32-bit size + value: 2 diff --git a/data/registers/dma_v1.yaml b/data/registers/dma_v1.yaml index 44d6963..822fabf 100644 --- a/data/registers/dma_v1.yaml +++ b/data/registers/dma_v1.yaml @@ -145,10 +145,6 @@ fieldset/CR: bit_offset: 23 bit_size: 2 enum: BURST - - name: CHSEL - description: Channel selection - bit_offset: 25 - bit_size: 4 fieldset/FCR: description: stream x FIFO control register fields: diff --git a/data/registers/dma_v2.yaml b/data/registers/dma_v2.yaml new file mode 100644 index 0000000..44d6963 --- /dev/null +++ b/data/registers/dma_v2.yaml @@ -0,0 +1,386 @@ +--- +block/DMA: + description: DMA controller + items: + - name: ISR + description: low interrupt status register + array: + len: 2 + stride: 4 + byte_offset: 0 + reset_value: 0 + access: Read + fieldset: IXR + - name: IFCR + description: low interrupt flag clear register + array: + len: 2 + stride: 4 + byte_offset: 8 + reset_value: 0 + access: Write + fieldset: IXR + - name: ST + description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" + array: + len: 8 + stride: 24 + byte_offset: 16 + block: ST +block/ST: + description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" + items: + - name: CR + description: stream x configuration register + byte_offset: 0 + reset_value: 0 + fieldset: CR + - name: NDTR + description: stream x number of data register + byte_offset: 4 + reset_value: 0 + fieldset: NDTR + - name: PAR + description: stream x peripheral address register + byte_offset: 8 + reset_value: 0 + - name: M0AR + description: stream x memory 0 address register + byte_offset: 12 + reset_value: 0 + - name: M1AR + description: stream x memory 1 address register + byte_offset: 16 + reset_value: 0 + - name: FCR + description: stream x FIFO control register + byte_offset: 20 + reset_value: 33 + fieldset: FCR +fieldset/CR: + description: stream x configuration register + fields: + - name: EN + description: Stream enable / flag stream ready when read low + bit_offset: 0 + bit_size: 1 + - name: DMEIE + description: Direct mode error interrupt enable + bit_offset: 1 + bit_size: 1 + - name: TEIE + description: Transfer error interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HTIE + description: Half transfer interrupt enable + bit_offset: 3 + bit_size: 1 + - name: TCIE + description: Transfer complete interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PFCTRL + description: Peripheral flow controller + bit_offset: 5 + bit_size: 1 + enum: PFCTRL + - name: DIR + description: Data transfer direction + bit_offset: 6 + bit_size: 2 + enum: DIR + - name: CIRC + description: Circular mode + bit_offset: 8 + bit_size: 1 + enum: CIRC + - name: PINC + description: Peripheral increment mode + bit_offset: 9 + bit_size: 1 + enum: INC + - name: MINC + description: Memory increment mode + bit_offset: 10 + bit_size: 1 + enum: INC + - name: PSIZE + description: Peripheral data size + bit_offset: 11 + bit_size: 2 + enum: SIZE + - name: MSIZE + description: Memory data size + bit_offset: 13 + bit_size: 2 + enum: SIZE + - name: PINCOS + description: Peripheral increment offset size + bit_offset: 15 + bit_size: 1 + enum: PINCOS + - name: PL + description: Priority level + bit_offset: 16 + bit_size: 2 + enum: PL + - name: DBM + description: Double buffer mode + bit_offset: 18 + bit_size: 1 + enum: DBM + - name: CT + description: Current target (only in double buffer mode) + bit_offset: 19 + bit_size: 1 + enum: CT + - name: PBURST + description: Peripheral burst transfer configuration + bit_offset: 21 + bit_size: 2 + enum: BURST + - name: MBURST + description: Memory burst transfer configuration + bit_offset: 23 + bit_size: 2 + enum: BURST + - name: CHSEL + description: Channel selection + bit_offset: 25 + bit_size: 4 +fieldset/FCR: + description: stream x FIFO control register + fields: + - name: FTH + description: FIFO threshold selection + bit_offset: 0 + bit_size: 2 + enum: FTH + - name: DMDIS + description: Direct mode disable + bit_offset: 2 + bit_size: 1 + enum: DMDIS + - name: FS + description: FIFO status + bit_offset: 3 + bit_size: 3 + enum: FS + - name: FEIE + description: FIFO error interrupt enable + bit_offset: 7 + bit_size: 1 +fieldset/IXR: + description: interrupt register + fields: + - name: FEIF + description: Stream x FIFO error interrupt flag (x=3..0) + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 16 + - 22 + - name: DMEIF + description: Stream x direct mode error interrupt flag (x=3..0) + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 16 + - 22 + - name: TEIF + description: Stream x transfer error interrupt flag (x=3..0) + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 16 + - 22 + - name: HTIF + description: Stream x half transfer interrupt flag (x=3..0) + bit_offset: 4 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 16 + - 22 + - name: TCIF + description: Stream x transfer complete interrupt flag (x = 3..0) + bit_offset: 5 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 16 + - 22 +fieldset/NDTR: + description: stream x number of data register + fields: + - name: NDT + description: Number of data items to transfer + bit_offset: 0 + bit_size: 16 +enum/CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular mode disabled + value: 0 + - name: Enabled + description: Circular mode enabled + value: 1 +enum/CT: + bit_size: 1 + variants: + - name: Memory0 + description: The current target memory is Memory 0 + value: 0 + - name: Memory1 + description: The current target memory is Memory 1 + value: 1 +enum/DBM: + bit_size: 1 + variants: + - name: Disabled + description: No buffer switching at the end of transfer + value: 0 + - name: Enabled + description: Memory target switched at the end of the DMA transfer + value: 1 +enum/DIR: + bit_size: 2 + variants: + - name: PeripheralToMemory + description: Peripheral-to-memory + value: 0 + - name: MemoryToPeripheral + description: Memory-to-peripheral + value: 1 + - name: MemoryToMemory + description: Memory-to-memory + value: 2 +enum/DMDIS: + bit_size: 1 + variants: + - name: Enabled + description: Direct mode is enabled + value: 0 + - name: Disabled + description: Direct mode is disabled + value: 1 +enum/FS: + bit_size: 3 + variants: + - name: Quarter1 + description: 0 < fifo_level < 1/4 + value: 0 + - name: Quarter2 + description: 1/4 <= fifo_level < 1/2 + value: 1 + - name: Quarter3 + description: 1/2 <= fifo_level < 3/4 + value: 2 + - name: Quarter4 + description: 3/4 <= fifo_level < full + value: 3 + - name: Empty + description: FIFO is empty + value: 4 + - name: Full + description: FIFO is full + value: 5 +enum/FTH: + bit_size: 2 + variants: + - name: Quarter + description: 1/4 full FIFO + value: 0 + - name: Half + description: 1/2 full FIFO + value: 1 + - name: ThreeQuarters + description: 3/4 full FIFO + value: 2 + - name: Full + description: Full FIFO + value: 3 +enum/BURST: + bit_size: 2 + variants: + - name: Single + description: Single transfer + value: 0 + - name: INCR4 + description: Incremental burst of 4 beats + value: 1 + - name: INCR8 + description: Incremental burst of 8 beats + value: 2 + - name: INCR16 + description: Incremental burst of 16 beats + value: 3 +enum/INC: + bit_size: 1 + variants: + - name: Fixed + description: Address pointer is fixed + value: 0 + - name: Incremented + description: Address pointer is incremented after each data transfer + value: 1 +enum/SIZE: + bit_size: 2 + variants: + - name: Bits8 + description: Byte (8-bit) + value: 0 + - name: Bits16 + description: Half-word (16-bit) + value: 1 + - name: Bits32 + description: Word (32-bit) + value: 2 +enum/PFCTRL: + bit_size: 1 + variants: + - name: DMA + description: The DMA is the flow controller + value: 0 + - name: Peripheral + description: The peripheral is the flow controller + value: 1 +enum/PINCOS: + bit_size: 1 + variants: + - name: PSIZE + description: The offset size for the peripheral address calculation is linked to the PSIZE + value: 0 + - name: Fixed4 + description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) + value: 1 +enum/PL: + bit_size: 2 + variants: + - name: Low + description: Low + value: 0 + - name: Medium + description: Medium + value: 1 + - name: High + description: High + value: 2 + - name: VeryHigh + description: Very high + value: 3 diff --git a/parse.py b/parse.py index 3e7a573..eaf5aa9 100644 --- a/parse.py +++ b/parse.py @@ -351,6 +351,13 @@ perimap = [ ('.*:IPCC:v1_0', 'ipcc_v1/IPCC'), ('.*:DMAMUX:v1', 'dmamux_v1/DMAMUX'), + + ('.*:BDMA:DMA', 'bdma_v1/DMA'), + ('STM32L4[PQRS].*:.*:DMA', 'bdma_v1/DMA'), # L4+ + ('STM32L[04].*:.*:DMA', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above) + ('STM32F[247].*:.*:DMA', 'dma_v2/DMA'), + ('STM32H7.*:.*:DMA', 'dma_v1/DMA'), + ('.*:DMA', 'bdma_v1/DMA'), ] rng_clock_map = [ @@ -365,7 +372,7 @@ rng_clock_map = [ def match_peri(peri): for r, block in perimap: - if re.match(r, peri): + if re.match('^'+r+'$', peri): if block == '': return None return block @@ -650,14 +657,12 @@ def parse_chips(): # Handle DMA specially. for dma in ('DMA1', 'DMA2', 'BDMA'): if addr := defines.get(dma + '_BASE'): - block = 'bdma_v1/DMA' - if dma != 'BDMA' and chip['family'] in ('STM32F4', 'STM32F7', 'STM32H7'): - block = 'dma_v1/DMA' - p = OrderedDict({ 'address': addr, - 'block': block, }) + if block := match_peri(chip_name+':'+dma+':DMA'): + p['block'] = block + peris[dma] = p # DMAMUX is not in the cubedb XMLs