diff --git a/data/registers/flash_f0.yaml b/data/registers/flash_f0.yaml new file mode 100644 index 0000000..36a4d88 --- /dev/null +++ b/data/registers/flash_f0.yaml @@ -0,0 +1,463 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: Flash access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 4 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Flash option key register + byte_offset: 8 + access: Write + fieldset: OPTKEYR + - name: SR + description: Flash status register + byte_offset: 12 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 16 + fieldset: CR + - name: AR + description: Flash address register + byte_offset: 20 + access: Write + fieldset: AR + - name: OBR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OBR + - name: WRPR + description: Write protection register + byte_offset: 32 + access: Read + fieldset: WRPR +fieldset/ACR: + description: Flash access control register + fields: + - name: LATENCY + description: LATENCY + bit_offset: 0 + bit_size: 3 + enum: LATENCY + - name: PRFTBE + description: PRFTBE + bit_offset: 4 + bit_size: 1 + enum: PRFTBE + - name: PRFTBS + description: PRFTBS + bit_offset: 5 + bit_size: 1 + enum_read: PRFTBSR +fieldset/AR: + description: Flash address register + fields: + - name: FAR + description: Flash address + bit_offset: 0 + bit_size: 32 +fieldset/CR: + description: Flash control register + fields: + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + enum: PG + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + enum: PER + - name: MER + description: Mass erase + bit_offset: 2 + bit_size: 1 + enum: MER + - name: OPTPG + description: Option byte programming + bit_offset: 4 + bit_size: 1 + enum: OPTPG + - name: OPTER + description: Option byte erase + bit_offset: 5 + bit_size: 1 + enum: OPTER + - name: STRT + description: Start + bit_offset: 6 + bit_size: 1 + enum: STRT + - name: LOCK + description: Lock + bit_offset: 7 + bit_size: 1 + enum: LOCK + - name: OPTWRE + description: Option bytes write enable + bit_offset: 9 + bit_size: 1 + enum: OPTWRE + - name: ERRIE + description: Error interrupt enable + bit_offset: 10 + bit_size: 1 + enum: ERRIE + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 12 + bit_size: 1 + enum: EOPIE + - name: FORCE_OPTLOAD + description: Force option byte loading + bit_offset: 13 + bit_size: 1 + enum: FORCE_OPTLOAD +fieldset/KEYR: + description: Flash key register + fields: + - name: FKEYR + description: Flash Key + bit_offset: 0 + bit_size: 32 +fieldset/OBR: + description: Option byte register + fields: + - name: OPTERR + description: Option byte error + bit_offset: 0 + bit_size: 1 + enum: OPTERR + - name: RDPRT + description: Read protection level status + bit_offset: 1 + bit_size: 2 + enum: RDPRT + - name: WDG_SW + description: WDG_SW + bit_offset: 8 + bit_size: 1 + enum: WDG_SW + - name: nRST_STOP + description: nRST_STOP + bit_offset: 9 + bit_size: 1 + enum: nRST_STOP + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 10 + bit_size: 1 + enum: nRST_STDBY + - name: nBOOT0 + description: nBOOT0 + bit_offset: 11 + bit_size: 1 + enum: nBOOT0 + - name: nBOOT1 + description: BOOT1 + bit_offset: 12 + bit_size: 1 + enum: nBOOT1 + - name: VDDA_MONITOR + description: VDDA_MONITOR + bit_offset: 13 + bit_size: 1 + enum: VDDA_MONITOR + - name: RAM_PARITY_CHECK + description: RAM_PARITY_CHECK + bit_offset: 14 + bit_size: 1 + enum: RAM_PARITY_CHECK + - name: BOOT_SEL + description: BOOT_SEL + bit_offset: 15 + bit_size: 1 + enum: BOOT_SEL + - name: Data0 + description: Data0 + bit_offset: 16 + bit_size: 8 + - name: Data1 + description: Data1 + bit_offset: 24 + bit_size: 8 +fieldset/OPTKEYR: + description: Flash option key register + fields: + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: Flash status register + fields: + - name: BSY + description: Busy + bit_offset: 0 + bit_size: 1 + enum_read: BSYR + - name: PGERR + description: Programming error + bit_offset: 2 + bit_size: 1 + enum: PGERR + - name: WRPRT + description: Write protection error + bit_offset: 4 + bit_size: 1 + enum: WRPRT + - name: EOP + description: End of operation + bit_offset: 5 + bit_size: 1 + enum: EOP +fieldset/WRPR: + description: Write protection register + fields: + - name: WRP + description: Write protect + bit_offset: 0 + bit_size: 32 +enum/BOOT_SEL: + bit_size: 1 + variants: + - name: nBOOT0 + description: BOOT0 signal is defined by nBOOT0 option bit + value: 0 + - name: BOOT0 + description: BOOT0 signal is defined by BOOT0 pin value (legacy mode) + value: 1 +enum/BSYR: + bit_size: 1 + variants: + - name: Inactive + description: No write/erase operation is in progress + value: 0 + - name: Active + description: A write/erase operation is in progress + value: 1 +enum/EOP: + bit_size: 1 + variants: + - name: NoEvent + description: No EOP operation occurred + value: 0 + - name: Event + description: An EOP event occurred + value: 1 +enum/EOPIE: + bit_size: 1 + variants: + - name: Disabled + description: End of operation interrupt disabled + value: 0 + - name: Enabled + description: End of operation interrupt enabled + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Error interrupt generation disabled + value: 0 + - name: Enabled + description: Error interrupt generation enabled + value: 1 +enum/FORCE_OPTLOAD: + bit_size: 1 + variants: + - name: Inactive + description: Force option byte loading inactive + value: 0 + - name: Active + description: Force option byte loading active + value: 1 +enum/LATENCY: + bit_size: 3 + variants: + - name: WS0 + description: 0 wait states + value: 0 + - name: WS1 + description: 1 wait state + value: 1 +enum/LOCK: + bit_size: 1 + variants: + - name: Unlocked + description: FLASH_CR register is unlocked + value: 0 + - name: Locked + description: FLASH_CR register is locked + value: 1 +enum/MER: + bit_size: 1 + variants: + - name: MassErase + description: Erase activated for all user sectors + value: 1 +enum/OPTER: + bit_size: 1 + variants: + - name: OptionByteErase + description: Erase option byte activated + value: 1 +enum/OPTERR: + bit_size: 1 + variants: + - name: OptionByteError + description: The loaded option byte and its complement do not match + value: 1 +enum/OPTPG: + bit_size: 1 + variants: + - name: OptionByteProgramming + description: Program option byte activated + value: 1 +enum/OPTWRE: + bit_size: 1 + variants: + - name: Disabled + description: Option byte write disabled + value: 0 + - name: Enabled + description: Option byte write enabled + value: 1 +enum/PER: + bit_size: 1 + variants: + - name: PageErase + description: Erase activated for selected page + value: 1 +enum/PG: + bit_size: 1 + variants: + - name: Program + description: Flash programming activated + value: 1 +enum/PGERR: + bit_size: 1 + variants: + - name: NoError + description: No programming error occurred + value: 0 + - name: Error + description: A programming error occurred + value: 1 +enum/PRFTBE: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch is disabled + value: 0 + - name: Enabled + description: Prefetch is enabled + value: 1 +enum/PRFTBSR: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch buffer is disabled + value: 0 + - name: Enabled + description: Prefetch buffer is enabled + value: 1 +enum/RAM_PARITY_CHECK: + bit_size: 1 + variants: + - name: Enabled + description: RAM parity check enabled + value: 0 + - name: Disabled + description: RAM parity check disabled + value: 1 +enum/RDPRT: + bit_size: 2 + variants: + - name: Level0 + description: Level 0 + value: 0 + - name: Level1 + description: Level 1 + value: 1 + - name: Level2 + description: Level 2 + value: 3 +enum/STRT: + bit_size: 1 + variants: + - name: Start + description: Trigger an erase operation + value: 1 +enum/VDDA_MONITOR: + bit_size: 1 + variants: + - name: Disabled + description: VDDA power supply supervisor disabled + value: 0 + - name: Enabled + description: VDDA power supply supervisor enabled + value: 1 +enum/WDG_SW: + bit_size: 1 + variants: + - name: Hardware + description: Hardware watchdog + value: 0 + - name: Software + description: Software watchdog + value: 1 +enum/WRPRT: + bit_size: 1 + variants: + - name: NoError + description: No write protection error occurred + value: 0 + - name: Error + description: A write protection error occurred + value: 1 +enum/nBOOT0: + bit_size: 1 + variants: + - name: Disabled + description: "When BOOT_SEL is cleared, select the device boot mode" + value: 0 + - name: Enabled + description: "When BOOT_SEL is cleared, select the device boot mode" + value: 1 +enum/nBOOT1: + bit_size: 1 + variants: + - name: Disabled + description: "Together with BOOT0, select the device boot mode" + value: 0 + - name: Enabled + description: "Together with BOOT0, select the device boot mode" + value: 1 +enum/nRST_STDBY: + bit_size: 1 + variants: + - name: Reset + description: Reset generated when entering Standby mode + value: 0 + - name: NoReset + description: No reset generated + value: 1 +enum/nRST_STOP: + bit_size: 1 + variants: + - name: Reset + description: Reset generated when entering Stop mode + value: 0 + - name: NoReset + description: No reset generated + value: 1 diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml new file mode 100644 index 0000000..8a6fe68 --- /dev/null +++ b/data/registers/rcc_f0.yaml @@ -0,0 +1,1249 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 + - name: CR2 + description: Clock control register 2 + byte_offset: 52 + fieldset: CR2 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMAEN + description: DMA clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLITFEN + description: FLITF clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: IOPAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: IOPBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: IOPCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: IOPDEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: IOPEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: IOPFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: IOPARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: IOPBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: IOPCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: IOPDRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: IOPERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: IOPFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: USART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB interface clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN interface clock enable + bit_offset: 25 + bit_size: 1 + - name: CRSEN + description: Clock Recovery System interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: HDMI CEC interface clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + - name: USART5RST + description: USART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB interface reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN interface reset + bit_offset: 25 + bit_size: 1 + - name: CRSRST + description: Clock Recovery System interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: HDMI CEC reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: USART7EN + description: USART7 clock enable + bit_offset: 6 + bit_size: 1 + - name: USART8EN + description: USART8 clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: USART7RST + description: USART7 reset + bit_offset: 6 + bit_size: 1 + - name: USART8RST + description: USART8 reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: APCPRE is deprecated. See ADC field in CFGR2 register. + bit_offset: 14 + bit_size: 1 + - name: PLLSRC + description: PLL input clock source + bit_offset: 15 + bit_size: 2 + enum: PLLSRC + - name: PLLXTPRE + description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning" + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: PLL clock not divided for MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: USBSW + description: USB clock source selection + bit_offset: 7 + bit_size: 1 + enum: USBSW + - name: ADCSW + description: ADCSW is deprecated. See ADC field in CFGR2 register. + bit_offset: 8 + bit_size: 1 + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source + bit_offset: 18 + bit_size: 2 + enum: USARTSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: LSIRDYFR + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: LSIRDYFR + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSI14RDYF + description: HSI14 ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + enum_read: LSIRDYFR + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + enum: LSIRDYIE + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + enum: LSIRDYIE + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + enum: LSIRDYIE + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + enum: LSIRDYIE + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + enum: LSIRDYIE + - name: HSI14RDYIE + description: HSI14 ready interrupt enable + bit_offset: 13 + bit_size: 1 + enum: LSIRDYIE + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 14 + bit_size: 1 + enum: LSIRDYIE + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + enum_write: LSIRDYCW + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + enum_write: LSIRDYCW + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSI14RDYC + description: HSI 14 MHz Ready Interrupt Clear + bit_offset: 21 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSI48RDYC + description: HSI48 Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + enum_write: LSIRDYCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSIRDYR + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: HSIRDYR +fieldset/CR2: + description: Clock control register 2 + fields: + - name: HSI14ON + description: HSI14 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI14RDY + description: HR14 clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSIRDYR + - name: HSI14DIS + description: HSI14 clock request from ADC disable + bit_offset: 2 + bit_size: 1 + enum: HSIDIS + - name: HSI14TRIM + description: HSI14 clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSI14CAL + description: HSI14 clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSI48CAL + description: HSI48 factory clock calibration + bit_offset: 24 + bit_size: 8 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: V18PWRRSTF + description: 1.8 V domain reset flag + bit_offset: 23 + bit_size: 1 + enum_read: OBLRSTFR + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + enum_read: OBLRSTFR + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: OBLRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: OBLRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: OBLRSTFR + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: OBLRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: OBLRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: OBLRSTFR +enum/CECSW: + bit_size: 1 + variants: + - name: HSI_Div244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear CSSF flag + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interrupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIDIS: + bit_size: 1 + variants: + - name: Allow + description: ADC can turn on the HSI14 oscillator + value: 0 + - name: Disallow + description: ADC can not turn on the HSI14 oscillator + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: HSI48 oscillator ready + value: 0 + - name: Ready + description: HSI48 oscillator ready + value: 1 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/LSIRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO: + bit_size: 3 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: HSI14 + description: Internal RC 14 MHz (HSI14) oscillator clock selected + value: 1 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" + value: 7 + - name: HSI48 + description: Internal RC 48 MHz (HSI48) oscillator clock selected + value: 8 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/OBLRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLNODIV: + bit_size: 1 + variants: + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 +enum/PLLSRC: + bit_size: 2 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSI_Div_PREDIV + description: HSI divided by PREDIV selected as PLL input clock + value: 1 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 2 + - name: HSI48_Div_PREDIV + description: HSI48 divided by PREDIV selected as PLL input clock + value: 3 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 + - name: HSI48 + description: HSI48 selected as system clock (when available) + value: 3 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 + - name: HSI48 + description: HSI48 used as system clock (when avaiable) + value: 3 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 +enum/USBSW: + bit_size: 1 + variants: + - name: HSI48 + description: HSI48 selected as USB clock source + value: 0 + - name: PLLCLK + description: PLL clock selected as USB clock source + value: 1 diff --git a/data/registers/rcc_f0x0.yaml b/data/registers/rcc_f0x0.yaml new file mode 100644 index 0000000..e68b7b4 --- /dev/null +++ b/data/registers/rcc_f0x0.yaml @@ -0,0 +1,1153 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 + - name: CR2 + description: Clock control register 2 + byte_offset: 52 + fieldset: CR2 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMAEN + description: DMA clock enable + bit_offset: 0 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLITFEN + description: FLITF clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: IOPAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: IOPBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: IOPCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: IOPDEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: IOPFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: IOPARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: IOPBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: IOPCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: IOPDRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: IOPFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: USART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB interface clock enable + bit_offset: 23 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + - name: USART5RST + description: USART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB interface reset + bit_offset: 23 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: ADCEN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: APCPRE is deprecated. See ADC field in CFGR2 register. + bit_offset: 14 + bit_size: 1 + - name: PLLSRC + description: PLL input clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning" + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: PLL clock not divided for MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: USBSW + description: USB clock source selection + bit_offset: 7 + bit_size: 1 + enum: USBSW + - name: ADCSW + description: ADCSW is deprecated. See ADC field in CFGR2 register. + bit_offset: 8 + bit_size: 1 + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source + bit_offset: 18 + bit_size: 2 + enum: USARTSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: LSIRDYFR + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: LSIRDYFR + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSI14RDYF + description: HSI14 ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + enum_read: LSIRDYFR + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + enum: LSIRDYIE + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + enum: LSIRDYIE + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + enum: LSIRDYIE + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + enum: LSIRDYIE + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + enum: LSIRDYIE + - name: HSI14RDYIE + description: HSI14 ready interrupt enable + bit_offset: 13 + bit_size: 1 + enum: LSIRDYIE + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 14 + bit_size: 1 + enum: LSIRDYIE + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + enum_write: LSIRDYCW + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + enum_write: LSIRDYCW + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSI14RDYC + description: HSI 14 MHz Ready Interrupt Clear + bit_offset: 21 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSI48RDYC + description: HSI48 Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + enum_write: LSIRDYCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSIRDYR + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: HSIRDYR +fieldset/CR2: + description: Clock control register 2 + fields: + - name: HSI14ON + description: HSI14 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI14RDY + description: HR14 clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSIRDYR + - name: HSI14DIS + description: HSI14 clock request from ADC disable + bit_offset: 2 + bit_size: 1 + enum: HSIDIS + - name: HSI14TRIM + description: HSI14 clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSI14CAL + description: HSI14 clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSI48CAL + description: HSI48 factory clock calibration + bit_offset: 24 + bit_size: 8 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: V18PWRRSTF + description: 1.8 V domain reset flag + bit_offset: 23 + bit_size: 1 + enum_read: OBLRSTFR + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + enum_read: OBLRSTFR + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: OBLRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: OBLRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: OBLRSTFR + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: OBLRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: OBLRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: OBLRSTFR +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear CSSF flag + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interrupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIDIS: + bit_size: 1 + variants: + - name: Allow + description: ADC can turn on the HSI14 oscillator + value: 0 + - name: Disallow + description: ADC can not turn on the HSI14 oscillator + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: HSI14 oscillator not ready + value: 0 + - name: Ready + description: HSI14 oscillator ready + value: 1 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/LSIRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO: + bit_size: 3 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: HSI14 + description: Internal RC 14 MHz (HSI14) oscillator clock selected + value: 1 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" + value: 7 + - name: HSI48 + description: Internal RC 48 MHz (HSI48) oscillator clock selected + value: 8 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/OBLRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLNODIV: + bit_size: 1 + variants: + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 + - name: HSI48 + description: HSI48 selected as system clock (when available) + value: 3 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 + - name: HSI48 + description: HSI48 used as system clock (when avaiable) + value: 3 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 +enum/USBSW: + bit_size: 1 + variants: + - name: Disabled + description: USB clock disabled + value: 0 + - name: PLLCLK + description: PLL clock selected as USB clock source + value: 1 diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml new file mode 100644 index 0000000..ec2b981 --- /dev/null +++ b/data/registers/syscfg_f0.yaml @@ -0,0 +1,457 @@ +--- +block/SYSCFG: + description: System configuration controller + items: + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR2 + description: configuration register 2 + byte_offset: 24 + fieldset: CFGR2 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: PA11_PA12_RMP + description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) + bit_offset: 4 + bit_size: 1 + enum: PA11_PA12_RMP + - name: IR_MOD + description: IR Modulation Envelope signal selection + bit_offset: 6 + bit_size: 2 + enum: IR_MOD + - name: ADC_DMA_RMP + description: ADC DMA remapping bit + bit_offset: 8 + bit_size: 1 + enum: ADC_DMA_RMP + - name: USART1_TX_DMA_RMP + description: USART1_TX DMA remapping bit + bit_offset: 9 + bit_size: 1 + enum: USART1_TX_DMA_RMP + - name: USART1_RX_DMA_RMP + description: USART1_RX DMA request remapping bit + bit_offset: 10 + bit_size: 1 + enum: USART1_RX_DMA_RMP + - name: TIM16_DMA_RMP + description: TIM16 DMA request remapping bit + bit_offset: 11 + bit_size: 1 + enum: TIM16_DMA_RMP + - name: TIM17_DMA_RMP + description: TIM17 DMA request remapping bit + bit_offset: 12 + bit_size: 1 + enum: TIM17_DMA_RMP + - name: TIM16_DMA_RMP2 + description: TIM16 alternate DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM16_DMA_RMP2 + - name: TIM17_DMA_RMP2 + description: TIM17 alternate DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM17_DMA_RMP2 + - name: I2C_PB6_FMP + description: Fast Mode Plus (FM plus) driving capability activation bits. + bit_offset: 16 + bit_size: 1 + enum: I2C_PB6_FMP + - name: I2C_PB7_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 17 + bit_size: 1 + enum: I2C_PB7_FMP + - name: I2C_PB8_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 18 + bit_size: 1 + enum: I2C_PB8_FMP + - name: I2C_PB9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 19 + bit_size: 1 + enum: I2C_PB9_FMP + - name: I2C1_FMP + description: FM+ driving capability activation for I2C1 + bit_offset: 20 + bit_size: 1 + enum: I2C1_FMP + - name: I2C2_FMP + description: FM+ driving capability activation for I2C2 + bit_offset: 21 + bit_size: 1 + enum: I2C2_FMP + - name: I2C_PA9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 22 + bit_size: 1 + enum: I2C_PA9_FMP + - name: I2C_PA10_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 23 + bit_size: 1 + enum: I2C_PA10_FMP + - name: SPI2_DMA_RMP + description: SPI2 DMA request remapping bit + bit_offset: 24 + bit_size: 1 + enum: SPI2_DMA_RMP + - name: USART2_DMA_RMP + description: USART2 DMA request remapping bit + bit_offset: 25 + bit_size: 1 + enum: USART2_DMA_RMP + - name: USART3_DMA_RMP + description: USART3 DMA request remapping bit + bit_offset: 26 + bit_size: 1 + enum: USART3_DMA_RMP + - name: I2C1_DMA_RMP + description: I2C1 DMA request remapping bit + bit_offset: 27 + bit_size: 1 + enum: I2C1_DMA_RMP + - name: TIM1_DMA_RMP + description: TIM1 DMA request remapping bit + bit_offset: 28 + bit_size: 1 + enum: TIM1_DMA_RMP + - name: TIM2_DMA_RMP + description: TIM2 DMA request remapping bit + bit_offset: 29 + bit_size: 1 + enum: TIM2_DMA_RMP + - name: TIM3_DMA_RMP + description: TIM3 DMA request remapping bit + bit_offset: 30 + bit_size: 1 + enum: TIM3_DMA_RMP +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: LOCKUP_LOCK + description: Cortex-M0 LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + enum: LOCKUP_LOCK + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + enum: SRAM_PARITY_LOCK + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + enum: PVD_LOCK + - name: SRAM_PEF + description: SRAM parity flag + bit_offset: 8 + bit_size: 1 + enum_read: SRAM_PEFR + enum_write: SRAM_PEFW +fieldset/EXTICR: + description: external interrupt configuration register 1 + fields: + - name: EXTI + description: EXTI configuration bits + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 +enum/ADC_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: ADC DMA request mapped on DMA channel 1 + value: 0 + - name: Remapped + description: ADC DMA request mapped on DMA channel 2 + value: 1 +enum/I2C1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively + value: 0 + - name: Remapped + description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively + value: 1 +enum/I2C1_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers + value: 1 +enum/I2C2_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers + value: 1 +enum/I2C_PA10_FMP: + bit_size: 1 + variants: + - name: Standard + description: PA10 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed + value: 1 +enum/I2C_PA9_FMP: + bit_size: 1 + variants: + - name: Standard + description: PA9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed + value: 1 +enum/I2C_PB6_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB6 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + value: 1 +enum/I2C_PB7_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB7 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + value: 1 +enum/I2C_PB8_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB8 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + value: 1 +enum/I2C_PB9_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + value: 1 +enum/IR_MOD: + bit_size: 2 + variants: + - name: TIM16 + description: TIM16 selected + value: 0 + - name: USART1 + description: USART1 selected + value: 1 + - name: USART4 + description: USART4 selected + value: 2 +enum/LOCKUP_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input + value: 1 +enum/MEM_MODE: + bit_size: 2 + variants: + - name: MainFlash + description: Main Flash memory mapped at 0x0000_0000 + value: 0 + - name: SystemFlash + description: System Flash memory mapped at 0x0000_0000 + value: 1 + - name: MainFlash2 + description: Main Flash memory mapped at 0x0000_0000 + value: 2 + - name: SRAM + description: Embedded SRAM mapped at 0x0000_0000 + value: 3 +enum/PA11_PA12_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Pin pair PA9/PA10 mapped on the pins + value: 0 + - name: Remapped + description: Pin pair PA11/PA12 mapped instead of PA9/PA10 + value: 1 +enum/PVD_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: PVD interrupt disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: PVD interrupt connected to TIM1/15/16/17 Break input + value: 1 +enum/SPI2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively + value: 0 + - name: Remapped + description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively + value: 1 +enum/SRAM_PARITY_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: SRAM parity error disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: SRAM parity error connected to TIM1/15/16/17 Break input + value: 1 +enum/SRAM_PEFR: + bit_size: 1 + variants: + - name: NoParityError + description: No SRAM parity error detected + value: 0 + - name: ParityErrorDetected + description: SRAM parity error detected + value: 1 +enum/SRAM_PEFW: + bit_size: 1 + variants: + - name: Clear + description: Clear SRAM parity error flag + value: 1 +enum/TIM16_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 + value: 0 + - name: Remapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 + value: 1 +enum/TIM16_DMA_RMP2: + bit_size: 1 + variants: + - name: NotAlternateRemapped + description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit + value: 0 + - name: AlternateRemapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 + value: 1 +enum/TIM17_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 + value: 0 + - name: Remapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 + value: 1 +enum/TIM17_DMA_RMP2: + bit_size: 1 + variants: + - name: NotAlternateRemapped + description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit + value: 0 + - name: AlternateRemapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 + value: 1 +enum/TIM1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively" + value: 0 + - name: Remapped + description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6" + value: 1 +enum/TIM2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively + value: 0 + - name: Remapped + description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 + value: 1 +enum/TIM3_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 + value: 0 + - name: Remapped + description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 + value: 1 +enum/USART1_RX_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART1_RX DMA request mapped on DMA channel 3 + value: 0 + - name: Remapped + description: USART1_RX DMA request mapped on DMA channel 5 + value: 1 +enum/USART1_TX_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART1_TX DMA request mapped on DMA channel 2 + value: 0 + - name: Remapped + description: USART1_TX DMA request mapped on DMA channel 4 + value: 1 +enum/USART2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively + value: 0 + - name: Remapped + description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively + value: 1 +enum/USART3_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) + value: 0 + - name: Remapped + description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively + value: 1 diff --git a/parse.py b/parse.py index 3e0d585..0991f64 100644 --- a/parse.py +++ b/parse.py @@ -311,6 +311,7 @@ perimap = [ ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'), ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'), ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'), + ('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), @@ -321,6 +322,8 @@ perimap = [ ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'), + ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'), + ('STM32F0.*:RCC:.*', 'rcc_f0/RCC'), ('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'), @@ -328,6 +331,7 @@ perimap = [ ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), + ('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'), ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'),