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split FMC into NOR_PSRAM, NAND and SDRAM

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This commit is contained in:
eZio Pan 2024-02-24 17:05:04 +08:00
parent de08d9fe06
commit ac3b6c2054
2 changed files with 60 additions and 24 deletions
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63
data/registers/fmc_v4.yaml
View File

@ -1,5 +1,37 @@
block/FMC: block/FMC:
description: Flexible memory controller. description: Flexible memory controller.
items:
- name: NOR_PSRAM
byte_offset: 0
block: NOR_PSRAM
- name: NAND
byte_offset: 128
block: NAND
- name: SDRAM
byte_offset: 320
block: SDRAM
block/NAND:
items:
- name: PCR
description: NAND Flash control registers.
byte_offset: 0
fieldset: PCR
- name: SR
description: FIFO status and interrupt register.
byte_offset: 4
fieldset: SR
- name: PMEM
description: Common memory space timing register.
byte_offset: 8
fieldset: PMEM
- name: PATT
description: Attribute memory space timing register.
byte_offset: 12
fieldset: PATT
- name: ECCR
description: ECC result registers.
byte_offset: 20
block/NOR_PSRAM:
items: items:
- name: BCR1 - name: BCR1
description: SRAM/NOR-Flash chip-select control register for bank 1. description: SRAM/NOR-Flash chip-select control register for bank 1.
@ -23,25 +55,6 @@ block/FMC:
description: PSRAM chip select counter register. description: PSRAM chip select counter register.
byte_offset: 32 byte_offset: 32
fieldset: PCSCNTR fieldset: PCSCNTR
- name: PCR
description: NAND Flash control registers.
byte_offset: 128
fieldset: PCR
- name: SR
description: FIFO status and interrupt register.
byte_offset: 132
fieldset: SR
- name: PMEM
description: Common memory space timing register.
byte_offset: 136
fieldset: PMEM
- name: PATT
description: Attribute memory space timing register.
byte_offset: 140
fieldset: PATT
- name: ECCR
description: ECC result registers.
byte_offset: 148
- name: BWTR - name: BWTR
description: SRAM/NOR-Flash write timing registers 1. description: SRAM/NOR-Flash write timing registers 1.
array: array:
@ -49,31 +62,33 @@ block/FMC:
stride: 8 stride: 8
byte_offset: 260 byte_offset: 260
fieldset: BWTR fieldset: BWTR
block/SDRAM:
items:
- name: SDCR - name: SDCR
description: SDRAM control registers 1. description: SDRAM control registers 1.
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 320 byte_offset: 0
fieldset: SDCR fieldset: SDCR
- name: SDTR - name: SDTR
description: SDRAM timing registers 1. description: SDRAM timing registers 1.
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 328 byte_offset: 8
fieldset: SDTR fieldset: SDTR
- name: SDCMR - name: SDCMR
description: SDRAM Command Mode register. description: SDRAM Command Mode register.
byte_offset: 336 byte_offset: 16
fieldset: SDCMR fieldset: SDCMR
- name: SDRTR - name: SDRTR
description: SDRAM refresh timer register. description: SDRAM refresh timer register.
byte_offset: 340 byte_offset: 20
fieldset: SDRTR fieldset: SDRTR
- name: SDSR - name: SDSR
description: SDRAM status register. description: SDRAM status register.
byte_offset: 344 byte_offset: 24
fieldset: SDSR fieldset: SDSR
fieldset/BCR: fieldset/BCR:
description: SRAM/NOR-Flash chip-select control register for bank 4. description: SRAM/NOR-Flash chip-select control register for bank 4.

21
transforms/FMC.yaml
View File

@ -19,3 +19,24 @@ transforms:
blocks: FMC blocks: FMC
from: ^(BTR|BWTR|SDCR|SDTR)\d+$ from: ^(BTR|BWTR|SDCR|SDTR)\d+$
to: $1 to: $1
- !MakeBlock
blocks: FMC
from: ^(BCR\d*|BW?TR\d*|PCSCNTR)$
to_outer: NOR_PSRAM
to_block: NOR_PSRAM
to_inner: $1
- !MakeBlock
blocks: FMC
from: ^(PCR|SR|PMEM|PATT|ECCR)$
to_outer: NAND
to_block: NAND
to_inner: $1
- !MakeBlock
blocks: FMC
from: ^(SDCR\d*|SDTR\d*|SDCMR|SDRTR|SDSR)$
to_outer: SDRAM
to_block: SDRAM
to_inner: $1