Add usart v2
This commit is contained in:
Dario Nieuwenhuis
parent
5e59f22819
commit
abf5d3f2a2
737
data/registers/usart_v2.yaml
Normal file
737
data/registers/usart_v2.yaml
Normal file
@ -0,0 +1,737 @@
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---
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block/USART:
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description: Universal synchronous asynchronous receiver transmitter
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items:
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- name: CR1
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description: Control register 1
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byte_offset: 0
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fieldset: CR1
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- name: CR2
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description: Control register 2
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byte_offset: 4
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fieldset: CR2
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- name: CR3
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description: Control register 3
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byte_offset: 8
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fieldset: CR3
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- name: BRR
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description: Baud rate register
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byte_offset: 12
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fieldset: BRR
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- name: GTPR
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description: Guard time and prescaler register
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byte_offset: 16
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fieldset: GTPR
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- name: RTOR
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description: Receiver timeout register
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byte_offset: 20
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fieldset: RTOR
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- name: RQR
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description: Request register
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byte_offset: 24
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access: Write
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fieldset: RQR
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- name: ISR
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description: Interrupt & status register
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byte_offset: 28
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access: Read
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fieldset: IXR
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- name: ICR
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description: Interrupt flag clear register
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byte_offset: 32
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access: Write
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fieldset: IXR
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- name: RDR
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description: Receive data register
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byte_offset: 36
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access: Read
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fieldset: DR
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- name: TDR
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description: Transmit data register
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byte_offset: 40
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fieldset: DR
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fieldset/BRR:
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description: Baud rate register
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fields:
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- name: BRR
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description: mantissa of USARTDIV
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bit_offset: 0
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bit_size: 16
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fieldset/CR1:
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description: Control register 1
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fields:
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- name: UE
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description: USART enable
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bit_offset: 0
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bit_size: 1
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- name: UESM
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description: USART enable in Stop mode
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bit_offset: 1
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bit_size: 1
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- name: RE
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description: Receiver enable
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bit_offset: 2
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bit_size: 1
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- name: TE
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description: Transmitter enable
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bit_offset: 3
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bit_size: 1
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- name: IDLEIE
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description: IDLE interrupt enable
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bit_offset: 4
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bit_size: 1
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- name: RXNEIE
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description: RXNE interrupt enable
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bit_offset: 5
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bit_size: 1
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- name: TCIE
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description: Transmission complete interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: TXEIE
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description: interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: PEIE
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description: PE interrupt enable
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bit_offset: 8
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bit_size: 1
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- name: PS
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description: Parity selection
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bit_offset: 9
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bit_size: 1
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enum: PS
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- name: PCE
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description: Parity control enable
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bit_offset: 10
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bit_size: 1
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- name: WAKE
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description: Receiver wakeup method
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bit_offset: 11
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bit_size: 1
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- name: M0
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description: Word length
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bit_offset: 12
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bit_size: 1
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enum: M0
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- name: MME
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description: Mute mode enable
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bit_offset: 13
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bit_size: 1
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- name: CMIE
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description: Character match interrupt enable
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bit_offset: 14
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bit_size: 1
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- name: OVER
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description: Oversampling mode
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bit_offset: 15
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bit_size: 1
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array:
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len: 1
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stride: 0
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enum: OVER
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- name: DEDT
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description: Driver Enable deassertion time
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bit_offset: 16
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bit_size: 5
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- name: DEAT
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description: Driver Enable assertion time
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bit_offset: 21
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bit_size: 5
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- name: RTOIE
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description: Receiver timeout interrupt enable
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bit_offset: 26
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bit_size: 1
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- name: EOBIE
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description: End of Block interrupt enable
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bit_offset: 27
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bit_size: 1
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- name: M1
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description: Word length
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bit_offset: 12
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bit_size: 1
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enum: M1
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fieldset/CR2:
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description: Control register 2
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fields:
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- name: ADDM
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description: 7-bit Address Detection/4-bit Address Detection
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bit_offset: 4
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bit_size: 1
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array:
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len: 1
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stride: 0
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enum: ADDM
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- name: LBDL
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description: LIN break detection length
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bit_offset: 5
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bit_size: 1
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enum: LBDL
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- name: LBDIE
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description: LIN break detection interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: LBCL
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description: Last bit clock pulse
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bit_offset: 8
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bit_size: 1
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enum: LBCL
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- name: CPHA
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description: Clock phase
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bit_offset: 9
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bit_size: 1
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enum: CPHA
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- name: CPOL
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description: Clock polarity
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bit_offset: 10
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bit_size: 1
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enum: CPOL
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- name: CLKEN
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description: Clock enable
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bit_offset: 11
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bit_size: 1
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- name: STOP
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description: STOP bits
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bit_offset: 12
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bit_size: 2
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enum: STOP
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- name: LINEN
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description: LIN mode enable
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bit_offset: 14
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bit_size: 1
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- name: SWAP
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description: Swap TX/RX pins
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bit_offset: 15
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bit_size: 1
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enum: SWAP
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- name: RXINV
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description: RX pin active level inversion
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bit_offset: 16
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bit_size: 1
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enum: RXINV
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- name: TXINV
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description: TX pin active level inversion
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bit_offset: 17
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bit_size: 1
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enum: TXINV
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- name: DATAINV
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description: Binary data inversion
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bit_offset: 18
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bit_size: 1
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enum: DATAINV
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- name: MSBFIRST
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description: Most significant bit first
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bit_offset: 19
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bit_size: 1
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enum: MSBFIRST
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- name: ABREN
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description: Auto baud rate enable
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bit_offset: 20
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bit_size: 1
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- name: ABRMOD
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description: Auto baud rate mode
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bit_offset: 21
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bit_size: 2
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enum: ABRMOD
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- name: RTOEN
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description: Receiver timeout enable
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bit_offset: 23
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bit_size: 1
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- name: ADD
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description: Address of the USART node
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bit_offset: 24
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bit_size: 8
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fieldset/CR3:
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description: Control register 3
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fields:
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- name: EIE
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description: Error interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: IREN
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description: IrDA mode enable
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bit_offset: 1
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bit_size: 1
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- name: IRLP
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description: IrDA low-power
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bit_offset: 2
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bit_size: 1
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enum: IRLP
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- name: HDSEL
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description: Half-duplex selection
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bit_offset: 3
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bit_size: 1
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enum: HDSEL
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- name: NACK
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description: Smartcard NACK enable
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bit_offset: 4
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bit_size: 1
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- name: SCEN
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description: Smartcard mode enable
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bit_offset: 5
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bit_size: 1
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- name: DMAR
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description: DMA enable receiver
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bit_offset: 6
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bit_size: 1
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- name: DMAT
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description: DMA enable transmitter
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bit_offset: 7
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bit_size: 1
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- name: RTSE
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description: RTS enable
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bit_offset: 8
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bit_size: 1
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- name: CTSE
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description: CTS enable
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bit_offset: 9
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bit_size: 1
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- name: CTSIE
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description: CTS interrupt enable
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bit_offset: 10
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bit_size: 1
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- name: ONEBIT
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description: One sample bit method enable
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bit_offset: 11
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bit_size: 1
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enum: ONEBIT
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- name: OVRDIS
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description: Overrun Disable
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bit_offset: 12
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bit_size: 1
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enum: OVRDIS
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- name: DDRE
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description: DMA Disable on Reception Error
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bit_offset: 13
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bit_size: 1
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- name: DEM
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description: Driver enable mode
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bit_offset: 14
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bit_size: 1
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- name: DEP
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description: Driver enable polarity selection
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bit_offset: 15
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bit_size: 1
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enum: DEP
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- name: SCARCNT
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description: Smartcard auto-retry count
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bit_offset: 17
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bit_size: 3
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- name: WUS
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description: Wakeup from Stop mode interrupt flag selection
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bit_offset: 20
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bit_size: 2
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enum: WUS
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- name: WUFIE
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description: Wakeup from Stop mode interrupt enable
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bit_offset: 22
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bit_size: 1
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fieldset/GTPR:
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description: Guard time and prescaler register
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fields:
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- name: PSC
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description: Prescaler value
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bit_offset: 0
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bit_size: 8
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- name: GT
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description: Guard time value
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bit_offset: 8
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bit_size: 8
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fieldset/IXR:
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description: Interrupt & status register
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fields:
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- name: PE
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description: Parity error
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bit_offset: 0
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bit_size: 1
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- name: FE
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description: Framing error
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bit_offset: 1
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bit_size: 1
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- name: NF
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description: Noise detected flag
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bit_offset: 2
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bit_size: 1
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- name: ORE
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description: Overrun error
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bit_offset: 3
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bit_size: 1
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- name: IDLE
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description: Idle line detected
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bit_offset: 4
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bit_size: 1
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- name: RXNE
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description: Read data register not empty
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bit_offset: 5
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bit_size: 1
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- name: TC
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description: Transmission complete
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bit_offset: 6
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bit_size: 1
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- name: TXE
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description: Transmit data register empty
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bit_offset: 7
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bit_size: 1
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- name: LBDF
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description: LIN break detection flag
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bit_offset: 8
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bit_size: 1
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- name: CTSIF
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description: CTS interrupt flag
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bit_offset: 9
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bit_size: 1
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- name: CTS
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description: CTS flag
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bit_offset: 10
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bit_size: 1
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- name: RTOF
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description: Receiver timeout
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bit_offset: 11
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bit_size: 1
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- name: EOBF
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description: End of block flag
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bit_offset: 12
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bit_size: 1
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- name: ABRE
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description: Auto baud rate error
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bit_offset: 14
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bit_size: 1
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- name: ABRF
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description: Auto baud rate flag
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bit_offset: 15
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bit_size: 1
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- name: BUSY
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description: Busy flag
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bit_offset: 16
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bit_size: 1
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- name: CMF
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description: character match flag
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bit_offset: 17
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bit_size: 1
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- name: SBKF
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description: Send break flag
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bit_offset: 18
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bit_size: 1
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- name: RWU
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description: Receiver wakeup from Mute mode
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bit_offset: 19
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bit_size: 1
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- name: WUF
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description: Wakeup from Stop mode flag
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bit_offset: 20
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bit_size: 1
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- name: TEACK
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description: Transmit enable acknowledge flag
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bit_offset: 21
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bit_size: 1
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- name: REACK
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description: Receive enable acknowledge flag
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bit_offset: 22
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bit_size: 1
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fieldset/DR:
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description: Data register
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fields:
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- name: DR
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description: data value
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bit_offset: 0
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bit_size: 9
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fieldset/RQR:
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description: Request register
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fields:
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- name: ABRRQ
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description: Auto baud rate request
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bit_offset: 0
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bit_size: 1
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enum: ABRRQ
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- name: SBKRQ
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description: Send break request
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bit_offset: 1
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bit_size: 1
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enum: SBKRQ
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- name: MMRQ
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description: Mute mode request
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bit_offset: 2
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bit_size: 1
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enum: MMRQ
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- name: RXFRQ
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description: Receive data flush request
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bit_offset: 3
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bit_size: 1
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enum: RXFRQ
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- name: TXFRQ
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description: Transmit data flush request
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bit_offset: 4
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bit_size: 1
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enum: TXFRQ
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fieldset/RTOR:
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description: Receiver timeout register
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fields:
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- name: RTO
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description: Receiver timeout value
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bit_offset: 0
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bit_size: 24
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- name: BLEN
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description: Block Length
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bit_offset: 24
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bit_size: 8
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enum/ABRMOD:
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bit_size: 2
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variants:
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- name: Start
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description: Measurement of the start bit is used to detect the baud rate
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value: 0
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- name: Edge
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description: Falling edge to falling edge measurement
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value: 1
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- name: Frame7F
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description: "0x7F frame detection"
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value: 2
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- name: Frame55
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description: "0x55 frame detection"
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value: 3
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enum/ABRRQ:
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bit_size: 1
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variants:
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- name: Request
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description: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
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value: 1
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enum/ADDM:
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bit_size: 1
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variants:
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- name: Bit4
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description: 4-bit address detection
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value: 0
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- name: Bit7
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description: 7-bit address detection
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value: 1
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enum/CPHA:
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bit_size: 1
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variants:
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- name: First
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description: The first clock transition is the first data capture edge
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value: 0
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- name: Second
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description: The second clock transition is the first data capture edge
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value: 1
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enum/CPOL:
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bit_size: 1
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variants:
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- name: Low
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description: Steady low value on CK pin outside transmission window
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value: 0
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- name: High
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description: Steady high value on CK pin outside transmission window
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value: 1
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enum/DATAINV:
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bit_size: 1
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variants:
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- name: Positive
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description: Logical data from the data register are send/received in positive/direct logic
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value: 0
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- name: Negative
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description: Logical data from the data register are send/received in negative/inverse logic
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value: 1
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enum/DDRE:
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bit_size: 1
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variants:
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- name: NotDisabled
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description: DMA is not disabled in case of reception error
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value: 0
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- name: Disabled
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description: DMA is disabled following a reception error
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value: 1
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enum/DEP:
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bit_size: 1
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variants:
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- name: High
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description: DE signal is active high
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value: 0
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- name: Low
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description: DE signal is active low
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value: 1
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enum/HDSEL:
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bit_size: 1
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variants:
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- name: NotSelected
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description: Half duplex mode is not selected
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value: 0
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- name: Selected
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description: Half duplex mode is selected
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value: 1
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enum/IRLP:
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bit_size: 1
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variants:
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- name: Normal
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description: Normal mode
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value: 0
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- name: LowPower
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||||
description: Low-power mode
|
||||
value: 1
|
||||
enum/LBCL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotOutput
|
||||
description: The clock pulse of the last data bit is not output to the CK pin
|
||||
value: 0
|
||||
- name: Output
|
||||
description: The clock pulse of the last data bit is output to the CK pin
|
||||
value: 1
|
||||
enum/LBDL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Bit10
|
||||
description: 10-bit break detection
|
||||
value: 0
|
||||
- name: Bit11
|
||||
description: 11-bit break detection
|
||||
value: 1
|
||||
enum/M0:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Bit8
|
||||
description: "1 start bit, 8 data bits, n stop bits"
|
||||
value: 0
|
||||
- name: Bit9
|
||||
description: "1 start bit, 9 data bits, n stop bits"
|
||||
value: 1
|
||||
enum/M1:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: M0
|
||||
description: Use M0 to set the data bits
|
||||
value: 0
|
||||
- name: Bit7
|
||||
description: "1 start bit, 7 data bits, n stop bits"
|
||||
value: 1
|
||||
enum/MMRQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Mute
|
||||
description: Puts the USART in mute mode and sets the RWU flag
|
||||
value: 1
|
||||
enum/MSBFIRST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: LSB
|
||||
description: "data is transmitted/received with data bit 0 first, following the start bit"
|
||||
value: 0
|
||||
- name: MSB
|
||||
description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"
|
||||
value: 1
|
||||
enum/ONEBIT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Sample3
|
||||
description: Three sample bit method
|
||||
value: 0
|
||||
- name: Sample1
|
||||
description: One sample bit method
|
||||
value: 1
|
||||
enum/OVER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Oversampling16
|
||||
description: Oversampling by 16
|
||||
value: 0
|
||||
- name: Oversampling8
|
||||
description: Oversampling by 8
|
||||
value: 1
|
||||
enum/OVRDIS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
|
||||
value: 1
|
||||
enum/PS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Even
|
||||
description: Even parity
|
||||
value: 0
|
||||
- name: Odd
|
||||
description: Odd parity
|
||||
value: 1
|
||||
enum/RXFRQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Discard
|
||||
description: "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"
|
||||
value: 1
|
||||
enum/RXINV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Standard
|
||||
description: RX pin signal works using the standard logic levels
|
||||
value: 0
|
||||
- name: Inverted
|
||||
description: RX pin signal values are inverted
|
||||
value: 1
|
||||
enum/SBKRQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Break
|
||||
description: "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"
|
||||
value: 1
|
||||
enum/STOP:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Stop1
|
||||
description: 1 stop bit
|
||||
value: 0
|
||||
- name: Stop0p5
|
||||
description: 0.5 stop bit
|
||||
value: 1
|
||||
- name: Stop2
|
||||
description: 2 stop bit
|
||||
value: 2
|
||||
- name: Stop1p5
|
||||
description: 1.5 stop bit
|
||||
value: 3
|
||||
enum/SWAP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Standard
|
||||
description: TX/RX pins are used as defined in standard pinout
|
||||
value: 0
|
||||
- name: Swapped
|
||||
description: The TX and RX pins functions are swapped
|
||||
value: 1
|
||||
enum/TXFRQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Discard
|
||||
description: Set the TXE flags. This allows to discard the transmit data
|
||||
value: 1
|
||||
enum/TXINV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Standard
|
||||
description: TX pin signal works using the standard logic levels
|
||||
value: 0
|
||||
- name: Inverted
|
||||
description: TX pin signal values are inverted
|
||||
value: 1
|
||||
enum/WAKE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Idle
|
||||
description: Idle line
|
||||
value: 0
|
||||
- name: Address
|
||||
description: Address mask
|
||||
value: 1
|
||||
enum/WUS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Address
|
||||
description: WUF active on address match
|
||||
value: 0
|
||||
- name: Start
|
||||
description: WuF active on Start bit detection
|
||||
value: 2
|
||||
- name: RXNE
|
||||
description: WUF active on RXNE
|
||||
value: 3
|
||||
Loading…
x
Reference in New Issue
Block a user