extract

data/registers/comp_h5.yaml

@@ -0,0 +1,99 @@
+block/COMP:
+  description: Comparator.
+  items:
+  - name: COMP_SR
+    description: Comparator status register.
+    byte_offset: 0
+    fieldset: COMP_SR
+  - name: COMP_ICFR
+    description: Comparator interrupt clear flag register.
+    byte_offset: 4
+    fieldset: COMP_ICFR
+  - name: COMP_CFGR1
+    description: Comparator configuration register 1.
+    byte_offset: 12
+    fieldset: COMP_CFGR1
+  - name: COMP_CFGR2
+    description: Comparator configuration register 2.
+    byte_offset: 16
+    fieldset: COMP_CFGR2
+fieldset/COMP_CFGR1:
+  description: Comparator configuration register 1.
+  fields:
+  - name: EN
+    description: COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP<4D>Channel1.
+    bit_offset: 0
+    bit_size: 1
+  - name: BRGEN
+    description: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V<sub>REF_COMP</sub> (similar to V<sub>REFINT</sub>). If SCALEN and BRGEN are set, the four scaler outputs provide V<sub>REF_COMP</sub>, 3/4<>V<sub>REF_COMP</sub>, 1/2<>V<sub>REF_COMP</sub> and 1/4<>V<sub>REF_COMP</sub> levels, respectively.
+    bit_offset: 1
+    bit_size: 1
+  - name: SCALEN
+    description: Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the V<sub>REFINT</sub> scaler for the COMP channels.
+    bit_offset: 2
+    bit_size: 1
+  - name: POLARITY
+    description: COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity.
+    bit_offset: 3
+    bit_size: 1
+  - name: ITEN
+    description: COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1.
+    bit_offset: 6
+    bit_size: 1
+  - name: HYST
+    description: COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1.
+    bit_offset: 8
+    bit_size: 2
+  - name: PWRMODE
+    description: Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1.
+    bit_offset: 12
+    bit_size: 2
+  - name: INMSEL
+    description: 'COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table<6C>146: COMP1 inverting input assignment for more details.'
+    bit_offset: 16
+    bit_size: 4
+  - name: INPSEL1
+    description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table<6C>145: COMP1 noninverting input assignment for more details.'
+    bit_offset: 20
+    bit_size: 1
+  - name: INPSEL2
+    description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table<6C>145: COMP1 noninverting input assignment for more details.'
+    bit_offset: 22
+    bit_size: 1
+  - name: BLANKING
+    description: 'COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved.'
+    bit_offset: 24
+    bit_size: 4
+  - name: LOCK
+    description: Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0].
+    bit_offset: 31
+    bit_size: 1
+fieldset/COMP_CFGR2:
+  description: Comparator configuration register 2.
+  fields:
+  - name: INPSEL0
+    description: 'COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table<6C>145: COMP1 noninverting input assignment for more details.'
+    bit_offset: 4
+    bit_size: 1
+  - name: LOCK
+    description: Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0].
+    bit_offset: 31
+    bit_size: 1
+fieldset/COMP_ICFR:
+  description: Comparator interrupt clear flag register.
+  fields:
+  - name: CC1IF
+    description: Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register.
+    bit_offset: 16
+    bit_size: 1
+fieldset/COMP_SR:
+  description: Comparator status register.
+  fields:
+  - name: C1VAL
+    description: COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
+    bit_offset: 0
+    bit_size: 1
+  - name: C1IF
+    description: COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.
+    bit_offset: 16
+    bit_size: 1