From ab99fff0af448cae804c3270088fa0b2ce7416d3 Mon Sep 17 00:00:00 2001 From: Olle Sandberg Date: Mon, 4 Sep 2023 09:04:34 +0200 Subject: [PATCH] Support STM32WLEx ADC peripheral Use adc_g0 since very similar to the WLE one. --- data/registers/rcc_wle.yaml | 13 +++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 14 insertions(+) diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index c130d96..0ebd82c 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -689,6 +689,7 @@ fieldset/CCIPR: description: ADC clock source selection bit_offset: 28 bit_size: 2 + enum: ADCSEL - name: RNGSEL description: RNG clock source selection bit_offset: 30 @@ -1044,3 +1045,15 @@ fieldset/PLLCFGR: description: Main PLL division factor for PLLRCLK bit_offset: 29 bit_size: 3 +enum/ADCSEL: + bit_size: 2 + variants: + - name: HSI16 + description: HSI16 used as ADC clock source + value: 1 + - name: PLLPCLK + description: PLLPCLK used as ADC clock source + value: 2 + - name: SYSCLK + description: SYSCLK used as ADC clock source + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 07fa785..dda3ed6 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -208,6 +208,7 @@ impl PeriMatcher { ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")), + ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")), ("STM32H5.*:SBS:.*", ("sbs", "h5", "SBS")), (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")),