From ab8905103047eac0a96e2919dc7df93377880af4 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 14 Feb 2024 00:53:34 +0100 Subject: [PATCH] rcc: Rename TIMI2C -> TIMIC. --- data/registers/rcc_h5.yaml | 6 +++--- data/registers/rcc_h50.yaml | 6 +++--- data/registers/rcc_u5.yaml | 8 ++++---- data/registers/rcc_wba.yaml | 8 ++++---- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 6c6c2a8..963dcad 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -1449,11 +1449,11 @@ fieldset/CCIPR1: bit_offset: 27 bit_size: 3 enum: USARTSEL - - name: TIMI2CSEL + - name: TIMICSEL description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software." bit_offset: 31 bit_size: 1 - enum: TIMI2CSEL + enum: TIMICSEL fieldset/CCIPR2: description: RCC kernel clock configuration register fields: @@ -4121,7 +4121,7 @@ enum/SYSTICKSEL: - name: LSE description: lse_ck[1] selected as clock source value: 2 -enum/TIMI2CSEL: +enum/TIMICSEL: bit_size: 1 variants: - name: B_0x0 diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index a97a5fb..542a9a0 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -813,11 +813,11 @@ fieldset/CCIPR1: bit_offset: 6 bit_size: 3 enum: USARTSEL - - name: TIMI2CSEL + - name: TIMICSEL description: "TIM2, TIM3 and LPTIM2 input capture source selection\r Set and reset by software." bit_offset: 31 bit_size: 1 - enum: TIMI2CSEL + enum: TIMICSEL fieldset/CCIPR2: description: RCC kernel clock configuration register fields: @@ -3162,7 +3162,7 @@ enum/SYSTICKSEL: - name: LSE description: lse_ck[1] selected as clock source value: 2 -enum/TIMI2CSEL: +enum/TIMICSEL: bit_size: 1 variants: - name: B_0x0 diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index a1b98ad..c6983e9 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -1617,11 +1617,11 @@ fieldset/CCIPR1: bit_offset: 26 bit_size: 2 enum: ICLKSEL - - name: TIMI2CSEL - description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMI2CSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMI2CSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMI2CSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMI2CSEL configured to 0xx) before selecting or changing a clock sources division." + - name: TIMICSEL + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division." bit_offset: 29 bit_size: 3 - enum: TIMI2CSEL + enum: TIMICSEL fieldset/CCIPR2: description: RCC peripherals independent clock configuration register 2 fields: @@ -4396,7 +4396,7 @@ enum/SYSTICKSEL: - name: LSE description: LSE selected value: 2 -enum/TIMI2CSEL: +enum/TIMICSEL: bit_size: 3 variants: - name: DISABLE diff --git a/data/registers/rcc_wba.yaml b/data/registers/rcc_wba.yaml index c0e4c2d..bbae58f 100644 --- a/data/registers/rcc_wba.yaml +++ b/data/registers/rcc_wba.yaml @@ -791,11 +791,11 @@ fieldset/CCIPR1: bit_offset: 22 bit_size: 2 enum: SYSTICKSEL - - name: TIMI2CSEL - description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMI2CSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. \r When TIMI2CSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMI2CSEL configured to 0) before selecting or changing a clock sources division." + - name: TIMICSEL + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. \r When TIMICSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division." bit_offset: 31 bit_size: 1 - enum: TIMI2CSEL + enum: TIMICSEL fieldset/CCIPR2: description: RCC peripherals independent clock configuration register 2 fields: @@ -1546,7 +1546,7 @@ enum/SYSTICKSEL: - name: LSE description: LSE selected value: 2 -enum/TIMI2CSEL: +enum/TIMICSEL: bit_size: 1 variants: - name: HSI