From 39b513b598d7945c7275d1a020153d4e9c165b6e Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:14:56 +0800 Subject: [PATCH 1/6] rename aes_u5 to aes_v3a --- data/registers/{aes_u5.yaml => aes_v3a.yaml} | 0 stm32-data-gen/src/chips.rs | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename data/registers/{aes_u5.yaml => aes_v3a.yaml} (100%) diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_v3a.yaml similarity index 100% rename from data/registers/aes_u5.yaml rename to data/registers/aes_v3a.yaml diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e6de9f0..20b5520 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -152,9 +152,9 @@ impl PeriMatcher { ("STM32L1.*:AES:.*", ("aes", "v1", "AES")), ("STM32L4.*:AES:.*", ("aes", "v1", "AES")), ("STM32L5.*:AES:.*", ("aes", "v2", "AES")), - ("STM32U5.*:AES:.*", ("aes", "u5", "AES")), ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), + ("STM32U5.*:AES:.*", ("aes", "v3a", "AES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 2c6cd074ef325278197e798bd21edf02809699b8 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:27:17 +0800 Subject: [PATCH 2/6] concate `CHMOD` field into one --- data/registers/aes_v3a.yaml | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/data/registers/aes_v3a.yaml b/data/registers/aes_v3a.yaml index e46fc54..bbe75a7 100644 --- a/data/registers/aes_v3a.yaml +++ b/data/registers/aes_v3a.yaml @@ -74,10 +74,15 @@ fieldset/CR: bit_offset: 3 bit_size: 2 enum: MODE - - name: CHMOD10 - description: Chaining mode bit1 bit0 - bit_offset: 5 - bit_size: 2 + - name: CHMOD + description: Chaining mode selection + bit_offset: + - start: 5 + end: 6 + - start: 16 + end: 16 + bit_size: 3 + enum: CHMOD - name: DMAINEN description: Enable DMA management of data input phase bit_offset: 11 @@ -91,10 +96,6 @@ fieldset/CR: bit_offset: 13 bit_size: 2 enum: GCMPH - - name: CHMOD2 - description: Chaining mode bit2 - bit_offset: 16 - bit_size: 1 - name: KEYSIZE description: Key size selection bit_offset: 18 @@ -256,3 +257,21 @@ enum/MODE: - name: Mode3 description: Decryption value: 2 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 From 3f975e6217e692846279740a0b0863cd3fd2811a Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:33:58 +0800 Subject: [PATCH 3/6] branch from v3a to v3b --- data/registers/aes_v3b.yaml | 277 ++++++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) create mode 100644 data/registers/aes_v3b.yaml diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml new file mode 100644 index 0000000..bbe75a7 --- /dev/null +++ b/data/registers/aes_v3b.yaml @@ -0,0 +1,277 @@ +block/AES: + description: Advanced encryption standard hardware accelerator + items: + - name: CR + description: Control register + byte_offset: 0 + fieldset: CR + - name: SR + description: Status register + byte_offset: 4 + fieldset: SR + - name: DINR + description: Data input register + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: Data output register + byte_offset: 12 + fieldset: DOUTR + - name: KEYR + description: Key register + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 + byte_offset: 16 + fieldset: KEYR + - name: IVR + description: Initialization vector register + array: + len: 4 + stride: 4 + byte_offset: 32 + fieldset: IVR + - name: SUSPR + description: Suspend register + array: + len: 8 + stride: 4 + byte_offset: 64 + fieldset: SUSPR + - name: IER + description: interrupt enable register + byte_offset: 768 + fieldset: IER + - name: ISR + description: interrupt status register + byte_offset: 772 + fieldset: ISR + - name: ICR + description: interrupt clear register + byte_offset: 776 + fieldset: ICR +fieldset/CR: + description: Control register + fields: + - name: EN + description: AES enable + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: Data type selection + bit_offset: 1 + bit_size: 2 + enum: DATATYPE + - name: MODE + description: Operating mode + bit_offset: 3 + bit_size: 2 + enum: MODE + - name: CHMOD + description: Chaining mode selection + bit_offset: + - start: 5 + end: 6 + - start: 16 + end: 16 + bit_size: 3 + enum: CHMOD + - name: DMAINEN + description: Enable DMA management of data input phase + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: Enable DMA management of data output phase + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: GCM or CCM phase selection + bit_offset: 13 + bit_size: 2 + enum: GCMPH + - name: KEYSIZE + description: Key size selection + bit_offset: 18 + bit_size: 1 + - name: NPBLB + description: Number of padding bytes in last block of payload + bit_offset: 20 + bit_size: 4 + - name: KMOD + description: Key mode selection + bit_offset: 24 + bit_size: 2 + - name: IPRST + description: AES peripheral software reset + bit_offset: 31 + bit_size: 1 +fieldset/DINR: + description: Data input register + fields: + - name: DIN + description: Input data word + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: Data output register + fields: + - name: DOUT + description: Output data word + bit_offset: 0 + bit_size: 32 +fieldset/ICR: + description: Interrupt clear register + fields: + - name: CCF + description: Computation complete flag clear + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag clear + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag clear + bit_offset: 2 + bit_size: 1 +fieldset/IER: + description: Interrupt enable register + fields: + - name: CCFIE + description: Computation complete flag interrupt enable + bit_offset: 0 + bit_size: 1 + - name: RWEIE + description: Read or write error interrupt enable + bit_offset: 1 + bit_size: 1 + - name: KEIE + description: Key error interrupt enable + bit_offset: 2 + bit_size: 1 +fieldset/ISR: + description: Interrupt status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag + bit_offset: 2 + bit_size: 1 +fieldset/IVR: + description: Initialization vector register + fields: + - name: IVI + description: Initialization vector input + bit_offset: 0 + bit_size: 32 +fieldset/KEYR: + description: Key register + fields: + - name: KEY + description: Cryptographic key + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: Status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: Read error flag + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: Write error flag + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy flag + bit_offset: 3 + bit_size: 1 + - name: KEYVALID + description: Key valid flag + bit_offset: 7 + bit_size: 1 +fieldset/SUSPR: + description: Suspend register + fields: + - name: SUSP + description: AES suspend + bit_offset: 0 + bit_size: 32 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: Encryption + value: 0 + - name: Mode2 + description: Key derivation (or key preparation for ECB/CBC decryption) + value: 1 + - name: Mode3 + description: Decryption + value: 2 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 From ccb0f18f5be6f15cd8dab2e4e1890b5252b62948 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:33:11 +0800 Subject: [PATCH 4/6] tailoring from aes_v3a to aes_v3b --- data/registers/aes_v3b.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml index bbe75a7..32a85c0 100644 --- a/data/registers/aes_v3b.yaml +++ b/data/registers/aes_v3b.yaml @@ -129,10 +129,6 @@ fieldset/DOUTR: fieldset/ICR: description: Interrupt clear register fields: - - name: CCF - description: Computation complete flag clear - bit_offset: 0 - bit_size: 1 - name: RWEIF description: Read or write error interrupt flag clear bit_offset: 1 From 12810e94550facbe78b2c7afa019e6fca7706df3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:46:25 +0800 Subject: [PATCH 5/6] add aes_v3b to chips.rs --- stm32-data-gen/src/chips.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 20b5520..a1270f2 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -155,6 +155,7 @@ impl PeriMatcher { ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), ("STM32U5.*:AES:.*", ("aes", "v3a", "AES")), + ("STM32(H5|WBA).*:AES:.*", ("aes", "v3b", "AES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 25ae37ec2220920004e63c28cf0f48ef181695e4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 18:37:31 +0800 Subject: [PATCH 6/6] recreate transform file and apply transform --- data/registers/aes_v3a.yaml | 76 +++++++++---------------------------- data/registers/aes_v3b.yaml | 76 +++++++++---------------------------- transforms/AES.yaml | 19 ++++++++++ 3 files changed, 55 insertions(+), 116 deletions(-) create mode 100644 transforms/AES.yaml diff --git a/data/registers/aes_v3a.yaml b/data/registers/aes_v3a.yaml index bbe75a7..9dd3cad 100644 --- a/data/registers/aes_v3a.yaml +++ b/data/registers/aes_v3a.yaml @@ -12,11 +12,9 @@ block/AES: - name: DINR description: Data input register byte_offset: 8 - fieldset: DINR - name: DOUTR description: Data output register byte_offset: 12 - fieldset: DOUTR - name: KEYR description: Key register array: @@ -30,21 +28,18 @@ block/AES: - 40 - 44 byte_offset: 16 - fieldset: KEYR - name: IVR description: Initialization vector register array: len: 4 stride: 4 byte_offset: 32 - fieldset: IVR - name: SUSPR description: Suspend register array: len: 8 stride: 4 byte_offset: 64 - fieldset: SUSPR - name: IER description: interrupt enable register byte_offset: 768 @@ -112,20 +107,6 @@ fieldset/CR: description: AES peripheral software reset bit_offset: 31 bit_size: 1 -fieldset/DINR: - description: Data input register - fields: - - name: DIN - description: Input data word - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: Data output register - fields: - - name: DOUT - description: Output data word - bit_offset: 0 - bit_size: 32 fieldset/ICR: description: Interrupt clear register fields: @@ -171,20 +152,6 @@ fieldset/ISR: description: Key error interrupt flag bit_offset: 2 bit_size: 1 -fieldset/IVR: - description: Initialization vector register - fields: - - name: IVI - description: Initialization vector input - bit_offset: 0 - bit_size: 32 -fieldset/KEYR: - description: Key register - fields: - - name: KEY - description: Cryptographic key - bit_offset: 0 - bit_size: 32 fieldset/SR: description: Status register fields: @@ -208,13 +175,24 @@ fieldset/SR: description: Key valid flag bit_offset: 7 bit_size: 1 -fieldset/SUSPR: - description: Suspend register - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 enum/DATATYPE: bit_size: 2 variants: @@ -257,21 +235,3 @@ enum/MODE: - name: Mode3 description: Decryption value: 2 -enum/CHMOD: - bit_size: 3 - variants: - - name: ECB - description: Electronic codebook - value: 0 - - name: CBC - description: Cipher-block chaining - value: 1 - - name: CTR - description: Counter mode - value: 2 - - name: GCM_GMAC - description: Galois counter mode and Galois message authentication code - value: 3 - - name: CCM - description: Counter with CBC-MAC - value: 4 diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml index 32a85c0..0ef8b12 100644 --- a/data/registers/aes_v3b.yaml +++ b/data/registers/aes_v3b.yaml @@ -12,11 +12,9 @@ block/AES: - name: DINR description: Data input register byte_offset: 8 - fieldset: DINR - name: DOUTR description: Data output register byte_offset: 12 - fieldset: DOUTR - name: KEYR description: Key register array: @@ -30,21 +28,18 @@ block/AES: - 40 - 44 byte_offset: 16 - fieldset: KEYR - name: IVR description: Initialization vector register array: len: 4 stride: 4 byte_offset: 32 - fieldset: IVR - name: SUSPR description: Suspend register array: len: 8 stride: 4 byte_offset: 64 - fieldset: SUSPR - name: IER description: interrupt enable register byte_offset: 768 @@ -112,20 +107,6 @@ fieldset/CR: description: AES peripheral software reset bit_offset: 31 bit_size: 1 -fieldset/DINR: - description: Data input register - fields: - - name: DIN - description: Input data word - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: Data output register - fields: - - name: DOUT - description: Output data word - bit_offset: 0 - bit_size: 32 fieldset/ICR: description: Interrupt clear register fields: @@ -167,20 +148,6 @@ fieldset/ISR: description: Key error interrupt flag bit_offset: 2 bit_size: 1 -fieldset/IVR: - description: Initialization vector register - fields: - - name: IVI - description: Initialization vector input - bit_offset: 0 - bit_size: 32 -fieldset/KEYR: - description: Key register - fields: - - name: KEY - description: Cryptographic key - bit_offset: 0 - bit_size: 32 fieldset/SR: description: Status register fields: @@ -204,13 +171,24 @@ fieldset/SR: description: Key valid flag bit_offset: 7 bit_size: 1 -fieldset/SUSPR: - description: Suspend register - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 enum/DATATYPE: bit_size: 2 variants: @@ -253,21 +231,3 @@ enum/MODE: - name: Mode3 description: Decryption value: 2 -enum/CHMOD: - bit_size: 3 - variants: - - name: ECB - description: Electronic codebook - value: 0 - - name: CBC - description: Cipher-block chaining - value: 1 - - name: CTR - description: Counter mode - value: 2 - - name: GCM_GMAC - description: Galois counter mode and Galois message authentication code - value: 3 - - name: CCM - description: Counter with CBC-MAC - value: 4 diff --git a/transforms/AES.yaml b/transforms/AES.yaml new file mode 100644 index 0000000..b8a13c8 --- /dev/null +++ b/transforms/AES.yaml @@ -0,0 +1,19 @@ +transforms: + - !DeleteFieldsets + from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$ + + - !MakeRegisterArray + blocks: AES + from: ^(IVR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: AES + allow_cursed: true + from: ^(KEYR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: AES + from: ^(SUSP)\d(R)$ + to: $1$2