diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 34749b4..91a0d03 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -1,4 +1,4 @@ ---- + block/RCC: description: Reset and clock control items: @@ -301,57 +301,46 @@ fieldset/AHB1ENR: description: DMA1 Clock Enable bit_offset: 0 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: DMA2EN description: DMA2 Clock Enable bit_offset: 1 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: ADC12EN description: ADC1/2 Peripheral Clocks Enable bit_offset: 5 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: ETH1MACEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: ETH1TXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: ETH1RXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: USB2OTGHSULPIEN description: " Enable USB_PHY2 clocks " bit_offset: 18 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: USB1OTGEN description: USB1OTG Peripheral Clocks Enable bit_offset: 25 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: USB1ULPIEN description: USB_PHY1 Clocks Enable bit_offset: 26 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: USB2OTGEN description: USB2OTG Peripheral Clocks Enable bit_offset: 27 bit_size: 1 - enum: AHB1ENR_DMA1EN - name: USB2ULPIEN description: USB_PHY2 Clocks Enable bit_offset: 28 bit_size: 1 - enum: AHB1ENR_DMA1EN fieldset/AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: @@ -359,52 +348,42 @@ fieldset/AHB1LPENR: description: DMA1 Clock Enable During CSleep Mode bit_offset: 0 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: DMA2LPEN description: DMA2 Clock Enable During CSleep Mode bit_offset: 1 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: ADC12LPEN description: ADC1/2 Peripheral Clocks Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: ETH1MACLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: ETH1TXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: ETH1RXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: USB1OTGLPEN description: USB1OTG peripheral clock enable during CSleep mode bit_offset: 25 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: USB1OTGHSULPILPEN description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: USB2OTGLPEN description: USB2OTG peripheral clock enable during CSleep mode bit_offset: 27 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - name: USB2OTGHSULPILPEN description: USB_PHY2 clocks enable during CSleep mode bit_offset: 28 bit_size: 1 - enum: AHB1LPENR_DMA1LPEN fieldset/AHB1RSTR: description: RCC AHB1 Peripheral Reset Register fields: @@ -412,32 +391,26 @@ fieldset/AHB1RSTR: description: DMA1 block reset bit_offset: 0 bit_size: 1 - enum: DMA1RST - name: DMA2RST description: DMA2 block reset bit_offset: 1 bit_size: 1 - enum: DMA1RST - name: ADC12RST description: ADC1&2 block reset bit_offset: 5 bit_size: 1 - enum: DMA1RST - name: ETH1MACRST description: ETH1MAC block reset bit_offset: 15 bit_size: 1 - enum: DMA1RST - name: USB1OTGRST description: USB1OTG block reset bit_offset: 25 bit_size: 1 - enum: DMA1RST - name: USB2OTGRST description: USB2OTG block reset bit_offset: 27 bit_size: 1 - enum: DMA1RST fieldset/AHB2ENR: description: RCC AHB2 Clock Register fields: @@ -445,42 +418,34 @@ fieldset/AHB2ENR: description: DCMI peripheral clock bit_offset: 0 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: CRYPTEN description: CRYPT peripheral clock enable bit_offset: 4 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: HASHEN description: HASH peripheral clock enable bit_offset: 5 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: RNGEN description: RNG peripheral clocks enable bit_offset: 6 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: SDMMC2EN description: SDMMC2 and SDMMC2 delay clock enable bit_offset: 9 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: SRAM1EN description: SRAM1 block enable bit_offset: 29 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: SRAM2EN description: SRAM2 block enable bit_offset: 30 bit_size: 1 - enum: AHB2ENR_DCMIEN - name: SRAM3EN description: SRAM3 block enable bit_offset: 31 bit_size: 1 - enum: AHB2ENR_DCMIEN fieldset/AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: @@ -488,42 +453,34 @@ fieldset/AHB2LPENR: description: DCMI peripheral clock enable during csleep mode bit_offset: 0 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: CRYPTLPEN description: CRYPT peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: HASHLPEN description: HASH peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: RNGLPEN description: RNG peripheral clock enable during CSleep mode bit_offset: 6 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: SDMMC2LPEN description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode bit_offset: 9 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: SRAM1LPEN description: SRAM1 Clock Enable During CSleep Mode bit_offset: 29 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: SRAM2LPEN description: SRAM2 Clock Enable During CSleep Mode bit_offset: 30 bit_size: 1 - enum: AHB2LPENR_DCMILPEN - name: SRAM3LPEN description: SRAM3 Clock Enable During CSleep Mode bit_offset: 31 bit_size: 1 - enum: AHB2LPENR_DCMILPEN fieldset/AHB2RSTR: description: RCC AHB2 Peripheral Reset Register fields: @@ -531,27 +488,22 @@ fieldset/AHB2RSTR: description: CAMITF block reset bit_offset: 0 bit_size: 1 - enum: CAMITFRST - name: CRYPTRST description: Cryptography block reset bit_offset: 4 bit_size: 1 - enum: CAMITFRST - name: HASHRST description: Hash block reset bit_offset: 5 bit_size: 1 - enum: CAMITFRST - name: RNGRST description: Random Number Generator block reset bit_offset: 6 bit_size: 1 - enum: CAMITFRST - name: SDMMC2RST description: SDMMC2 and SDMMC2 Delay block reset bit_offset: 9 bit_size: 1 - enum: CAMITFRST fieldset/AHB3ENR: description: RCC AHB3 Clock Register fields: @@ -559,32 +511,26 @@ fieldset/AHB3ENR: description: MDMA Peripheral Clock Enable bit_offset: 0 bit_size: 1 - enum: AHB3ENR_MDMAEN - name: DMA2DEN description: DMA2D Peripheral Clock Enable bit_offset: 4 bit_size: 1 - enum: AHB3ENR_MDMAEN - name: JPGDECEN description: JPGDEC Peripheral Clock Enable bit_offset: 5 bit_size: 1 - enum: AHB3ENR_MDMAEN - name: FMCEN description: FMC Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - enum: AHB3ENR_MDMAEN - name: QSPIEN description: QUADSPI and QUADSPI Delay Clock Enable bit_offset: 14 bit_size: 1 - enum: AHB3ENR_MDMAEN - name: SDMMC1EN description: SDMMC1 and SDMMC1 Delay Clock Enable bit_offset: 16 bit_size: 1 - enum: AHB3ENR_MDMAEN fieldset/AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: @@ -592,57 +538,46 @@ fieldset/AHB3LPENR: description: MDMA Clock Enable During CSleep Mode bit_offset: 0 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: DMA2DLPEN description: DMA2D Clock Enable During CSleep Mode bit_offset: 4 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: JPGDECLPEN description: JPGDEC Clock Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: FLASHLPEN description: FLITF Clock Enable During CSleep Mode bit_offset: 8 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: FMCLPEN description: FMC Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: QSPILPEN description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: SDMMC1LPEN description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: D1DTCM1LPEN description: D1DTCM1 Block Clock Enable During CSleep mode bit_offset: 28 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: DTCM2LPEN description: D1 DTCM2 Block Clock Enable During CSleep mode bit_offset: 29 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: ITCMLPEN description: D1ITCM Block Clock Enable During CSleep mode bit_offset: 30 bit_size: 1 - enum: AHB3LPENR_MDMALPEN - name: AXISRAMLPEN description: AXISRAM Block Clock Enable During CSleep mode bit_offset: 31 bit_size: 1 - enum: AHB3LPENR_MDMALPEN fieldset/AHB3RSTR: description: RCC AHB3 Reset Register fields: @@ -650,37 +585,30 @@ fieldset/AHB3RSTR: description: MDMA block reset bit_offset: 0 bit_size: 1 - enum: MDMARST - name: DMA2DRST description: DMA2D block reset bit_offset: 4 bit_size: 1 - enum: MDMARST - name: JPGDECRST description: JPGDEC block reset bit_offset: 5 bit_size: 1 - enum: MDMARST - name: FMCRST description: FMC block reset bit_offset: 12 bit_size: 1 - enum: MDMARST - name: QSPIRST description: QUADSPI and QUADSPI delay block reset bit_offset: 14 bit_size: 1 - enum: MDMARST - name: SDMMC1RST description: SDMMC1 and SDMMC1 delay block reset bit_offset: 16 bit_size: 1 - enum: MDMARST - name: CPURST description: CPU reset bit_offset: 31 bit_size: 1 - enum: MDMARST fieldset/AHB4ENR: description: RCC AHB4 Clock Register fields: @@ -688,82 +616,66 @@ fieldset/AHB4ENR: description: 0GPIO peripheral clock enable bit_offset: 0 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOBEN description: 0GPIO peripheral clock enable bit_offset: 1 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOCEN description: 0GPIO peripheral clock enable bit_offset: 2 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIODEN description: 0GPIO peripheral clock enable bit_offset: 3 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOEEN description: 0GPIO peripheral clock enable bit_offset: 4 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOFEN description: 0GPIO peripheral clock enable bit_offset: 5 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOGEN description: 0GPIO peripheral clock enable bit_offset: 6 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOHEN description: 0GPIO peripheral clock enable bit_offset: 7 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOIEN description: 0GPIO peripheral clock enable bit_offset: 8 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOJEN description: 0GPIO peripheral clock enable bit_offset: 9 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: GPIOKEN description: 0GPIO peripheral clock enable bit_offset: 10 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: CRCEN description: CRC peripheral clock enable bit_offset: 19 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: BDMAEN description: BDMA and DMAMUX2 Clock Enable bit_offset: 21 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: ADC3EN description: ADC3 Peripheral Clocks Enable bit_offset: 24 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: HSEMEN description: HSEM peripheral clock enable bit_offset: 25 bit_size: 1 - enum: AHB4ENR_GPIOAEN - name: BKPRAMEN description: Backup RAM Clock Enable bit_offset: 28 bit_size: 1 - enum: AHB4ENR_GPIOAEN fieldset/AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: @@ -771,82 +683,66 @@ fieldset/AHB4LPENR: description: GPIO peripheral clock enable during CSleep mode bit_offset: 0 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOBLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOCLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 2 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIODLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 3 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOELPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOFLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOGLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 6 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOHLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 7 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOILPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 8 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOJLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 9 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: GPIOKLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 10 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: CRCLPEN description: CRC peripheral clock enable during CSleep mode bit_offset: 19 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: BDMALPEN description: BDMA Clock Enable During CSleep Mode bit_offset: 21 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: ADC3LPEN description: ADC3 Peripheral Clocks Enable During CSleep Mode bit_offset: 24 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: BKPRAMLPEN description: Backup RAM Clock Enable During CSleep Mode bit_offset: 28 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - name: SRAM4LPEN description: SRAM4 Clock Enable During CSleep Mode bit_offset: 29 bit_size: 1 - enum: AHB4LPENR_GPIOALPEN fieldset/AHB4RSTR: description: RCC AHB4 Peripheral Reset Register fields: @@ -854,77 +750,62 @@ fieldset/AHB4RSTR: description: GPIO block reset bit_offset: 0 bit_size: 1 - enum: GPIOARST - name: GPIOBRST description: GPIO block reset bit_offset: 1 bit_size: 1 - enum: GPIOARST - name: GPIOCRST description: GPIO block reset bit_offset: 2 bit_size: 1 - enum: GPIOARST - name: GPIODRST description: GPIO block reset bit_offset: 3 bit_size: 1 - enum: GPIOARST - name: GPIOERST description: GPIO block reset bit_offset: 4 bit_size: 1 - enum: GPIOARST - name: GPIOFRST description: GPIO block reset bit_offset: 5 bit_size: 1 - enum: GPIOARST - name: GPIOGRST description: GPIO block reset bit_offset: 6 bit_size: 1 - enum: GPIOARST - name: GPIOHRST description: GPIO block reset bit_offset: 7 bit_size: 1 - enum: GPIOARST - name: GPIOIRST description: GPIO block reset bit_offset: 8 bit_size: 1 - enum: GPIOARST - name: GPIOJRST description: GPIO block reset bit_offset: 9 bit_size: 1 - enum: GPIOARST - name: GPIOKRST description: GPIO block reset bit_offset: 10 bit_size: 1 - enum: GPIOARST - name: CRCRST description: CRC block reset bit_offset: 19 bit_size: 1 - enum: GPIOARST - name: BDMARST description: BDMA block reset bit_offset: 21 bit_size: 1 - enum: GPIOARST - name: ADC3RST description: ADC3 block reset bit_offset: 24 bit_size: 1 - enum: GPIOARST - name: HSEMRST description: HSEM block reset bit_offset: 25 bit_size: 1 - enum: GPIOARST fieldset/APB1HENR: description: RCC APB1 Clock Register fields: @@ -932,27 +813,22 @@ fieldset/APB1HENR: description: Clock Recovery System peripheral clock enable bit_offset: 1 bit_size: 1 - enum: APB1HENR_CRSEN - name: SWPEN description: SWPMI Peripheral Clocks Enable bit_offset: 2 bit_size: 1 - enum: APB1HENR_CRSEN - name: OPAMPEN description: OPAMP peripheral clock enable bit_offset: 4 bit_size: 1 - enum: APB1HENR_CRSEN - name: MDIOSEN description: MDIOS peripheral clock enable bit_offset: 5 bit_size: 1 - enum: APB1HENR_CRSEN - name: FDCANEN description: FDCAN Peripheral Clocks Enable bit_offset: 8 bit_size: 1 - enum: APB1HENR_CRSEN fieldset/APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: @@ -960,27 +836,22 @@ fieldset/APB1HLPENR: description: Clock Recovery System peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: APB1HLPENR_CRSLPEN - name: SWPLPEN description: SWPMI Peripheral Clocks Enable During CSleep Mode bit_offset: 2 bit_size: 1 - enum: APB1HLPENR_CRSLPEN - name: OPAMPLPEN description: OPAMP peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: APB1HLPENR_CRSLPEN - name: MDIOSLPEN description: MDIOS peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: APB1HLPENR_CRSLPEN - name: FDCANLPEN description: FDCAN Peripheral Clocks Enable During CSleep Mode bit_offset: 8 bit_size: 1 - enum: APB1HLPENR_CRSLPEN fieldset/APB1HRSTR: description: RCC APB1 Peripheral Reset Register fields: @@ -988,27 +859,22 @@ fieldset/APB1HRSTR: description: Clock Recovery System reset bit_offset: 1 bit_size: 1 - enum: CRSRST - name: SWPRST description: SWPMI block reset bit_offset: 2 bit_size: 1 - enum: CRSRST - name: OPAMPRST description: OPAMP block reset bit_offset: 4 bit_size: 1 - enum: CRSRST - name: MDIOSRST description: MDIOS block reset bit_offset: 5 bit_size: 1 - enum: CRSRST - name: FDCANRST description: FDCAN block reset bit_offset: 8 bit_size: 1 - enum: CRSRST fieldset/APB1LENR: description: RCC APB1 Clock Register fields: @@ -1016,122 +882,98 @@ fieldset/APB1LENR: description: TIM peripheral clock enable bit_offset: 0 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM3EN description: TIM peripheral clock enable bit_offset: 1 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM4EN description: TIM peripheral clock enable bit_offset: 2 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM5EN description: TIM peripheral clock enable bit_offset: 3 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM6EN description: TIM peripheral clock enable bit_offset: 4 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM7EN description: TIM peripheral clock enable bit_offset: 5 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM12EN description: TIM peripheral clock enable bit_offset: 6 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM13EN description: TIM peripheral clock enable bit_offset: 7 bit_size: 1 - enum: APB1LENR_TIM2EN - name: TIM14EN description: TIM peripheral clock enable bit_offset: 8 bit_size: 1 - enum: APB1LENR_TIM2EN - name: LPTIM1EN description: LPTIM1 Peripheral Clocks Enable bit_offset: 9 bit_size: 1 - enum: APB1LENR_TIM2EN - name: SPI2EN description: SPI2 Peripheral Clocks Enable bit_offset: 14 bit_size: 1 - enum: APB1LENR_TIM2EN - name: SPI3EN description: SPI3 Peripheral Clocks Enable bit_offset: 15 bit_size: 1 - enum: APB1LENR_TIM2EN - name: SPDIFRXEN description: SPDIFRX Peripheral Clocks Enable bit_offset: 16 bit_size: 1 - enum: APB1LENR_TIM2EN - name: USART2EN description: USART2 Peripheral Clocks Enable bit_offset: 17 bit_size: 1 - enum: APB1LENR_TIM2EN - name: USART3EN description: USART3 Peripheral Clocks Enable bit_offset: 18 bit_size: 1 - enum: APB1LENR_TIM2EN - name: UART4EN description: UART4 Peripheral Clocks Enable bit_offset: 19 bit_size: 1 - enum: APB1LENR_TIM2EN - name: UART5EN description: UART5 Peripheral Clocks Enable bit_offset: 20 bit_size: 1 - enum: APB1LENR_TIM2EN - name: I2C1EN description: I2C1 Peripheral Clocks Enable bit_offset: 21 bit_size: 1 - enum: APB1LENR_TIM2EN - name: I2C2EN description: I2C2 Peripheral Clocks Enable bit_offset: 22 bit_size: 1 - enum: APB1LENR_TIM2EN - name: I2C3EN description: I2C3 Peripheral Clocks Enable bit_offset: 23 bit_size: 1 - enum: APB1LENR_TIM2EN - name: CECEN description: HDMI-CEC peripheral clock enable bit_offset: 27 bit_size: 1 - enum: APB1LENR_TIM2EN - name: DAC12EN description: DAC1&2 peripheral clock enable bit_offset: 29 bit_size: 1 - enum: APB1LENR_TIM2EN - name: UART7EN description: UART7 Peripheral Clocks Enable bit_offset: 30 bit_size: 1 - enum: APB1LENR_TIM2EN - name: UART8EN description: UART8 Peripheral Clocks Enable bit_offset: 31 bit_size: 1 - enum: APB1LENR_TIM2EN fieldset/APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: @@ -1139,122 +981,98 @@ fieldset/APB1LLPENR: description: TIM2 peripheral clock enable during CSleep mode bit_offset: 0 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM3LPEN description: TIM3 peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM4LPEN description: TIM4 peripheral clock enable during CSleep mode bit_offset: 2 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM5LPEN description: TIM5 peripheral clock enable during CSleep mode bit_offset: 3 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM6LPEN description: TIM6 peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM7LPEN description: TIM7 peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM12LPEN description: TIM12 peripheral clock enable during CSleep mode bit_offset: 6 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM13LPEN description: TIM13 peripheral clock enable during CSleep mode bit_offset: 7 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: TIM14LPEN description: TIM14 peripheral clock enable during CSleep mode bit_offset: 8 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: LPTIM1LPEN description: LPTIM1 Peripheral Clocks Enable During CSleep Mode bit_offset: 9 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: SPI2LPEN description: SPI2 Peripheral Clocks Enable During CSleep Mode bit_offset: 14 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: SPI3LPEN description: SPI3 Peripheral Clocks Enable During CSleep Mode bit_offset: 15 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: SPDIFRXLPEN description: SPDIFRX Peripheral Clocks Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: USART2LPEN description: USART2 Peripheral Clocks Enable During CSleep Mode bit_offset: 17 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: USART3LPEN description: USART3 Peripheral Clocks Enable During CSleep Mode bit_offset: 18 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: UART4LPEN description: UART4 Peripheral Clocks Enable During CSleep Mode bit_offset: 19 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: UART5LPEN description: UART5 Peripheral Clocks Enable During CSleep Mode bit_offset: 20 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: I2C1LPEN description: I2C1 Peripheral Clocks Enable During CSleep Mode bit_offset: 21 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: I2C2LPEN description: I2C2 Peripheral Clocks Enable During CSleep Mode bit_offset: 22 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: I2C3LPEN description: I2C3 Peripheral Clocks Enable During CSleep Mode bit_offset: 23 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: CECLPEN description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode bit_offset: 27 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: DAC12LPEN description: DAC1/2 peripheral clock enable during CSleep mode bit_offset: 29 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: UART7LPEN description: UART7 Peripheral Clocks Enable During CSleep Mode bit_offset: 30 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - name: UART8LPEN description: UART8 Peripheral Clocks Enable During CSleep Mode bit_offset: 31 bit_size: 1 - enum: APB1LLPENR_TIM2LPEN fieldset/APB1LRSTR: description: RCC APB1 Peripheral Reset Register fields: @@ -1262,122 +1080,98 @@ fieldset/APB1LRSTR: description: TIM block reset bit_offset: 0 bit_size: 1 - enum: TIM2RST - name: TIM3RST description: TIM block reset bit_offset: 1 bit_size: 1 - enum: TIM2RST - name: TIM4RST description: TIM block reset bit_offset: 2 bit_size: 1 - enum: TIM2RST - name: TIM5RST description: TIM block reset bit_offset: 3 bit_size: 1 - enum: TIM2RST - name: TIM6RST description: TIM block reset bit_offset: 4 bit_size: 1 - enum: TIM2RST - name: TIM7RST description: TIM block reset bit_offset: 5 bit_size: 1 - enum: TIM2RST - name: TIM12RST description: TIM block reset bit_offset: 6 bit_size: 1 - enum: TIM2RST - name: TIM13RST description: TIM block reset bit_offset: 7 bit_size: 1 - enum: TIM2RST - name: TIM14RST description: TIM block reset bit_offset: 8 bit_size: 1 - enum: TIM2RST - name: LPTIM1RST description: TIM block reset bit_offset: 9 bit_size: 1 - enum: TIM2RST - name: SPI2RST description: SPI2 block reset bit_offset: 14 bit_size: 1 - enum: TIM2RST - name: SPI3RST description: SPI3 block reset bit_offset: 15 bit_size: 1 - enum: TIM2RST - name: SPDIFRXRST description: SPDIFRX block reset bit_offset: 16 bit_size: 1 - enum: TIM2RST - name: USART2RST description: USART2 block reset bit_offset: 17 bit_size: 1 - enum: TIM2RST - name: USART3RST description: USART3 block reset bit_offset: 18 bit_size: 1 - enum: TIM2RST - name: UART4RST description: UART4 block reset bit_offset: 19 bit_size: 1 - enum: TIM2RST - name: UART5RST description: UART5 block reset bit_offset: 20 bit_size: 1 - enum: TIM2RST - name: I2C1RST description: I2C1 block reset bit_offset: 21 bit_size: 1 - enum: TIM2RST - name: I2C2RST description: I2C2 block reset bit_offset: 22 bit_size: 1 - enum: TIM2RST - name: I2C3RST description: I2C3 block reset bit_offset: 23 bit_size: 1 - enum: TIM2RST - name: CECRST description: HDMI-CEC block reset bit_offset: 27 bit_size: 1 - enum: TIM2RST - name: DAC12RST description: DAC1 and 2 Blocks Reset bit_offset: 29 bit_size: 1 - enum: TIM2RST - name: UART7RST description: UART7 block reset bit_offset: 30 bit_size: 1 - enum: TIM2RST - name: UART8RST description: UART8 block reset bit_offset: 31 bit_size: 1 - enum: TIM2RST fieldset/APB2ENR: description: RCC APB2 Clock Register fields: @@ -1385,77 +1179,62 @@ fieldset/APB2ENR: description: TIM1 peripheral clock enable bit_offset: 0 bit_size: 1 - enum: APB2ENR_TIM1EN - name: TIM8EN description: TIM8 peripheral clock enable bit_offset: 1 bit_size: 1 - enum: APB2ENR_TIM1EN - name: USART1EN description: USART1 Peripheral Clocks Enable bit_offset: 4 bit_size: 1 - enum: APB2ENR_TIM1EN - name: USART6EN description: USART6 Peripheral Clocks Enable bit_offset: 5 bit_size: 1 - enum: APB2ENR_TIM1EN - name: SPI1EN description: SPI1 Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - enum: APB2ENR_TIM1EN - name: SPI4EN description: SPI4 Peripheral Clocks Enable bit_offset: 13 bit_size: 1 - enum: APB2ENR_TIM1EN - name: TIM15EN description: TIM15 peripheral clock enable bit_offset: 16 bit_size: 1 - enum: APB2ENR_TIM1EN - name: TIM16EN description: TIM16 peripheral clock enable bit_offset: 17 bit_size: 1 - enum: APB2ENR_TIM1EN - name: TIM17EN description: TIM17 peripheral clock enable bit_offset: 18 bit_size: 1 - enum: APB2ENR_TIM1EN - name: SPI5EN description: SPI5 Peripheral Clocks Enable bit_offset: 20 bit_size: 1 - enum: APB2ENR_TIM1EN - name: SAI1EN description: SAI1 Peripheral Clocks Enable bit_offset: 22 bit_size: 1 - enum: APB2ENR_TIM1EN - name: SAI2EN description: SAI2 Peripheral Clocks Enable bit_offset: 23 bit_size: 1 - enum: APB2ENR_TIM1EN - name: SAI3EN description: SAI3 Peripheral Clocks Enable bit_offset: 24 bit_size: 1 - enum: APB2ENR_TIM1EN - name: DFSDM1EN description: DFSDM1 Peripheral Clocks Enable bit_offset: 28 bit_size: 1 - enum: APB2ENR_TIM1EN - name: HRTIMEN description: HRTIM peripheral clock enable bit_offset: 29 bit_size: 1 - enum: APB2ENR_TIM1EN fieldset/APB2LPENR: description: RCC APB2 Sleep Clock Register fields: @@ -1463,77 +1242,62 @@ fieldset/APB2LPENR: description: TIM1 peripheral clock enable during CSleep mode bit_offset: 0 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: TIM8LPEN description: TIM8 peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: USART1LPEN description: USART1 Peripheral Clocks Enable During CSleep Mode bit_offset: 4 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: USART6LPEN description: USART6 Peripheral Clocks Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: SPI1LPEN description: SPI1 Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: SPI4LPEN description: SPI4 Peripheral Clocks Enable During CSleep Mode bit_offset: 13 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: TIM15LPEN description: TIM15 peripheral clock enable during CSleep mode bit_offset: 16 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: TIM16LPEN description: TIM16 peripheral clock enable during CSleep mode bit_offset: 17 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: TIM17LPEN description: TIM17 peripheral clock enable during CSleep mode bit_offset: 18 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: SPI5LPEN description: SPI5 Peripheral Clocks Enable During CSleep Mode bit_offset: 20 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: SAI1LPEN description: SAI1 Peripheral Clocks Enable During CSleep Mode bit_offset: 22 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: SAI2LPEN description: SAI2 Peripheral Clocks Enable During CSleep Mode bit_offset: 23 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: SAI3LPEN description: SAI3 Peripheral Clocks Enable During CSleep Mode bit_offset: 24 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: DFSDM1LPEN description: DFSDM1 Peripheral Clocks Enable During CSleep Mode bit_offset: 28 bit_size: 1 - enum: APB2LPENR_TIM1LPEN - name: HRTIMLPEN description: HRTIM peripheral clock enable during CSleep mode bit_offset: 29 bit_size: 1 - enum: APB2LPENR_TIM1LPEN fieldset/APB2RSTR: description: RCC APB2 Peripheral Reset Register fields: @@ -1541,77 +1305,62 @@ fieldset/APB2RSTR: description: TIM1 block reset bit_offset: 0 bit_size: 1 - enum: TIM1RST - name: TIM8RST description: TIM8 block reset bit_offset: 1 bit_size: 1 - enum: TIM1RST - name: USART1RST description: USART1 block reset bit_offset: 4 bit_size: 1 - enum: TIM1RST - name: USART6RST description: USART6 block reset bit_offset: 5 bit_size: 1 - enum: TIM1RST - name: SPI1RST description: SPI1 block reset bit_offset: 12 bit_size: 1 - enum: TIM1RST - name: SPI4RST description: SPI4 block reset bit_offset: 13 bit_size: 1 - enum: TIM1RST - name: TIM15RST description: TIM15 block reset bit_offset: 16 bit_size: 1 - enum: TIM1RST - name: TIM16RST description: TIM16 block reset bit_offset: 17 bit_size: 1 - enum: TIM1RST - name: TIM17RST description: TIM17 block reset bit_offset: 18 bit_size: 1 - enum: TIM1RST - name: SPI5RST description: SPI5 block reset bit_offset: 20 bit_size: 1 - enum: TIM1RST - name: SAI1RST description: SAI1 block reset bit_offset: 22 bit_size: 1 - enum: TIM1RST - name: SAI2RST description: SAI2 block reset bit_offset: 23 bit_size: 1 - enum: TIM1RST - name: SAI3RST description: SAI3 block reset bit_offset: 24 bit_size: 1 - enum: TIM1RST - name: DFSDM1RST description: DFSDM1 block reset bit_offset: 28 bit_size: 1 - enum: TIM1RST - name: HRTIMRST description: HRTIM block reset bit_offset: 29 bit_size: 1 - enum: TIM1RST fieldset/APB3ENR: description: RCC APB3 Clock Register fields: @@ -1619,12 +1368,10 @@ fieldset/APB3ENR: description: LTDC peripheral clock enable bit_offset: 3 bit_size: 1 - enum: APB3ENR_LTDCEN - name: WWDG1EN description: WWDG1 Clock Enable bit_offset: 6 bit_size: 1 - enum: APB3ENR_LTDCEN fieldset/APB3LPENR: description: RCC APB3 Sleep Clock Register fields: @@ -1632,12 +1379,10 @@ fieldset/APB3LPENR: description: LTDC peripheral clock enable during CSleep mode bit_offset: 3 bit_size: 1 - enum: APB3LPENR_LTDCLPEN - name: WWDG1LPEN description: WWDG1 Clock Enable During CSleep Mode bit_offset: 6 bit_size: 1 - enum: APB3LPENR_LTDCLPEN fieldset/APB3RSTR: description: RCC APB3 Peripheral Reset Register fields: @@ -1645,7 +1390,6 @@ fieldset/APB3RSTR: description: LTDC block reset bit_offset: 3 bit_size: 1 - enum: LTDCRST fieldset/APB4ENR: description: RCC APB4 Clock Register fields: @@ -1653,62 +1397,50 @@ fieldset/APB4ENR: description: SYSCFG peripheral clock enable bit_offset: 1 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: LPUART1EN description: LPUART1 Peripheral Clocks Enable bit_offset: 3 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: SPI6EN description: SPI6 Peripheral Clocks Enable bit_offset: 5 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: I2C4EN description: I2C4 Peripheral Clocks Enable bit_offset: 7 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: LPTIM2EN description: LPTIM2 Peripheral Clocks Enable bit_offset: 9 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: LPTIM3EN description: LPTIM3 Peripheral Clocks Enable bit_offset: 10 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: LPTIM4EN description: LPTIM4 Peripheral Clocks Enable bit_offset: 11 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: LPTIM5EN description: LPTIM5 Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: COMP12EN description: COMP1/2 peripheral clock enable bit_offset: 14 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: VREFEN description: VREF peripheral clock enable bit_offset: 15 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: RTCAPBEN description: RTC APB Clock Enable bit_offset: 16 bit_size: 1 - enum: APB4ENR_SYSCFGEN - name: SAI4EN description: SAI4 Peripheral Clocks Enable bit_offset: 21 bit_size: 1 - enum: APB4ENR_SYSCFGEN fieldset/APB4LPENR: description: RCC APB4 Sleep Clock Register fields: @@ -1716,62 +1448,50 @@ fieldset/APB4LPENR: description: SYSCFG peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: LPUART1LPEN description: LPUART1 Peripheral Clocks Enable During CSleep Mode bit_offset: 3 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: SPI6LPEN description: SPI6 Peripheral Clocks Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: I2C4LPEN description: I2C4 Peripheral Clocks Enable During CSleep Mode bit_offset: 7 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: LPTIM2LPEN description: LPTIM2 Peripheral Clocks Enable During CSleep Mode bit_offset: 9 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: LPTIM3LPEN description: LPTIM3 Peripheral Clocks Enable During CSleep Mode bit_offset: 10 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: LPTIM4LPEN description: LPTIM4 Peripheral Clocks Enable During CSleep Mode bit_offset: 11 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: LPTIM5LPEN description: LPTIM5 Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: COMP12LPEN description: COMP1/2 peripheral clock enable during CSleep mode bit_offset: 14 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: VREFLPEN description: VREF peripheral clock enable during CSleep mode bit_offset: 15 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: RTCAPBLPEN description: RTC APB Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - name: SAI4LPEN description: SAI4 Peripheral Clocks Enable During CSleep Mode bit_offset: 21 bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN fieldset/APB4RSTR: description: RCC APB4 Peripheral Reset Register fields: @@ -1779,57 +1499,46 @@ fieldset/APB4RSTR: description: SYSCFG block reset bit_offset: 1 bit_size: 1 - enum: SYSCFGRST - name: LPUART1RST description: LPUART1 block reset bit_offset: 3 bit_size: 1 - enum: SYSCFGRST - name: SPI6RST description: SPI6 block reset bit_offset: 5 bit_size: 1 - enum: SYSCFGRST - name: I2C4RST description: I2C4 block reset bit_offset: 7 bit_size: 1 - enum: SYSCFGRST - name: LPTIM2RST description: LPTIM2 block reset bit_offset: 9 bit_size: 1 - enum: SYSCFGRST - name: LPTIM3RST description: LPTIM3 block reset bit_offset: 10 bit_size: 1 - enum: SYSCFGRST - name: LPTIM4RST description: LPTIM4 block reset bit_offset: 11 bit_size: 1 - enum: SYSCFGRST - name: LPTIM5RST description: LPTIM5 block reset bit_offset: 12 bit_size: 1 - enum: SYSCFGRST - name: COMP12RST description: COMP12 Blocks Reset bit_offset: 14 bit_size: 1 - enum: SYSCFGRST - name: VREFRST description: VREF block reset bit_offset: 15 bit_size: 1 - enum: SYSCFGRST - name: SAI4RST description: SAI4 block reset bit_offset: 21 bit_size: 1 - enum: SYSCFGRST fieldset/BDCR: description: RCC Backup Domain Control Register fields: @@ -1872,12 +1581,10 @@ fieldset/BDCR: description: RTC clock enable bit_offset: 15 bit_size: 1 - enum: RTCEN - name: BDRST description: VSwitch domain software reset bit_offset: 16 bit_size: 1 - enum: BDRST fieldset/C1_AHB1ENR: description: RCC AHB1 Clock Register fields: @@ -1885,52 +1592,42 @@ fieldset/C1_AHB1ENR: description: DMA1 Clock Enable bit_offset: 0 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: DMA2EN description: DMA2 Clock Enable bit_offset: 1 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: ADC12EN description: ADC1/2 Peripheral Clocks Enable bit_offset: 5 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: ETH1MACEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: ETH1TXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: ETH1RXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: USB1OTGEN description: USB1OTG Peripheral Clocks Enable bit_offset: 25 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: USB1ULPIEN description: USB_PHY1 Clocks Enable bit_offset: 26 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: USB2OTGEN description: USB2OTG Peripheral Clocks Enable bit_offset: 27 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - name: USB2ULPIEN description: USB_PHY2 Clocks Enable bit_offset: 28 bit_size: 1 - enum: C1_AHB1ENR_DMA1EN fieldset/C1_AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: @@ -1938,52 +1635,42 @@ fieldset/C1_AHB1LPENR: description: DMA1 Clock Enable During CSleep Mode bit_offset: 0 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: DMA2LPEN description: DMA2 Clock Enable During CSleep Mode bit_offset: 1 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: ADC12LPEN description: ADC1/2 Peripheral Clocks Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: ETH1MACLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: ETH1TXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: ETH1RXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: USB1OTGLPEN description: USB1OTG peripheral clock enable during CSleep mode bit_offset: 25 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: USB1ULPILPEN description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: USB2OTGLPEN description: USB2OTG peripheral clock enable during CSleep mode bit_offset: 27 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - name: USB2ULPILPEN description: USB_PHY2 clocks enable during CSleep mode bit_offset: 28 bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN fieldset/C1_AHB2ENR: description: RCC AHB2 Clock Register fields: @@ -1991,42 +1678,41 @@ fieldset/C1_AHB2ENR: description: DCMI peripheral clock bit_offset: 0 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - name: CRYPTEN description: CRYPT peripheral clock enable bit_offset: 4 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + - name: HASHEN description: HASH peripheral clock enable bit_offset: 5 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + - name: RNGEN description: RNG peripheral clocks enable bit_offset: 6 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + - name: SDMMC2EN description: SDMMC2 and SDMMC2 delay clock enable bit_offset: 9 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + - name: SRAM1EN description: SRAM1 block enable bit_offset: 29 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + - name: SRAM2EN description: SRAM2 block enable bit_offset: 30 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + - name: SRAM3EN description: SRAM3 block enable bit_offset: 31 bit_size: 1 - enum: C1_AHB2ENR_DCMIEN + fieldset/C1_AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: @@ -2034,42 +1720,42 @@ fieldset/C1_AHB2LPENR: description: DCMI peripheral clock enable during csleep mode bit_offset: 0 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: CRYPTLPEN description: CRYPT peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: HASHLPEN description: HASH peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: RNGLPEN description: RNG peripheral clock enable during CSleep mode bit_offset: 6 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: SDMMC2LPEN description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode bit_offset: 9 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: SRAM1LPEN description: SRAM1 Clock Enable During CSleep Mode bit_offset: 29 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: SRAM2LPEN description: SRAM2 Clock Enable During CSleep Mode bit_offset: 30 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + - name: SRAM3LPEN description: SRAM3 Clock Enable During CSleep Mode bit_offset: 31 bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN + fieldset/C1_AHB3ENR: description: RCC AHB3 Clock Register fields: @@ -2077,32 +1763,32 @@ fieldset/C1_AHB3ENR: description: MDMA Peripheral Clock Enable bit_offset: 0 bit_size: 1 - enum: C1_AHB3ENR_MDMAEN + - name: DMA2DEN description: DMA2D Peripheral Clock Enable bit_offset: 4 bit_size: 1 - enum: C1_AHB3ENR_MDMAEN + - name: JPGDECEN description: JPGDEC Peripheral Clock Enable bit_offset: 5 bit_size: 1 - enum: C1_AHB3ENR_MDMAEN + - name: FMCEN description: FMC Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - enum: C1_AHB3ENR_MDMAEN + - name: QSPIEN description: QUADSPI and QUADSPI Delay Clock Enable bit_offset: 14 bit_size: 1 - enum: C1_AHB3ENR_MDMAEN + - name: SDMMC1EN description: SDMMC1 and SDMMC1 Delay Clock Enable bit_offset: 16 bit_size: 1 - enum: C1_AHB3ENR_MDMAEN + fieldset/C1_AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: @@ -2110,17 +1796,17 @@ fieldset/C1_AHB3LPENR: description: MDMA Clock Enable During CSleep Mode bit_offset: 0 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: DMA2DLPEN description: DMA2D Clock Enable During CSleep Mode bit_offset: 4 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: JPGDECLPEN description: JPGDEC Clock Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: FLASHPREN description: Flash interface clock enable during csleep mode bit_offset: 8 @@ -2129,37 +1815,37 @@ fieldset/C1_AHB3LPENR: description: FMC Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: QSPILPEN description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: SDMMC1LPEN description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: D1DTCM1LPEN description: D1DTCM1 Block Clock Enable During CSleep mode bit_offset: 28 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: DTCM2LPEN description: D1 DTCM2 Block Clock Enable During CSleep mode bit_offset: 29 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: ITCMLPEN description: D1ITCM Block Clock Enable During CSleep mode bit_offset: 30 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + - name: AXISRAMLPEN description: AXISRAM Block Clock Enable During CSleep mode bit_offset: 31 bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN + fieldset/C1_AHB4ENR: description: RCC AHB4 Clock Register fields: @@ -2167,82 +1853,82 @@ fieldset/C1_AHB4ENR: description: 0GPIO peripheral clock enable bit_offset: 0 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOBEN description: 0GPIO peripheral clock enable bit_offset: 1 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOCEN description: 0GPIO peripheral clock enable bit_offset: 2 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIODEN description: 0GPIO peripheral clock enable bit_offset: 3 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOEEN description: 0GPIO peripheral clock enable bit_offset: 4 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOFEN description: 0GPIO peripheral clock enable bit_offset: 5 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOGEN description: 0GPIO peripheral clock enable bit_offset: 6 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOHEN description: 0GPIO peripheral clock enable bit_offset: 7 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOIEN description: 0GPIO peripheral clock enable bit_offset: 8 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOJEN description: 0GPIO peripheral clock enable bit_offset: 9 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: GPIOKEN description: 0GPIO peripheral clock enable bit_offset: 10 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: CRCEN description: CRC peripheral clock enable bit_offset: 19 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: BDMAEN description: BDMA and DMAMUX2 Clock Enable bit_offset: 21 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: ADC3EN description: ADC3 Peripheral Clocks Enable bit_offset: 24 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: HSEMEN description: HSEM peripheral clock enable bit_offset: 25 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + - name: BKPRAMEN description: Backup RAM Clock Enable bit_offset: 28 bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN + fieldset/C1_AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: @@ -2250,82 +1936,82 @@ fieldset/C1_AHB4LPENR: description: GPIO peripheral clock enable during CSleep mode bit_offset: 0 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOBLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOCLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 2 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIODLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 3 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOELPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOFLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOGLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 6 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOHLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 7 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOILPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 8 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOJLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 9 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOKLPEN description: GPIO peripheral clock enable during CSleep mode bit_offset: 10 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: CRCLPEN description: CRC peripheral clock enable during CSleep mode bit_offset: 19 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: BDMALPEN description: BDMA Clock Enable During CSleep Mode bit_offset: 21 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: ADC3LPEN description: ADC3 Peripheral Clocks Enable During CSleep Mode bit_offset: 24 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: BKPRAMLPEN description: Backup RAM Clock Enable During CSleep Mode bit_offset: 28 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + - name: SRAM4LPEN description: SRAM4 Clock Enable During CSleep Mode bit_offset: 29 bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN + fieldset/C1_APB1HENR: description: RCC APB1 Clock Register fields: @@ -2333,27 +2019,27 @@ fieldset/C1_APB1HENR: description: Clock Recovery System peripheral clock enable bit_offset: 1 bit_size: 1 - enum: C1_APB1HENR_CRSEN + - name: SWPEN description: SWPMI Peripheral Clocks Enable bit_offset: 2 bit_size: 1 - enum: C1_APB1HENR_CRSEN + - name: OPAMPEN description: OPAMP peripheral clock enable bit_offset: 4 bit_size: 1 - enum: C1_APB1HENR_CRSEN + - name: MDIOSEN description: MDIOS peripheral clock enable bit_offset: 5 bit_size: 1 - enum: C1_APB1HENR_CRSEN + - name: FDCANEN description: FDCAN Peripheral Clocks Enable bit_offset: 8 bit_size: 1 - enum: C1_APB1HENR_CRSEN + fieldset/C1_APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: @@ -2361,27 +2047,27 @@ fieldset/C1_APB1HLPENR: description: Clock Recovery System peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN + - name: SWPLPEN description: SWPMI Peripheral Clocks Enable During CSleep Mode bit_offset: 2 bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN + - name: OPAMPLPEN description: OPAMP peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN + - name: MDIOSLPEN description: MDIOS peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN + - name: FDCANLPEN description: FDCAN Peripheral Clocks Enable During CSleep Mode bit_offset: 8 bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN + fieldset/C1_APB1LENR: description: RCC APB1 Clock Register fields: @@ -2389,122 +2075,122 @@ fieldset/C1_APB1LENR: description: TIM peripheral clock enable bit_offset: 0 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM3EN description: TIM peripheral clock enable bit_offset: 1 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM4EN description: TIM peripheral clock enable bit_offset: 2 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM5EN description: TIM peripheral clock enable bit_offset: 3 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM6EN description: TIM peripheral clock enable bit_offset: 4 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM7EN description: TIM peripheral clock enable bit_offset: 5 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM12EN description: TIM peripheral clock enable bit_offset: 6 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM13EN description: TIM peripheral clock enable bit_offset: 7 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: TIM14EN description: TIM peripheral clock enable bit_offset: 8 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: LPTIM1EN description: LPTIM1 Peripheral Clocks Enable bit_offset: 9 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: SPI2EN description: SPI2 Peripheral Clocks Enable bit_offset: 14 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: SPI3EN description: SPI3 Peripheral Clocks Enable bit_offset: 15 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: SPDIFRXEN description: SPDIFRX Peripheral Clocks Enable bit_offset: 16 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: USART2EN description: USART2 Peripheral Clocks Enable bit_offset: 17 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: USART3EN description: USART3 Peripheral Clocks Enable bit_offset: 18 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: UART4EN description: UART4 Peripheral Clocks Enable bit_offset: 19 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: UART5EN description: UART5 Peripheral Clocks Enable bit_offset: 20 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: I2C1EN description: I2C1 Peripheral Clocks Enable bit_offset: 21 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: I2C2EN description: I2C2 Peripheral Clocks Enable bit_offset: 22 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: I2C3EN description: I2C3 Peripheral Clocks Enable bit_offset: 23 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: CECEN description: HDMI-CEC peripheral clock enable bit_offset: 27 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: DAC12EN description: DAC1&2 peripheral clock enable bit_offset: 29 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: UART7EN description: UART7 Peripheral Clocks Enable bit_offset: 30 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + - name: UART8EN description: UART8 Peripheral Clocks Enable bit_offset: 31 bit_size: 1 - enum: C1_APB1LENR_TIM2EN + fieldset/C1_APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: @@ -2512,122 +2198,122 @@ fieldset/C1_APB1LLPENR: description: TIM2 peripheral clock enable during CSleep mode bit_offset: 0 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM3LPEN description: TIM3 peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM4LPEN description: TIM4 peripheral clock enable during CSleep mode bit_offset: 2 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM5LPEN description: TIM5 peripheral clock enable during CSleep mode bit_offset: 3 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM6LPEN description: TIM6 peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM7LPEN description: TIM7 peripheral clock enable during CSleep mode bit_offset: 5 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM12LPEN description: TIM12 peripheral clock enable during CSleep mode bit_offset: 6 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM13LPEN description: TIM13 peripheral clock enable during CSleep mode bit_offset: 7 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM14LPEN description: TIM14 peripheral clock enable during CSleep mode bit_offset: 8 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: LPTIM1LPEN description: LPTIM1 Peripheral Clocks Enable During CSleep Mode bit_offset: 9 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: SPI2LPEN description: SPI2 Peripheral Clocks Enable During CSleep Mode bit_offset: 14 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: SPI3LPEN description: SPI3 Peripheral Clocks Enable During CSleep Mode bit_offset: 15 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: SPDIFRXLPEN description: SPDIFRX Peripheral Clocks Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: USART2LPEN description: USART2 Peripheral Clocks Enable During CSleep Mode bit_offset: 17 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: USART3LPEN description: USART3 Peripheral Clocks Enable During CSleep Mode bit_offset: 18 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: UART4LPEN description: UART4 Peripheral Clocks Enable During CSleep Mode bit_offset: 19 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: UART5LPEN description: UART5 Peripheral Clocks Enable During CSleep Mode bit_offset: 20 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: I2C1LPEN description: I2C1 Peripheral Clocks Enable During CSleep Mode bit_offset: 21 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: I2C2LPEN description: I2C2 Peripheral Clocks Enable During CSleep Mode bit_offset: 22 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: I2C3LPEN description: I2C3 Peripheral Clocks Enable During CSleep Mode bit_offset: 23 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: CECLPEN description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode bit_offset: 27 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: DAC12LPEN description: DAC1/2 peripheral clock enable during CSleep mode bit_offset: 29 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: UART7LPEN description: UART7 Peripheral Clocks Enable During CSleep Mode bit_offset: 30 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + - name: UART8LPEN description: UART8 Peripheral Clocks Enable During CSleep Mode bit_offset: 31 bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN + fieldset/C1_APB2ENR: description: RCC APB2 Clock Register fields: @@ -2635,77 +2321,77 @@ fieldset/C1_APB2ENR: description: TIM1 peripheral clock enable bit_offset: 0 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: TIM8EN description: TIM8 peripheral clock enable bit_offset: 1 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: USART1EN description: USART1 Peripheral Clocks Enable bit_offset: 4 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: USART6EN description: USART6 Peripheral Clocks Enable bit_offset: 5 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: SPI1EN description: SPI1 Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: SPI4EN description: SPI4 Peripheral Clocks Enable bit_offset: 13 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: TIM15EN description: TIM15 peripheral clock enable bit_offset: 16 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: TIM16EN description: TIM16 peripheral clock enable bit_offset: 17 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: TIM17EN description: TIM17 peripheral clock enable bit_offset: 18 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: SPI5EN description: SPI5 Peripheral Clocks Enable bit_offset: 20 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: SAI1EN description: SAI1 Peripheral Clocks Enable bit_offset: 22 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: SAI2EN description: SAI2 Peripheral Clocks Enable bit_offset: 23 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: SAI3EN description: SAI3 Peripheral Clocks Enable bit_offset: 24 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: DFSDM1EN description: DFSDM1 Peripheral Clocks Enable bit_offset: 28 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + - name: HRTIMEN description: HRTIM peripheral clock enable bit_offset: 29 bit_size: 1 - enum: C1_APB2ENR_TIM1EN + fieldset/C1_APB2LPENR: description: RCC APB2 Sleep Clock Register fields: @@ -2713,77 +2399,77 @@ fieldset/C1_APB2LPENR: description: TIM1 peripheral clock enable during CSleep mode bit_offset: 0 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: TIM8LPEN description: TIM8 peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: USART1LPEN description: USART1 Peripheral Clocks Enable During CSleep Mode bit_offset: 4 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: USART6LPEN description: USART6 Peripheral Clocks Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: SPI1LPEN description: SPI1 Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: SPI4LPEN description: SPI4 Peripheral Clocks Enable During CSleep Mode bit_offset: 13 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: TIM15LPEN description: TIM15 peripheral clock enable during CSleep mode bit_offset: 16 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: TIM16LPEN description: TIM16 peripheral clock enable during CSleep mode bit_offset: 17 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: TIM17LPEN description: TIM17 peripheral clock enable during CSleep mode bit_offset: 18 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: SPI5LPEN description: SPI5 Peripheral Clocks Enable During CSleep Mode bit_offset: 20 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: SAI1LPEN description: SAI1 Peripheral Clocks Enable During CSleep Mode bit_offset: 22 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: SAI2LPEN description: SAI2 Peripheral Clocks Enable During CSleep Mode bit_offset: 23 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: SAI3LPEN description: SAI3 Peripheral Clocks Enable During CSleep Mode bit_offset: 24 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: DFSDM1LPEN description: DFSDM1 Peripheral Clocks Enable During CSleep Mode bit_offset: 28 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + - name: HRTIMLPEN description: HRTIM peripheral clock enable during CSleep mode bit_offset: 29 bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN + fieldset/C1_APB3ENR: description: RCC APB3 Clock Register fields: @@ -2791,12 +2477,12 @@ fieldset/C1_APB3ENR: description: LTDC peripheral clock enable bit_offset: 3 bit_size: 1 - enum: C1_APB3ENR_LTDCEN + - name: WWDG1EN description: WWDG1 Clock Enable bit_offset: 6 bit_size: 1 - enum: C1_APB3ENR_LTDCEN + fieldset/C1_APB3LPENR: description: RCC APB3 Sleep Clock Register fields: @@ -2804,12 +2490,12 @@ fieldset/C1_APB3LPENR: description: LTDC peripheral clock enable during CSleep mode bit_offset: 3 bit_size: 1 - enum: C1_APB3LPENR_LTDCLPEN + - name: WWDG1LPEN description: WWDG1 Clock Enable During CSleep Mode bit_offset: 6 bit_size: 1 - enum: C1_APB3LPENR_LTDCLPEN + fieldset/C1_APB4ENR: description: RCC APB4 Clock Register fields: @@ -2817,62 +2503,62 @@ fieldset/C1_APB4ENR: description: SYSCFG peripheral clock enable bit_offset: 1 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: LPUART1EN description: LPUART1 Peripheral Clocks Enable bit_offset: 3 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: SPI6EN description: SPI6 Peripheral Clocks Enable bit_offset: 5 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: I2C4EN description: I2C4 Peripheral Clocks Enable bit_offset: 7 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM2EN description: LPTIM2 Peripheral Clocks Enable bit_offset: 9 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM3EN description: LPTIM3 Peripheral Clocks Enable bit_offset: 10 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM4EN description: LPTIM4 Peripheral Clocks Enable bit_offset: 11 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM5EN description: LPTIM5 Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: COMP12EN description: COMP1/2 peripheral clock enable bit_offset: 14 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: VREFEN description: VREF peripheral clock enable bit_offset: 15 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: RTCAPBEN description: RTC APB Clock Enable bit_offset: 16 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + - name: SAI4EN description: SAI4 Peripheral Clocks Enable bit_offset: 21 bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN + fieldset/C1_APB4LPENR: description: RCC APB4 Sleep Clock Register fields: @@ -2880,62 +2566,62 @@ fieldset/C1_APB4LPENR: description: SYSCFG peripheral clock enable during CSleep mode bit_offset: 1 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPUART1LPEN description: LPUART1 Peripheral Clocks Enable During CSleep Mode bit_offset: 3 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: SPI6LPEN description: SPI6 Peripheral Clocks Enable During CSleep Mode bit_offset: 5 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: I2C4LPEN description: I2C4 Peripheral Clocks Enable During CSleep Mode bit_offset: 7 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM2LPEN description: LPTIM2 Peripheral Clocks Enable During CSleep Mode bit_offset: 9 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM3LPEN description: LPTIM3 Peripheral Clocks Enable During CSleep Mode bit_offset: 10 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM4LPEN description: LPTIM4 Peripheral Clocks Enable During CSleep Mode bit_offset: 11 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM5LPEN description: LPTIM5 Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: COMP12LPEN description: COMP1/2 peripheral clock enable during CSleep mode bit_offset: 14 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: VREFLPEN description: VREF peripheral clock enable during CSleep mode bit_offset: 15 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: RTCAPBLPEN description: RTC APB Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + - name: SAI4LPEN description: SAI4 Peripheral Clocks Enable During CSleep Mode bit_offset: 21 bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN + fieldset/C1_RSR: description: RCC Reset Status Register fields: @@ -3473,82 +3159,82 @@ fieldset/D3AMR: description: BDMA and DMAMUX Autonomous mode enable bit_offset: 0 bit_size: 1 - enum: BDMAAMEN + - name: LPUART1AMEN description: LPUART1 Autonomous mode enable bit_offset: 3 bit_size: 1 - enum: BDMAAMEN + - name: SPI6AMEN description: SPI6 Autonomous mode enable bit_offset: 5 bit_size: 1 - enum: BDMAAMEN + - name: I2C4AMEN description: I2C4 Autonomous mode enable bit_offset: 7 bit_size: 1 - enum: BDMAAMEN + - name: LPTIM2AMEN description: LPTIM2 Autonomous mode enable bit_offset: 9 bit_size: 1 - enum: BDMAAMEN + - name: LPTIM3AMEN description: LPTIM3 Autonomous mode enable bit_offset: 10 bit_size: 1 - enum: BDMAAMEN + - name: LPTIM4AMEN description: LPTIM4 Autonomous mode enable bit_offset: 11 bit_size: 1 - enum: BDMAAMEN + - name: LPTIM5AMEN description: LPTIM5 Autonomous mode enable bit_offset: 12 bit_size: 1 - enum: BDMAAMEN + - name: COMP12AMEN description: COMP12 Autonomous mode enable bit_offset: 14 bit_size: 1 - enum: BDMAAMEN + - name: VREFAMEN description: VREF Autonomous mode enable bit_offset: 15 bit_size: 1 - enum: BDMAAMEN + - name: RTCAMEN description: RTC Autonomous mode enable bit_offset: 16 bit_size: 1 - enum: BDMAAMEN + - name: CRCAMEN description: CRC Autonomous mode enable bit_offset: 19 bit_size: 1 - enum: BDMAAMEN + - name: SAI4AMEN description: SAI4 Autonomous mode enable bit_offset: 21 bit_size: 1 - enum: BDMAAMEN + - name: ADC3AMEN description: ADC3 Autonomous mode enable bit_offset: 24 bit_size: 1 - enum: BDMAAMEN + - name: BKPRAMAMEN description: Backup RAM Autonomous mode enable bit_offset: 28 bit_size: 1 - enum: BDMAAMEN + - name: SRAM4AMEN description: SRAM4 Autonomous mode enable bit_offset: 29 bit_size: 1 - enum: BDMAAMEN + fieldset/D3CCIPR: description: RCC Domain 3 Kernel Clock Configuration Register fields: @@ -3727,7 +3413,7 @@ fieldset/PLLCFGR: array: len: 3 stride: 4 - enum: PLL1FRACEN + - name: PLLVCOSEL description: PLL1 VCO selection bit_offset: 1 @@ -3751,7 +3437,7 @@ fieldset/PLLCFGR: array: len: 3 stride: 3 - enum: DIVP1EN + - name: DIVQEN description: PLL1 DIVQ divider output enable bit_offset: 17 @@ -3759,7 +3445,7 @@ fieldset/PLLCFGR: array: len: 3 stride: 3 - enum: DIVP1EN + - name: DIVREN description: PLL1 DIVR divider output enable bit_offset: 18 @@ -3767,7 +3453,7 @@ fieldset/PLLCFGR: array: len: 3 stride: 3 - enum: DIVP1EN + fieldset/PLLCKSELR: description: RCC PLLs Clock Source Selection Register fields: @@ -3853,345 +3539,6 @@ enum/ADCSEL: - name: PER description: PER selected as peripheral clock value: 2 -enum/AHB1ENR_DMA1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB1LPENR_DMA1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/AHB2ENR_DCMIEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB2LPENR_DCMILPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/AHB3ENR_MDMAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB3LPENR_MDMALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/AHB4ENR_GPIOAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB4LPENR_GPIOALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB1HENR_CRSEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB1HLPENR_CRSLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB1LENR_TIM2EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB1LLPENR_TIM2LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB2ENR_TIM1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB2LPENR_TIM1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB3ENR_LTDCEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB3LPENR_LTDCLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB4ENR_SYSCFGEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB4LPENR_SYSCFGLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/BDMAAMEN: - bit_size: 1 - variants: - - name: Disabled - description: Clock disabled in autonomous mode - value: 0 - - name: Enabled - description: Clock enabled in autonomous mode - value: 1 -enum/BDRST: - bit_size: 1 - variants: - - name: Reset - description: Resets the entire VSW domain - value: 1 -enum/C1_AHB1ENR_DMA1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB1LPENR_DMA1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_AHB2ENR_DCMIEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB2LPENR_DCMILPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_AHB3ENR_MDMAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB3LPENR_MDMALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_AHB4ENR_GPIOAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB4LPENR_GPIOALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB1HENR_CRSEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB1HLPENR_CRSLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB1LENR_TIM2EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB1LLPENR_TIM2LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB2ENR_TIM1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB2LPENR_TIM1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB3ENR_LTDCEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB3LPENR_LTDCLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB4ENR_SYSCFGEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB4LPENR_SYSCFGLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 enum/C1_RSR_CPURSTFR: bit_size: 1 variants: @@ -4210,12 +3557,6 @@ enum/C1_RSR_RMVF: - name: Clear description: Clear the reset flags value: 1 -enum/CAMITFRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 enum/CECSEL: bit_size: 2 variants: @@ -4240,12 +3581,6 @@ enum/CKPERSEL: - name: HSE description: HSE selected as peripheral clock value: 2 -enum/CRSRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 enum/D1PPRE: bit_size: 3 variants: @@ -4507,21 +3842,6 @@ enum/DIVP1: - name: Div128 description: pll_p_ck = vco_ck / 128 value: 127 -enum/DIVP1EN: - bit_size: 1 - variants: - - name: Disabled - description: Clock ouput is disabled - value: 0 - - name: Enabled - description: Clock output is enabled - value: 1 -enum/DMA1RST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 enum/FDCANSEL: bit_size: 2 variants: @@ -4549,12 +3869,6 @@ enum/FMCSEL: - name: PER description: PER selected as peripheral clock value: 3 -enum/GPIOARST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 enum/HPRE: bit_size: 4 variants: @@ -4831,12 +4145,6 @@ enum/LSIRDYR: - name: Ready description: LSI oscillator ready value: 1 -enum/LTDCRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 enum/MCO1: bit_size: 3 variants: @@ -4876,21 +4184,6 @@ enum/MCO2: - name: LSI description: LSI selected for micro-controller clock output value: 5 -enum/MDMARST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/PLL1FRACEN: - bit_size: 1 - variants: - - name: Reset - description: Reset latch to tranfer FRACN to the Sigma-Delta modulator - value: 0 - - name: Set - description: Set latch to tranfer FRACN to the Sigma-Delta modulator - value: 1 enum/PLL1RGE: bit_size: 2 variants: @@ -4963,15 +4256,6 @@ enum/RSR_RMVF: - name: Clear description: Clear the reset flags value: 1 -enum/RTCEN: - bit_size: 1 - variants: - - name: Disabled - description: RTC clock disabled - value: 0 - - name: Enabled - description: RTC clock enabled - value: 1 enum/RTCSEL: bit_size: 2 variants: @@ -5137,24 +4421,6 @@ enum/SWSR: - name: PLL1 description: PLL1 used as system clock value: 3 -enum/SYSCFGRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/TIM1RST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/TIM2RST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 enum/TIMPRE: bit_size: 1 variants: diff --git a/transform-RCC.yaml b/transform-RCC.yaml deleted file mode 100644 index 3634650..0000000 --- a/transform-RCC.yaml +++ /dev/null @@ -1,48 +0,0 @@ -transforms: - - MergeEnums: - from: CCMR\d_Input_CC\dS - to: CCMR_Input_CCS - check: Layout - - # Remove digits from enum names - - MergeEnums: - from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]* - to: $1$2$3 - skip_unmergeable: true - - - MakeFieldArray: - fieldsets: .* - from: ([A-Z]+)\d+ - to: $1 - allow_cursed: true - - MakeFieldArray: - fieldsets: .* - from: P\d+WP - to: PWP -# - MakeRegisterArray: -# blocks: .* -# from: ([A-Z]+)\d+ -# to: $1 - - MakeRegisterArray: - blocks: .* - from: EXTICR\d+ - to: EXTICR - - MergeEnums: - from: '[HL](IFCR|ISR)_(.*)' - to: $2 - - MergeFieldsets: - from: '[HL](IFCR|ISR)' - to: $1 - - MergeFieldsets: - from: EXTICR\d - to: EXTICR - - MakeRegisterArray: - blocks: .* - from: '[HL](IFCR|ISR)' - to: $1 - - DeleteEnums: - from: '.*EN' - bit_size: 1 - - DeleteEnums: - from: '.*RST' - bit_size: 1