chiptool fmt.

data/registers/adc_g4.yaml

@@ -129,16 +129,16 @@ fieldset/CALFACT:
 fieldset/CFGR:
   description: configuration register 1
   fields:
-  - name: DMAEN
-    description: Direct memory access enable
-    bit_offset: 0
-    bit_size: 1
-    enum: DMAEN
   - name: DMACFG
     description: direct memory access configuration
     bit_offset: 0
     bit_size: 1
     enum: DMACFG
+  - name: DMAEN
+    description: Direct memory access enable
+    bit_offset: 0
+    bit_size: 1
+    enum: DMAEN
   - name: RES
     description: data resolution
     bit_offset: 3
@@ -154,12 +154,12 @@ fieldset/CFGR:
     bit_size: 2
     enum: EXTEN
   - name: OVRMOD
-    description: overrun mode 
+    description: overrun mode
     bit_offset: 12
     bit_size: 1
     enum: OVRMOD
   - name: CONT
-    description:  single / continuous conversion mode for regular conversions
+    description: single / continuous conversion mode for regular conversions
     bit_offset: 13
     bit_size: 1
   - name: AUTDLY
@@ -171,7 +171,7 @@ fieldset/CFGR:
     bit_offset: 15
     bit_size: 1
   - name: DISCEN
-    description:  discontinuous mode for regular channels
+    description: discontinuous mode for regular channels
     bit_offset: 16
     bit_size: 1
   - name: DISCNUM
@@ -188,7 +188,7 @@ fieldset/CFGR:
     bit_size: 1
     enum: JQM
   - name: AWD1SGL
-    description:  enable the watchdog 1 on a single channel or on all channels
+    description: enable the watchdog 1 on a single channel or on all channels
     bit_offset: 22
     bit_size: 1
     enum: AWD1SGL
@@ -321,6 +321,13 @@ fieldset/DR:
     description: group regular conversion data
     bit_offset: 0
     bit_size: 16
+fieldset/GCOMP:
+  description: Gain compensation coefficient
+  fields:
+  - name: GCOMPCOEFF
+    description: Gain compensation coefficient
+    bit_offset: 0
+    bit_size: 14
 fieldset/IER:
   description: interrupt enable register
   fields:
@@ -445,43 +452,6 @@ fieldset/JSQR:
     array:
       len: 4
       stride: 6
-fieldset/TR1:
-  description: analog watchdog threshold register 1
-  fields:
-  - name: LT1
-    description: analog watchdog 1 lower threshold
-    bit_offset: 0
-    bit_size: 12
-  - name: AWDFILT
-    description: analog watchdog filtering parameter
-    bit_offset: 12
-    bit_size: 3
-  - name: HT1
-    description: analog watchdog 1 higher threshold
-    bit_offset: 16
-    bit_size: 12
-fieldset/TR2:
-  description: analog watchdog threshold register 2
-  fields:
-  - name: LT2
-    description: analog watchdog 2 lower threshold
-    bit_offset: 0
-    bit_size: 8
-  - name: HT2
-    description: analog watchdog 2 higher threshold
-    bit_offset: 16
-    bit_size: 8
-fieldset/TR3:
-  description: analog watchdog threshold register 3
-  fields:
-  - name: LT3
-    description: analog watchdog 3 lower threshold
-    bit_offset: 0
-    bit_size: 8
-  - name: HT3
-    description: analog watchdog 3 higher threshold
-    bit_offset: 16
-    bit_size: 8
 fieldset/OFR:
   description: offset number x register
   fields:
@@ -498,7 +468,7 @@ fieldset/OFR:
     bit_offset: 25
     bit_size: 1
   - name: OFFSET1_CH
-    description: Channel selection for the data offset 
+    description: Channel selection for the data offset
     bit_offset: 26
     bit_size: 5
   - name: OFFSET_EN
@@ -575,13 +545,43 @@ fieldset/SQR4:
     array:
       len: 2
       stride: 6
-fieldset/GCOMP:
+fieldset/TR1:
-  description: Gain compensation coefficient
+  description: analog watchdog threshold register 1
   fields:
-  - name: GCOMPCOEFF
+  - name: LT1
-    description:  Gain compensation coefficient
+    description: analog watchdog 1 lower threshold
     bit_offset: 0
-    bit_size: 14
+    bit_size: 12
+  - name: AWDFILT
+    description: analog watchdog filtering parameter
+    bit_offset: 12
+    bit_size: 3
+  - name: HT1
+    description: analog watchdog 1 higher threshold
+    bit_offset: 16
+    bit_size: 12
+fieldset/TR2:
+  description: analog watchdog threshold register 2
+  fields:
+  - name: LT2
+    description: analog watchdog 2 lower threshold
+    bit_offset: 0
+    bit_size: 8
+  - name: HT2
+    description: analog watchdog 2 higher threshold
+    bit_offset: 16
+    bit_size: 8
+fieldset/TR3:
+  description: analog watchdog threshold register 3
+  fields:
+  - name: LT3
+    description: analog watchdog 3 lower threshold
+    bit_offset: 0
+    bit_size: 8
+  - name: HT3
+    description: analog watchdog 3 higher threshold
+    bit_offset: 16
+    bit_size: 8
 enum/ADCALDIF:
   bit_size: 1
   variants:
@@ -615,15 +615,6 @@ enum/DIFSEL:
   - name: Differential
     description: Input channel is configured in differential mode
     value: 1
-enum/DMAEN:
-  bit_size: 1
-  variants:
-  - name: Disable
-    description: DMA disable
-    value: 0
-  - name: Enable
-    description: DMA enable 
-    value: 1
 enum/DMACFG:
   bit_size: 1
   variants:
@@ -633,6 +624,15 @@ enum/DMACFG:
   - name: CircularMode
     description: DMA Circular mode selected
     value: 1
+enum/DMAEN:
+  bit_size: 1
+  variants:
+  - name: Disable
+    description: DMA disable
+    value: 0
+  - name: Enable
+    description: DMA enable
+    value: 1
 enum/EXTEN:
   bit_size: 2
   variants:
@@ -740,4 +740,4 @@ enum/TROVS:
     value: 0
   - name: Triggered
     description: Each oversampled conversion for a channel needs a new trigger
-    value: 1
+    value: 1

data/registers/comp_u0.yaml

@@ -94,24 +94,6 @@ enum/HYST:
     value: 2
   - name: High
     value: 3
-enum/WINMODE:
-  bit_size: 1
-  variants:
-  - name: ThisInpsel
-    description: Signal selected with INPSEL[2:0] bitfield of this register.
-    value: 0
-  - name: OtherInpsel
-    description: Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode).
-    value: 1
-enum/WINOUT:
-  bit_size: 1
-  variants:
-  - name: COMP1_VALUE
-    description: Comparator 1 value.
-    value: 0
-  - name: COMP1_VALUE XOR COMP2_VALUE
-    description: Comparator 1 value XOR comparator 2 value (required for window mode).
-    value: 1
 enum/POLARITY:
   bit_size: 1
   variants:
@@ -136,3 +118,21 @@ enum/PWRMODE:
   - name: VeryLowSpeed
     description: Very-low speed / ultra-low power.
     value: 3
+enum/WINMODE:
+  bit_size: 1
+  variants:
+  - name: ThisInpsel
+    description: Signal selected with INPSEL[2:0] bitfield of this register.
+    value: 0
+  - name: OtherInpsel
+    description: Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode).
+    value: 1
+enum/WINOUT:
+  bit_size: 1
+  variants:
+  - name: COMP1_VALUE
+    description: Comparator 1 value.
+    value: 0
+  - name: COMP1_VALUE XOR COMP2_VALUE
+    description: Comparator 1 value XOR comparator 2 value (required for window mode).
+    value: 1

data/registers/crc_v2.yaml

@@ -1,13 +1,13 @@
 block/CRC:
   description: Cyclic Redundancy Check calculation unit
   items:
-  - name: DR32
-    description: Data register
-    byte_offset: 0
   - name: DR16
     description: Data register - half-word sized
     byte_offset: 0
     bit_size: 16
+  - name: DR32
+    description: Data register
+    byte_offset: 0
   - name: DR8
     description: Data register - byte sized
     byte_offset: 0

data/registers/crc_v3.yaml

@@ -1,13 +1,13 @@
 block/CRC:
   description: Cyclic Redundancy Check calculation unit
   items:
-  - name: DR32
-    description: Data register
-    byte_offset: 0
   - name: DR16
     description: Data register - half-word sized
     byte_offset: 0
     bit_size: 16
+  - name: DR32
+    description: Data register
+    byte_offset: 0
   - name: DR8
     description: Data register - byte sized
     byte_offset: 0

data/registers/flash_h50.yaml

@@ -713,27 +713,6 @@ enum/OPTSR_NRST_STDBY:
   - name: B_0x1
     description: no reset generated when entering Standby mode on core domain.
     value: 1
-enum/PRODUCT_STATE:
-  bit_size: 8
-  variants:
-  - name: OPEN
-    description: Open
-    value: 0xED
-  - name: PROVISIONING
-    description: Provisioning
-    value: 0x17
-  - name: IROT_PROVISIONED
-    description: iROT-Provisioned
-    value: 0x2E
-  - name: CLOSED
-    description: Closed
-    value: 0x72
-  - name: LOCKED
-    description: Locked
-    value: 0x5C
-  - name: REGRESSION
-    description: Regression
-    value: 0x9A
 enum/OPTSR_NRST_STOP:
   bit_size: 1
   variants:
@@ -770,3 +749,24 @@ enum/PRIVBB:
   - name: B_0x1
     description: sector y in bank 1 is privileged
     value: 1
+enum/PRODUCT_STATE:
+  bit_size: 8
+  variants:
+  - name: PROVISIONING
+    description: Provisioning
+    value: 23
+  - name: IROT_PROVISIONED
+    description: iROT-Provisioned
+    value: 46
+  - name: LOCKED
+    description: Locked
+    value: 92
+  - name: CLOSED
+    description: Closed
+    value: 114
+  - name: REGRESSION
+    description: Regression
+    value: 154
+  - name: OPEN
+    description: Open
+    value: 237

data/registers/hsem_v1.yaml

@@ -18,34 +18,34 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 256
     fieldset: IER
-    array:
-      len: 2
-      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
-    byte_offset: 260
-    fieldset: ICR
     array:
       len: 2
       stride: 16
+    byte_offset: 260
+    fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 2
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 2
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -65,6 +65,36 @@ fieldset/CR:
     description: Semaphore clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/ICR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: ISC
+    description: Interrupt semaphore x clear bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/IER:
+  description: HSEM Interrupt enable register.
+  fields:
+  - name: ISE
+    description: Interrupt semaphore x enable bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/ISR:
+  description: HSEM Interrupt status register.
+  fields:
+  - name: ISF
+    description: Interrupt semaphore x status bit before enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/KEYR:
   description: HSEM Interrupt clear register.
   fields:
@@ -72,6 +102,16 @@ fieldset/KEYR:
     description: Semaphore Clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/MISR:
+  description: HSEM Masked interrupt status register.
+  fields:
+  - name: MISF
+    description: masked interrupt semaphore x status bit after enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:
@@ -102,43 +142,3 @@ fieldset/RLR:
     description: Lock indication.
     bit_offset: 31
     bit_size: 1
-fieldset/IER:
-  description: HSEM Interrupt enable register.
-  fields:
-  - name: ISE
-    description: Interrupt semaphore x enable bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ICR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: ISC
-    description: Interrupt semaphore x clear bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ISR:
-  description: HSEM Interrupt status register.
-  fields:
-  - name: ISF
-    description: Interrupt semaphore x status bit before enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/MISR:
-  description: HSEM Masked interrupt status register.
-  fields:
-  - name: MISF
-    description: masked interrupt semaphore x status bit after enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1

data/registers/hsem_v2.yaml

@@ -18,35 +18,35 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
-    byte_offset: 256
-    fieldset: IER
     array:
       len: 1
       stride: 16
+    byte_offset: 256
+    fieldset: IER
   - name: ICR
     description: HSEM Interrupt clear register.
+    array:
+      len: 1
+      stride: 16
     byte_offset: 260
     access: Read
     fieldset: ICR
+  - name: ISR
+    description: HSEM Interrupt status register.
     array:
       len: 1
       stride: 16
-  - name: ISR
-    description: HSEM Interrupt status register.
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 1
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 1
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -66,6 +66,36 @@ fieldset/CR:
     description: Semaphore clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/ICR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: ISC
+    description: Interrupt semaphore x clear bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/IER:
+  description: HSEM Interrupt enable register.
+  fields:
+  - name: ISE
+    description: Interrupt semaphore x enable bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/ISR:
+  description: HSEM Interrupt status register.
+  fields:
+  - name: ISF
+    description: Interrupt semaphore x status bit before enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/KEYR:
   description: HSEM Interrupt clear register.
   fields:
@@ -73,6 +103,16 @@ fieldset/KEYR:
     description: Semaphore Clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/MISR:
+  description: HSEM Masked interrupt status register.
+  fields:
+  - name: MISF
+    description: masked interrupt semaphore x status bit after enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:
@@ -103,43 +143,3 @@ fieldset/RLR:
     description: Lock indication.
     bit_offset: 31
     bit_size: 1
-fieldset/IER:
-  description: HSEM Interrupt enable register.
-  fields:
-  - name: ISE
-    description: Interrupt semaphore x enable bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ICR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: ISC
-    description: Interrupt semaphore x clear bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ISR:
-  description: HSEM Interrupt status register.
-  fields:
-  - name: ISF
-    description: Interrupt semaphore x status bit before enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/MISR:
-  description: HSEM Masked interrupt status register.
-  fields:
-  - name: MISF
-    description: masked interrupt semaphore x status bit after enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1

data/registers/hsem_v3.yaml

@@ -18,34 +18,34 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 256
     fieldset: IER
-    array:
-      len: 2
-      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
-    byte_offset: 260
-    fieldset: ICR
     array:
       len: 2
       stride: 16
+    byte_offset: 260
+    fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 2
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 2
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -66,6 +66,36 @@ fieldset/CR:
     description: Semaphore clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/ICR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: ISC
+    description: Interrupt semaphore x clear bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/IER:
+  description: HSEM Interrupt enable register.
+  fields:
+  - name: ISE
+    description: Interrupt semaphore x enable bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/ISR:
+  description: HSEM Interrupt status register.
+  fields:
+  - name: ISF
+    description: Interrupt semaphore x status bit before enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
 fieldset/KEYR:
   description: HSEM Interrupt clear register.
   fields:
@@ -73,6 +103,16 @@ fieldset/KEYR:
     description: Semaphore Clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/MISR:
+  description: HSEM Masked interrupt status register.
+  fields:
+  - name: MISF
+    description: masked interrupt semaphore x status bit after enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:
@@ -103,43 +143,3 @@ fieldset/RLR:
     description: Lock indication.
     bit_offset: 31
     bit_size: 1
-fieldset/IER:
-  description: HSEM Interrupt enable register.
-  fields:
-  - name: ISE
-    description: Interrupt semaphore x enable bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1
-fieldset/ICR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: ISC
-    description: Interrupt semaphore x clear bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1
-fieldset/ISR:
-  description: HSEM Interrupt status register.
-  fields:
-  - name: ISF
-    description: Interrupt semaphore x status bit before enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1
-fieldset/MISR:
-  description: HSEM Masked interrupt status register.
-  fields:
-  - name: MISF
-    description: masked interrupt semaphore x status bit after enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1

data/registers/hsem_v4.yaml

@@ -18,34 +18,34 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
+    array:
+      len: 1
+      stride: 16
     byte_offset: 256
     fieldset: IER
-    array:
-      len: 1
-      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
-    byte_offset: 260
-    fieldset: ICR
     array:
       len: 1
       stride: 16
+    byte_offset: 260
+    fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.
+    array:
+      len: 1
+      stride: 16
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 1
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 1
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -55,6 +55,17 @@ block/HSEM:
     description: HSEM Interrupt clear register.
     byte_offset: 324
     fieldset: KEYR
+fieldset/CR:
+  description: HSEM Clear register.
+  fields:
+  - name: COREID
+    description: COREID.
+    bit_offset: 8
+    bit_size: 4
+  - name: KEY
+    description: Semaphore clear Key.
+    bit_offset: 16
+    bit_size: 16
 fieldset/ICR:
   description: HSEM Interrupt clear register.
   fields:
@@ -85,6 +96,13 @@ fieldset/ISR:
     array:
       len: 16
       stride: 1
+fieldset/KEYR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: KEY
+    description: Semaphore Clear Key.
+    bit_offset: 16
+    bit_size: 16
 fieldset/MISR:
   description: HSEM Masked interrupt status register.
   fields:
@@ -95,24 +113,6 @@ fieldset/MISR:
     array:
       len: 16
       stride: 1
-fieldset/CR:
-  description: HSEM Clear register.
-  fields:
-  - name: COREID
-    description: COREID.
-    bit_offset: 8
-    bit_size: 4
-  - name: KEY
-    description: Semaphore clear Key.
-    bit_offset: 16
-    bit_size: 16
-fieldset/KEYR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: KEY
-    description: Semaphore Clear Key.
-    bit_offset: 16
-    bit_size: 16
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:

data/registers/lpdma_v1.yaml

@@ -408,6 +408,15 @@ fieldset/SECCFGR:
     array:
       len: 16
       stride: 1
+enum/BREQ:
+  bit_size: 1
+  variants:
+  - name: Burst
+    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.
+    value: 0
+  - name: Block
+    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).
+    value: 1
 enum/DEC:
   bit_size: 1
   variants:
@@ -417,30 +426,15 @@ enum/DEC:
   - name: Subtract
     description: The address is decremented by the programmed offset.
     value: 1
-enum/LSM:
+enum/DREQ:
   bit_size: 1
   variants:
-  - name: RunToCompletion
+  - name: SourcePeripheral
-    description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.
+    description: selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port)
     value: 0
-  - name: LinkStep
+  - name: DestinationPeripheral
-    description: channel executed once for the current LLI
+    description: selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port)
     value: 1
-enum/PRIO:
-  bit_size: 2
-  variants:
-  - name: LowWithLowhWeight
-    description: low priority, low weight
-    value: 0
-  - name: LowWithMidWeight
-    description: low priority, mid weight
-    value: 1
-  - name: LowWithHighWeight
-    description: low priority, high weight
-    value: 2
-  - name: High
-    description: high priority
-    value: 3
 enum/DW:
   bit_size: 2
   variants:
@@ -453,6 +447,15 @@ enum/DW:
   - name: Word
     description: word (4 bytes)
     value: 2
+enum/LSM:
+  bit_size: 1
+  variants:
+  - name: RunToCompletion
+    description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.
+    value: 0
+  - name: LinkStep
+    description: channel executed once for the current LLI
+    value: 1
 enum/PAM:
   bit_size: 2
   variants:
@@ -469,24 +472,21 @@ enum/PAM:
   - name: Pack
     description: source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination
     value: 2
-enum/BREQ:
+enum/PRIO:
-  bit_size: 1
+  bit_size: 2
   variants:
-  - name: Burst
+  - name: LowWithLowhWeight
-    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.
+    description: low priority, low weight
     value: 0
-  - name: Block
+  - name: LowWithMidWeight
-    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).
+    description: low priority, mid weight
-    value: 1
-enum/DREQ:
-  bit_size: 1
-  variants:
-  - name: SourcePeripheral
-    description: selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port)
-    value: 0
-  - name: DestinationPeripheral
-    description: selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port)
     value: 1
+  - name: LowWithHighWeight
+    description: low priority, high weight
+    value: 2
+  - name: High
+    description: high priority
+    value: 3
 enum/SWREQ:
   bit_size: 1
   variants:

data/registers/lptim_v2b.yaml

@@ -49,10 +49,10 @@ block/LPTIM:
     fieldset: RCR
   - name: CCMR
     description: LPTIM capture/compare mode register 1.
-    byte_offset: 44
     array:
       len: 2
       stride: 1
+    byte_offset: 44
     fieldset: CCMR
 fieldset/ARR:
   description: LPTIM autoreload register.
@@ -232,10 +232,10 @@ fieldset/DIER:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 9
+      - 9
-        - 10
+      - 10
-        - 11
+      - 11
   - name: ARRMIE
     description: Autoreload match Interrupt Enable.
     bit_offset: 1
@@ -250,10 +250,10 @@ fieldset/DIER:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 16
+      - 16
-        - 17
+      - 17
-        - 18
+      - 18
   - name: ARROKIE
     description: Autoreload register update OK Interrupt Enable.
     bit_offset: 4
@@ -287,10 +287,10 @@ fieldset/DIER:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 9
+      - 9
-        - 10
+      - 10
-        - 11
+      - 11
 fieldset/ICR:
   description: LPTIM interrupt clear register.
   fields:
@@ -300,10 +300,10 @@ fieldset/ICR:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 9
+      - 9
-        - 10
+      - 10
-        - 11
+      - 11
   - name: ARRMCF
     description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.
     bit_offset: 1
@@ -318,10 +318,10 @@ fieldset/ICR:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 16
+      - 16
-        - 17
+      - 17
-        - 18
+      - 18
   - name: ARROKCF
     description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
     bit_offset: 4
@@ -362,10 +362,10 @@ fieldset/ISR:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 9
+      - 9
-        - 10
+      - 10
-        - 11
+      - 11
   - name: ARRM
     description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
     bit_offset: 1
@@ -380,10 +380,10 @@ fieldset/ISR:
     bit_size: 1
     array:
       offsets:
-        - 0
+      - 0
-        - 16
+      - 16
-        - 17
+      - 17
-        - 18
+      - 18
   - name: ARROK
     description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
     bit_offset: 4

data/registers/rcc_h7ab.yaml

@@ -1871,7 +1871,7 @@ fieldset/CIFR:
     description: HSE ready Interrupt Flag
     bit_offset: 3
     bit_size: 1
-  - name: CSIRDY
+  - name: CSIRDYF
     description: CSI ready Interrupt Flag
     bit_offset: 4
     bit_size: 1

data/registers/rcc_u0.yaml

@@ -1047,25 +1047,6 @@ fieldset/DBGCFGR:
     description: Debug support reset Set and cleared by software.
     bit_offset: 1
     bit_size: 1
-fieldset/ICSCR:
-  description: Internal clock sources calibration register.
-  fields:
-  - name: MSICAL
-    description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
-    bit_offset: 0
-    bit_size: 8
-  - name: MSITRIM
-    description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.
-    bit_offset: 8
-    bit_size: 8
-  - name: HSICAL
-    description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
-    bit_offset: 16
-    bit_size: 8
-  - name: HSITRIM
-    description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%.
-    bit_offset: 24
-    bit_size: 7
 fieldset/GPIOENR:
   description: I/O port clock enable register.
   fields:
@@ -1147,6 +1128,25 @@ fieldset/GPIOSMENR:
     description: I/O port F clock enable during Sleep mode Set and cleared by software.
     bit_offset: 5
     bit_size: 1
+fieldset/ICSCR:
+  description: Internal clock sources calibration register.
+  fields:
+  - name: MSICAL
+    description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
+    bit_offset: 0
+    bit_size: 8
+  - name: MSITRIM
+    description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.
+    bit_offset: 8
+    bit_size: 8
+  - name: HSICAL
+    description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
+    bit_offset: 16
+    bit_size: 8
+  - name: HSITRIM
+    description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%.
+    bit_offset: 24
+    bit_size: 7
 fieldset/PLLCFGR:
   description: PLL configuration register.
   fields:

data/registers/spi_v3.yaml

@@ -31,34 +31,34 @@ block/SPI:
     byte_offset: 24
     access: Write
     fieldset: IFCR
+  - name: TXDR16
+    description: Transmit Data Register - half-word sized
+    byte_offset: 32
+    access: Write
+    bit_size: 16
   - name: TXDR32
     description: Transmit Data Register
     byte_offset: 32
     access: Write
-  - name: TXDR16
-    description: Transmit Data Register - half-word sized
-    byte_offset: 32
-    bit_size: 16
-    access: Write
   - name: TXDR8
     description: Transmit Data Register - byte sized
     byte_offset: 32
-    bit_size: 8
     access: Write
+    bit_size: 8
+  - name: RXDR16
+    description: Receive Data Register - half-word sized
+    byte_offset: 48
+    access: Read
+    bit_size: 16
   - name: RXDR32
     description: Receive Data Register
     byte_offset: 48
     access: Read
-  - name: RXDR16
-    description: Receive Data Register - half-word sized
-    byte_offset: 48
-    bit_size: 16
-    access: Read
   - name: RXDR8
     description: Receive Data Register - byte sized
     byte_offset: 48
-    bit_size: 8
     access: Read
+    bit_size: 8
   - name: CRCPOLY
     description: Polynomial Register
     byte_offset: 64

data/registers/spi_v4.yaml

@@ -31,34 +31,34 @@ block/SPI:
     byte_offset: 24
     access: Write
     fieldset: IFCR
+  - name: TXDR16
+    description: Transmit Data Register - half-word sized
+    byte_offset: 32
+    access: Write
+    bit_size: 16
   - name: TXDR32
     description: Transmit Data Register
     byte_offset: 32
     access: Write
-  - name: TXDR16
-    description: Transmit Data Register - half-word sized
-    byte_offset: 32
-    bit_size: 16
-    access: Write
   - name: TXDR8
     description: Transmit Data Register - byte sized
     byte_offset: 32
-    bit_size: 8
     access: Write
+    bit_size: 8
+  - name: RXDR16
+    description: Receive Data Register - half-word sized
+    byte_offset: 48
+    access: Read
+    bit_size: 16
   - name: RXDR32
     description: Receive Data Register
     byte_offset: 48
     access: Read
-  - name: RXDR16
-    description: Receive Data Register - half-word sized
-    byte_offset: 48
-    bit_size: 16
-    access: Read
   - name: RXDR8
     description: Receive Data Register - byte sized
     byte_offset: 48
-    bit_size: 8
     access: Read
+    bit_size: 8
   - name: CRCPOLY
     description: Polynomial Register
     byte_offset: 64

data/registers/spi_v5.yaml

@@ -34,34 +34,34 @@ block/SPI:
   - name: AUTOCR
     byte_offset: 28
     fieldset: AUTOCR
+  - name: TXDR16
+    description: Transmit Data Register - half-word sized
+    byte_offset: 32
+    access: Write
+    bit_size: 16
   - name: TXDR32
     description: Transmit Data Register
     byte_offset: 32
     access: Write
-  - name: TXDR16
-    description: Transmit Data Register - half-word sized
-    byte_offset: 32
-    bit_size: 16
-    access: Write
   - name: TXDR8
     description: Transmit Data Register - byte sized
     byte_offset: 32
-    bit_size: 8
     access: Write
+    bit_size: 8
+  - name: RXDR16
+    description: Receive Data Register - half-word sized
+    byte_offset: 48
+    access: Read
+    bit_size: 16
   - name: RXDR32
     description: Receive Data Register
     byte_offset: 48
     access: Read
-  - name: RXDR16
-    description: Receive Data Register - half-word sized
-    byte_offset: 48
-    bit_size: 16
-    access: Read
   - name: RXDR8
     description: Receive Data Register - byte sized
     byte_offset: 48
-    bit_size: 8
     access: Read
+    bit_size: 8
   - name: CRCPOLY
     description: Polynomial Register
     byte_offset: 64