chiptool fmt.

data/registers/adc_g4.yaml

@@ -129,16 +129,16 @@ fieldset/CALFACT:
 fieldset/CFGR:
   description: configuration register 1
   fields:
-  - name: DMAEN
-    description: Direct memory access enable
-    bit_offset: 0
-    bit_size: 1
-    enum: DMAEN
   - name: DMACFG
     description: direct memory access configuration
     bit_offset: 0
     bit_size: 1
     enum: DMACFG
+  - name: DMAEN
+    description: Direct memory access enable
+    bit_offset: 0
+    bit_size: 1
+    enum: DMAEN
   - name: RES
     description: data resolution
     bit_offset: 3
@@ -321,6 +321,13 @@ fieldset/DR:
     description: group regular conversion data
     bit_offset: 0
     bit_size: 16
+fieldset/GCOMP:
+  description: Gain compensation coefficient
+  fields:
+  - name: GCOMPCOEFF
+    description: Gain compensation coefficient
+    bit_offset: 0
+    bit_size: 14
 fieldset/IER:
   description: interrupt enable register
   fields:
@@ -445,43 +452,6 @@ fieldset/JSQR:
     array:
       len: 4
       stride: 6
-fieldset/TR1:
-  description: analog watchdog threshold register 1
-  fields:
-  - name: LT1
-    description: analog watchdog 1 lower threshold
-    bit_offset: 0
-    bit_size: 12
-  - name: AWDFILT
-    description: analog watchdog filtering parameter
-    bit_offset: 12
-    bit_size: 3
-  - name: HT1
-    description: analog watchdog 1 higher threshold
-    bit_offset: 16
-    bit_size: 12
-fieldset/TR2:
-  description: analog watchdog threshold register 2
-  fields:
-  - name: LT2
-    description: analog watchdog 2 lower threshold
-    bit_offset: 0
-    bit_size: 8
-  - name: HT2
-    description: analog watchdog 2 higher threshold
-    bit_offset: 16
-    bit_size: 8
-fieldset/TR3:
-  description: analog watchdog threshold register 3
-  fields:
-  - name: LT3
-    description: analog watchdog 3 lower threshold
-    bit_offset: 0
-    bit_size: 8
-  - name: HT3
-    description: analog watchdog 3 higher threshold
-    bit_offset: 16
-    bit_size: 8
 fieldset/OFR:
   description: offset number x register
   fields:
@@ -575,13 +545,43 @@ fieldset/SQR4:
     array:
       len: 2
       stride: 6
-fieldset/GCOMP:
+fieldset/TR1:
-  description: Gain compensation coefficient
+  description: analog watchdog threshold register 1
   fields:
-  - name: GCOMPCOEFF
+  - name: LT1
-    description:  Gain compensation coefficient
+    description: analog watchdog 1 lower threshold
     bit_offset: 0
-    bit_size: 14
+    bit_size: 12
+  - name: AWDFILT
+    description: analog watchdog filtering parameter
+    bit_offset: 12
+    bit_size: 3
+  - name: HT1
+    description: analog watchdog 1 higher threshold
+    bit_offset: 16
+    bit_size: 12
+fieldset/TR2:
+  description: analog watchdog threshold register 2
+  fields:
+  - name: LT2
+    description: analog watchdog 2 lower threshold
+    bit_offset: 0
+    bit_size: 8
+  - name: HT2
+    description: analog watchdog 2 higher threshold
+    bit_offset: 16
+    bit_size: 8
+fieldset/TR3:
+  description: analog watchdog threshold register 3
+  fields:
+  - name: LT3
+    description: analog watchdog 3 lower threshold
+    bit_offset: 0
+    bit_size: 8
+  - name: HT3
+    description: analog watchdog 3 higher threshold
+    bit_offset: 16
+    bit_size: 8
 enum/ADCALDIF:
   bit_size: 1
   variants:
@@ -615,15 +615,6 @@ enum/DIFSEL:
   - name: Differential
     description: Input channel is configured in differential mode
     value: 1
-enum/DMAEN:
-  bit_size: 1
-  variants:
-  - name: Disable
-    description: DMA disable
-    value: 0
-  - name: Enable
-    description: DMA enable 
-    value: 1
 enum/DMACFG:
   bit_size: 1
   variants:
@@ -633,6 +624,15 @@ enum/DMACFG:
   - name: CircularMode
     description: DMA Circular mode selected
     value: 1
+enum/DMAEN:
+  bit_size: 1
+  variants:
+  - name: Disable
+    description: DMA disable
+    value: 0
+  - name: Enable
+    description: DMA enable
+    value: 1
 enum/EXTEN:
   bit_size: 2
   variants:

data/registers/comp_u0.yaml

@@ -94,24 +94,6 @@ enum/HYST:
     value: 2
   - name: High
     value: 3
-enum/WINMODE:
-  bit_size: 1
-  variants:
-  - name: ThisInpsel
-    description: Signal selected with INPSEL[2:0] bitfield of this register.
-    value: 0
-  - name: OtherInpsel
-    description: Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode).
-    value: 1
-enum/WINOUT:
-  bit_size: 1
-  variants:
-  - name: COMP1_VALUE
-    description: Comparator 1 value.
-    value: 0
-  - name: COMP1_VALUE XOR COMP2_VALUE
-    description: Comparator 1 value XOR comparator 2 value (required for window mode).
-    value: 1
 enum/POLARITY:
   bit_size: 1
   variants:
@@ -136,3 +118,21 @@ enum/PWRMODE:
   - name: VeryLowSpeed
     description: Very-low speed / ultra-low power.
     value: 3
+enum/WINMODE:
+  bit_size: 1
+  variants:
+  - name: ThisInpsel
+    description: Signal selected with INPSEL[2:0] bitfield of this register.
+    value: 0
+  - name: OtherInpsel
+    description: Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode).
+    value: 1
+enum/WINOUT:
+  bit_size: 1
+  variants:
+  - name: COMP1_VALUE
+    description: Comparator 1 value.
+    value: 0
+  - name: COMP1_VALUE XOR COMP2_VALUE
+    description: Comparator 1 value XOR comparator 2 value (required for window mode).
+    value: 1

data/registers/crc_v2.yaml

@@ -1,13 +1,13 @@
 block/CRC:
   description: Cyclic Redundancy Check calculation unit
   items:
-  - name: DR32
-    description: Data register
-    byte_offset: 0
   - name: DR16
     description: Data register - half-word sized
     byte_offset: 0
     bit_size: 16
+  - name: DR32
+    description: Data register
+    byte_offset: 0
   - name: DR8
     description: Data register - byte sized
     byte_offset: 0

data/registers/crc_v3.yaml

@@ -1,13 +1,13 @@
 block/CRC:
   description: Cyclic Redundancy Check calculation unit
   items:
-  - name: DR32
-    description: Data register
-    byte_offset: 0
   - name: DR16
     description: Data register - half-word sized
     byte_offset: 0
     bit_size: 16
+  - name: DR32
+    description: Data register
+    byte_offset: 0
   - name: DR8
     description: Data register - byte sized
     byte_offset: 0

data/registers/dsihost_u5.yaml

@@ -437,42 +437,42 @@ fieldset/DPCBCR:
   description: DSI D-PHY clock band control register.
   fields:
   - name: BC
-      description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."
+    description: 'Band control This field selects the frequency band used by the D-PHY. Others: Reserved.'
     bit_offset: 3
     bit_size: 5
 fieldset/DPCSRCR:
   description: DSI D-PHY clock skew rate control register.
   fields:
   - name: SRC
-      description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."
+    description: 'Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.'
     bit_offset: 0
     bit_size: 8
 fieldset/DPDL0BCR:
   description: DSI D-PHY data lane 0 band control register.
   fields:
   - name: BC
-      description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."
+    description: 'Band control This field selects the frequency band used by the D-PHY. Others: Reserved.'
     bit_offset: 0
     bit_size: 5
 fieldset/DPDL0SRCR:
   description: DSI D-PHY data lane 0 skew rate control register.
   fields:
   - name: SRC
-      description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."
+    description: 'Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.'
     bit_offset: 0
     bit_size: 8
 fieldset/DPDL1BCR:
   description: DSI D-PHY data lane 1 band control register.
   fields:
   - name: BC
-      description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."
+    description: 'Band control This field selects the frequency band used by the D-PHY. Others: Reserved.'
     bit_offset: 0
     bit_size: 5
 fieldset/DPDL1SRCR:
   description: DSI D-PHY data lane 1 skew rate control register.
   fields:
   - name: SRC
-      description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."
+    description: 'Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.'
     bit_offset: 0
     bit_size: 8
 fieldset/FBSR:
@@ -1072,7 +1072,7 @@ fieldset/LCCCR:
   description: DSI Host LTDC current color coding register.
   fields:
   - name: COLC
-      description: "Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit."
+    description: 'Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit.'
     bit_offset: 0
     bit_size: 4
   - name: LPE
@@ -1090,7 +1090,7 @@ fieldset/LCOLCR:
   description: DSI Host LTDC color coding register.
   fields:
   - name: COLC
-      description: "Color coding This field configures the DPI color coding. Others: Reserved."
+    description: 'Color coding This field configures the DPI color coding. Others: Reserved.'
     bit_offset: 0
     bit_size: 4
   - name: LPE
@@ -1159,7 +1159,7 @@ fieldset/PCONFR:
   description: DSI Host PHY configuration register.
   fields:
   - name: NL
-      description: "Number of lanes This field configures the number of active data lanes: Others: Reserved."
+    description: 'Number of lanes This field configures the number of active data lanes: Others: Reserved.'
     bit_offset: 0
     bit_size: 2
   - name: SW_TIME
@@ -1298,7 +1298,7 @@ fieldset/TCCR3:
     bit_offset: 0
     bit_size: 16
   - name: PM
-      description: "Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready."
+    description: 'Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready.'
     bit_offset: 24
     bit_size: 1
 fieldset/TCCR4:
@@ -1375,7 +1375,7 @@ fieldset/VMCCR:
   description: DSI Host video mode current configuration register.
   fields:
   - name: VMT
-      description: "Video mode type This field returns the current video mode transmission type: 1x: Burst mode."
+    description: 'Video mode type This field returns the current video mode transmission type: 1x: Burst mode.'
     bit_offset: 0
     bit_size: 2
   - name: LPVSAE
@@ -1414,7 +1414,7 @@ fieldset/VMCR:
   description: DSI Host video mode configuration register.
   fields:
   - name: VMT
-      description: "Video mode type This field configures the video mode transmission type : 1x: Burst mode."
+    description: 'Video mode type This field configures the video mode transmission type : 1x: Burst mode.'
     bit_offset: 0
     bit_size: 2
   - name: LPVSAE
@@ -1705,14 +1705,14 @@ fieldset/WRPCR:
     bit_offset: 0
     bit_size: 1
   - name: NDIV
-      description: "PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2."
+    description: 'PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2.'
     bit_offset: 2
     bit_size: 9
   - name: IDF
-      description: "PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511."
+    description: 'PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511.'
     bit_offset: 11
     bit_size: 9
   - name: ODF
-      description: "PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511."
+    description: 'PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511.'
     bit_offset: 20
     bit_size: 9

data/registers/flash_h50.yaml

@@ -713,27 +713,6 @@ enum/OPTSR_NRST_STDBY:
   - name: B_0x1
     description: no reset generated when entering Standby mode on core domain.
     value: 1
-enum/PRODUCT_STATE:
-  bit_size: 8
-  variants:
-  - name: OPEN
-    description: Open
-    value: 0xED
-  - name: PROVISIONING
-    description: Provisioning
-    value: 0x17
-  - name: IROT_PROVISIONED
-    description: iROT-Provisioned
-    value: 0x2E
-  - name: CLOSED
-    description: Closed
-    value: 0x72
-  - name: LOCKED
-    description: Locked
-    value: 0x5C
-  - name: REGRESSION
-    description: Regression
-    value: 0x9A
 enum/OPTSR_NRST_STOP:
   bit_size: 1
   variants:
@@ -770,3 +749,24 @@ enum/PRIVBB:
   - name: B_0x1
     description: sector y in bank 1 is privileged
     value: 1
+enum/PRODUCT_STATE:
+  bit_size: 8
+  variants:
+  - name: PROVISIONING
+    description: Provisioning
+    value: 23
+  - name: IROT_PROVISIONED
+    description: iROT-Provisioned
+    value: 46
+  - name: LOCKED
+    description: Locked
+    value: 92
+  - name: CLOSED
+    description: Closed
+    value: 114
+  - name: REGRESSION
+    description: Regression
+    value: 154
+  - name: OPEN
+    description: Open
+    value: 237

data/registers/hsem_v1.yaml

@@ -18,34 +18,34 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 256
     fieldset: IER
-    array:
-      len: 2
-      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
-    byte_offset: 260
-    fieldset: ICR
     array:
       len: 2
       stride: 16
+    byte_offset: 260
+    fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 2
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 2
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -65,6 +65,36 @@ fieldset/CR:
     description: Semaphore clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/ICR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: ISC
+    description: Interrupt semaphore x clear bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/IER:
+  description: HSEM Interrupt enable register.
+  fields:
+  - name: ISE
+    description: Interrupt semaphore x enable bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/ISR:
+  description: HSEM Interrupt status register.
+  fields:
+  - name: ISF
+    description: Interrupt semaphore x status bit before enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/KEYR:
   description: HSEM Interrupt clear register.
   fields:
@@ -72,6 +102,16 @@ fieldset/KEYR:
     description: Semaphore Clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/MISR:
+  description: HSEM Masked interrupt status register.
+  fields:
+  - name: MISF
+    description: masked interrupt semaphore x status bit after enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:
@@ -102,43 +142,3 @@ fieldset/RLR:
     description: Lock indication.
     bit_offset: 31
     bit_size: 1
-fieldset/IER:
-  description: HSEM Interrupt enable register.
-  fields:
-  - name: ISE
-    description: Interrupt semaphore x enable bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ICR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: ISC
-    description: Interrupt semaphore x clear bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ISR:
-  description: HSEM Interrupt status register.
-  fields:
-  - name: ISF
-    description: Interrupt semaphore x status bit before enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/MISR:
-  description: HSEM Masked interrupt status register.
-  fields:
-  - name: MISF
-    description: masked interrupt semaphore x status bit after enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1

data/registers/hsem_v2.yaml

@@ -18,35 +18,35 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
-    byte_offset: 256
-    fieldset: IER
     array:
       len: 1
       stride: 16
+    byte_offset: 256
+    fieldset: IER
   - name: ICR
     description: HSEM Interrupt clear register.
+    array:
+      len: 1
+      stride: 16
     byte_offset: 260
     access: Read
     fieldset: ICR
+  - name: ISR
+    description: HSEM Interrupt status register.
     array:
       len: 1
       stride: 16
-  - name: ISR
-    description: HSEM Interrupt status register.
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 1
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 1
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -66,6 +66,36 @@ fieldset/CR:
     description: Semaphore clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/ICR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: ISC
+    description: Interrupt semaphore x clear bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/IER:
+  description: HSEM Interrupt enable register.
+  fields:
+  - name: ISE
+    description: Interrupt semaphore x enable bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/ISR:
+  description: HSEM Interrupt status register.
+  fields:
+  - name: ISF
+    description: Interrupt semaphore x status bit before enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/KEYR:
   description: HSEM Interrupt clear register.
   fields:
@@ -73,6 +103,16 @@ fieldset/KEYR:
     description: Semaphore Clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/MISR:
+  description: HSEM Masked interrupt status register.
+  fields:
+  - name: MISF
+    description: masked interrupt semaphore x status bit after enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:
@@ -103,43 +143,3 @@ fieldset/RLR:
     description: Lock indication.
     bit_offset: 31
     bit_size: 1
-fieldset/IER:
-  description: HSEM Interrupt enable register.
-  fields:
-  - name: ISE
-    description: Interrupt semaphore x enable bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ICR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: ISC
-    description: Interrupt semaphore x clear bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/ISR:
-  description: HSEM Interrupt status register.
-  fields:
-  - name: ISF
-    description: Interrupt semaphore x status bit before enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1
-fieldset/MISR:
-  description: HSEM Masked interrupt status register.
-  fields:
-  - name: MISF
-    description: masked interrupt semaphore x status bit after enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 32
-      stride: 1

data/registers/hsem_v3.yaml

@@ -18,34 +18,34 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 256
     fieldset: IER
-    array:
-      len: 2
-      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
-    byte_offset: 260
-    fieldset: ICR
     array:
       len: 2
       stride: 16
+    byte_offset: 260
+    fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.
+    array:
+      len: 2
+      stride: 16
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 2
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 2
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -66,6 +66,36 @@ fieldset/CR:
     description: Semaphore clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/ICR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: ISC
+    description: Interrupt semaphore x clear bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/IER:
+  description: HSEM Interrupt enable register.
+  fields:
+  - name: ISE
+    description: Interrupt semaphore x enable bit.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/ISR:
+  description: HSEM Interrupt status register.
+  fields:
+  - name: ISF
+    description: Interrupt semaphore x status bit before enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
 fieldset/KEYR:
   description: HSEM Interrupt clear register.
   fields:
@@ -73,6 +103,16 @@ fieldset/KEYR:
     description: Semaphore Clear Key.
     bit_offset: 16
     bit_size: 16
+fieldset/MISR:
+  description: HSEM Masked interrupt status register.
+  fields:
+  - name: MISF
+    description: masked interrupt semaphore x status bit after enable (mask).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:
@@ -103,43 +143,3 @@ fieldset/RLR:
     description: Lock indication.
     bit_offset: 31
     bit_size: 1
-fieldset/IER:
-  description: HSEM Interrupt enable register.
-  fields:
-  - name: ISE
-    description: Interrupt semaphore x enable bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1
-fieldset/ICR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: ISC
-    description: Interrupt semaphore x clear bit.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1
-fieldset/ISR:
-  description: HSEM Interrupt status register.
-  fields:
-  - name: ISF
-    description: Interrupt semaphore x status bit before enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1
-fieldset/MISR:
-  description: HSEM Masked interrupt status register.
-  fields:
-  - name: MISF
-    description: masked interrupt semaphore x status bit after enable (mask).
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 16
-      stride: 1

data/registers/hsem_v4.yaml

@@ -18,34 +18,34 @@ block/HSEM:
     fieldset: RLR
   - name: IER
     description: HSEM Interrupt enable register.
+    array:
+      len: 1
+      stride: 16
     byte_offset: 256
     fieldset: IER
-    array:
-      len: 1
-      stride: 16
   - name: ICR
     description: HSEM Interrupt clear register.
-    byte_offset: 260
-    fieldset: ICR
     array:
       len: 1
       stride: 16
+    byte_offset: 260
+    fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.
+    array:
+      len: 1
+      stride: 16
     byte_offset: 264
     access: Read
     fieldset: ISR
+  - name: MISR
+    description: HSEM Masked interrupt status register.
     array:
       len: 1
       stride: 16
-  - name: MISR
-    description: HSEM Masked interrupt status register.
     byte_offset: 268
     access: Read
     fieldset: MISR
-    array:
-      len: 1
-      stride: 16
   - name: CR
     description: HSEM Clear register.
     byte_offset: 320
@@ -55,6 +55,17 @@ block/HSEM:
     description: HSEM Interrupt clear register.
     byte_offset: 324
     fieldset: KEYR
+fieldset/CR:
+  description: HSEM Clear register.
+  fields:
+  - name: COREID
+    description: COREID.
+    bit_offset: 8
+    bit_size: 4
+  - name: KEY
+    description: Semaphore clear Key.
+    bit_offset: 16
+    bit_size: 16
 fieldset/ICR:
   description: HSEM Interrupt clear register.
   fields:
@@ -85,6 +96,13 @@ fieldset/ISR:
     array:
       len: 16
       stride: 1
+fieldset/KEYR:
+  description: HSEM Interrupt clear register.
+  fields:
+  - name: KEY
+    description: Semaphore Clear Key.
+    bit_offset: 16
+    bit_size: 16
 fieldset/MISR:
   description: HSEM Masked interrupt status register.
   fields:
@@ -95,24 +113,6 @@ fieldset/MISR:
     array:
       len: 16
       stride: 1
-fieldset/CR:
-  description: HSEM Clear register.
-  fields:
-  - name: COREID
-    description: COREID.
-    bit_offset: 8
-    bit_size: 4
-  - name: KEY
-    description: Semaphore clear Key.
-    bit_offset: 16
-    bit_size: 16
-fieldset/KEYR:
-  description: HSEM Interrupt clear register.
-  fields:
-  - name: KEY
-    description: Semaphore Clear Key.
-    bit_offset: 16
-    bit_size: 16
 fieldset/R:
   description: HSEM register HSEM_R%s HSEM_R31.
   fields:

data/registers/lpdma_v1.yaml

@@ -408,6 +408,15 @@ fieldset/SECCFGR:
     array:
       len: 16
       stride: 1
+enum/BREQ:
+  bit_size: 1
+  variants:
+  - name: Burst
+    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.
+    value: 0
+  - name: Block
+    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).
+    value: 1
 enum/DEC:
   bit_size: 1
   variants:
@@ -417,30 +426,15 @@ enum/DEC:
   - name: Subtract
     description: The address is decremented by the programmed offset.
     value: 1
-enum/LSM:
+enum/DREQ:
   bit_size: 1
   variants:
-  - name: RunToCompletion
+  - name: SourcePeripheral
-    description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.
+    description: selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port)
     value: 0
-  - name: LinkStep
+  - name: DestinationPeripheral
-    description: channel executed once for the current LLI
+    description: selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port)
     value: 1
-enum/PRIO:
-  bit_size: 2
-  variants:
-  - name: LowWithLowhWeight
-    description: low priority, low weight
-    value: 0
-  - name: LowWithMidWeight
-    description: low priority, mid weight
-    value: 1
-  - name: LowWithHighWeight
-    description: low priority, high weight
-    value: 2
-  - name: High
-    description: high priority
-    value: 3
 enum/DW:
   bit_size: 2
   variants:
@@ -453,6 +447,15 @@ enum/DW:
   - name: Word
     description: word (4 bytes)
     value: 2
+enum/LSM:
+  bit_size: 1
+  variants:
+  - name: RunToCompletion
+    description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.
+    value: 0
+  - name: LinkStep
+    description: channel executed once for the current LLI
+    value: 1
 enum/PAM:
   bit_size: 2
   variants:
@@ -469,24 +472,21 @@ enum/PAM:
   - name: Pack
     description: source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination
     value: 2
-enum/BREQ:
+enum/PRIO:
-  bit_size: 1
+  bit_size: 2
   variants:
-  - name: Burst
+  - name: LowWithLowhWeight
-    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.
+    description: low priority, low weight
     value: 0
-  - name: Block
+  - name: LowWithMidWeight
-    description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).
+    description: low priority, mid weight
-    value: 1
-enum/DREQ:
-  bit_size: 1
-  variants:
-  - name: SourcePeripheral
-    description: selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port)
-    value: 0
-  - name: DestinationPeripheral
-    description: selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port)
     value: 1
+  - name: LowWithHighWeight
+    description: low priority, high weight
+    value: 2
+  - name: High
+    description: high priority
+    value: 3
 enum/SWREQ:
   bit_size: 1
   variants:

data/registers/lptim_v2b.yaml

@@ -49,10 +49,10 @@ block/LPTIM:
     fieldset: RCR
   - name: CCMR
     description: LPTIM capture/compare mode register 1.
-    byte_offset: 44
     array:
       len: 2
       stride: 1
+    byte_offset: 44
     fieldset: CCMR
 fieldset/ARR:
   description: LPTIM autoreload register.

data/registers/rcc_h7ab.yaml

@@ -1871,7 +1871,7 @@ fieldset/CIFR:
     description: HSE ready Interrupt Flag
     bit_offset: 3
     bit_size: 1
-  - name: CSIRDY
+  - name: CSIRDYF
     description: CSI ready Interrupt Flag
     bit_offset: 4
     bit_size: 1

data/registers/rcc_u0.yaml

@@ -1047,25 +1047,6 @@ fieldset/DBGCFGR:
     description: Debug support reset Set and cleared by software.
     bit_offset: 1
     bit_size: 1
-fieldset/ICSCR:
-  description: Internal clock sources calibration register.
-  fields:
-  - name: MSICAL
-    description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
-    bit_offset: 0
-    bit_size: 8
-  - name: MSITRIM
-    description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.
-    bit_offset: 8
-    bit_size: 8
-  - name: HSICAL
-    description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
-    bit_offset: 16
-    bit_size: 8
-  - name: HSITRIM
-    description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%.
-    bit_offset: 24
-    bit_size: 7
 fieldset/GPIOENR:
   description: I/O port clock enable register.
   fields:
@@ -1147,6 +1128,25 @@ fieldset/GPIOSMENR:
     description: I/O port F clock enable during Sleep mode Set and cleared by software.
     bit_offset: 5
     bit_size: 1
+fieldset/ICSCR:
+  description: Internal clock sources calibration register.
+  fields:
+  - name: MSICAL
+    description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
+    bit_offset: 0
+    bit_size: 8
+  - name: MSITRIM
+    description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.
+    bit_offset: 8
+    bit_size: 8
+  - name: HSICAL
+    description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
+    bit_offset: 16
+    bit_size: 8
+  - name: HSITRIM
+    description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%.
+    bit_offset: 24
+    bit_size: 7
 fieldset/PLLCFGR:
   description: PLL configuration register.
   fields:

data/registers/spi_v3.yaml

@@ -31,34 +31,34 @@ block/SPI:
     byte_offset: 24
     access: Write
     fieldset: IFCR
+  - name: TXDR16
+    description: Transmit Data Register - half-word sized
+    byte_offset: 32
+    access: Write
+    bit_size: 16
   - name: TXDR32
     description: Transmit Data Register
     byte_offset: 32
     access: Write
-  - name: TXDR16
-    description: Transmit Data Register - half-word sized
-    byte_offset: 32
-    bit_size: 16
-    access: Write
   - name: TXDR8
     description: Transmit Data Register - byte sized
     byte_offset: 32
-    bit_size: 8
     access: Write
+    bit_size: 8
+  - name: RXDR16
+    description: Receive Data Register - half-word sized
+    byte_offset: 48
+    access: Read
+    bit_size: 16
   - name: RXDR32
     description: Receive Data Register
     byte_offset: 48
     access: Read
-  - name: RXDR16
-    description: Receive Data Register - half-word sized
-    byte_offset: 48
-    bit_size: 16
-    access: Read
   - name: RXDR8
     description: Receive Data Register - byte sized
     byte_offset: 48
-    bit_size: 8
     access: Read
+    bit_size: 8
   - name: CRCPOLY
     description: Polynomial Register
     byte_offset: 64

data/registers/spi_v4.yaml

@@ -31,34 +31,34 @@ block/SPI:
     byte_offset: 24
     access: Write
     fieldset: IFCR
+  - name: TXDR16
+    description: Transmit Data Register - half-word sized
+    byte_offset: 32
+    access: Write
+    bit_size: 16
   - name: TXDR32
     description: Transmit Data Register
     byte_offset: 32
     access: Write
-  - name: TXDR16
-    description: Transmit Data Register - half-word sized
-    byte_offset: 32
-    bit_size: 16
-    access: Write
   - name: TXDR8
     description: Transmit Data Register - byte sized
     byte_offset: 32
-    bit_size: 8
     access: Write
+    bit_size: 8
+  - name: RXDR16
+    description: Receive Data Register - half-word sized
+    byte_offset: 48
+    access: Read
+    bit_size: 16
   - name: RXDR32
     description: Receive Data Register
     byte_offset: 48
     access: Read
-  - name: RXDR16
-    description: Receive Data Register - half-word sized
-    byte_offset: 48
-    bit_size: 16
-    access: Read
   - name: RXDR8
     description: Receive Data Register - byte sized
     byte_offset: 48
-    bit_size: 8
     access: Read
+    bit_size: 8
   - name: CRCPOLY
     description: Polynomial Register
     byte_offset: 64

data/registers/spi_v5.yaml

@@ -34,34 +34,34 @@ block/SPI:
   - name: AUTOCR
     byte_offset: 28
     fieldset: AUTOCR
+  - name: TXDR16
+    description: Transmit Data Register - half-word sized
+    byte_offset: 32
+    access: Write
+    bit_size: 16
   - name: TXDR32
     description: Transmit Data Register
     byte_offset: 32
     access: Write
-  - name: TXDR16
-    description: Transmit Data Register - half-word sized
-    byte_offset: 32
-    bit_size: 16
-    access: Write
   - name: TXDR8
     description: Transmit Data Register - byte sized
     byte_offset: 32
-    bit_size: 8
     access: Write
+    bit_size: 8
+  - name: RXDR16
+    description: Receive Data Register - half-word sized
+    byte_offset: 48
+    access: Read
+    bit_size: 16
   - name: RXDR32
     description: Receive Data Register
     byte_offset: 48
     access: Read
-  - name: RXDR16
-    description: Receive Data Register - half-word sized
-    byte_offset: 48
-    bit_size: 16
-    access: Read
   - name: RXDR8
     description: Receive Data Register - byte sized
     byte_offset: 48
-    bit_size: 8
     access: Read
+    bit_size: 8
   - name: CRCPOLY
     description: Polynomial Register
     byte_offset: 64