diff --git a/.gitignore b/.gitignore
index b7337d0..980f11a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,7 +3,9 @@
/sources
/tmp
.idea/
+.DS_Store
# transform*.yaml
__pycache__
-target/
\ No newline at end of file
+target/
+venv/
\ No newline at end of file
diff --git a/.vscode/settings.json b/.vscode/settings.json
index ee57673..1ecdb3f 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -3,6 +3,9 @@
"[toml]": {
"editor.formatOnSave": false
},
+ "[yaml]": {
+ "editor.formatOnSave": false
+ },
"[c]": {
"editor.formatOnSave": false
},
diff --git a/d b/d
index 74ac3dc..97996ca 100755
--- a/d
+++ b/d
@@ -4,7 +4,7 @@ set -e
cd $(dirname $0)
CMD=$1
-REV=796a8322b8f6e4329002a1fb49438aec95dae812
+REV=74b97817d4c4ed0db9d19a8eac46720b3c5b0d57
shift
case "$CMD" in
@@ -56,7 +56,7 @@ case "$CMD" in
cargo run --release --bin stm32-data-gen
cargo run --release --bin stm32-metapac-gen
cd build/stm32-metapac
- find . -name '*.rs' -not -path '*target*' | xargs rustfmt --skip-children --unstable-features --edition 2021
+ #find . -name '*.rs' -not -path '*target*' | xargs rustfmt --skip-children --unstable-features --edition 2021
cargo check --features stm32h755zi-cm7,pac,metadata
cargo check --features stm32f777zi,pac
cargo check --features stm32u585zi,metadata
@@ -65,4 +65,3 @@ case "$CMD" in
echo "unknown command"
;;
esac
-
diff --git a/data/dmamux/U0_DMAMUX1.yaml b/data/dmamux/U0_DMAMUX1.yaml
new file mode 100644
index 0000000..a3ac8a3
--- /dev/null
+++ b/data/dmamux/U0_DMAMUX1.yaml
@@ -0,0 +1,76 @@
+GENERATOR0: 1
+GENERATOR1: 2
+GENERATOR2: 3
+GENERATOR3: 4
+ADC1: 5
+AES_IN: 6
+AES_OUT: 7
+DAC1_CH1: 8
+I2C1_RX: 9
+I2C1_TX: 10
+I2C2_RX: 11
+I2C2_TX: 12
+I2C3_RX: 13
+I2C3_TX: 14
+I2C4_RX: 15
+I2C4_TX: 16
+LPTIM1_IC1: 17
+LPTIM1_IC2: 18
+LPTIM1_IC3: 19
+LPTIM1_IC4: 20
+LPTIM1_UE4: 21
+LPTIM2_IC1: 22
+LPTIM2_IC2: 23
+LPTIM2_UE: 24
+LPTIM3_IC1: 25
+LPTIM3_IC2: 26
+LPTIM3_IC3: 27
+LPTIM3_IC4: 28
+LPTIM3_UE: 29
+LPUART1_RX: 30
+LPUART1_TX: 31
+LPUART2_RX: 32
+LPUART2_TX: 33
+LPUART3_RX: 34
+LPUART3_TX: 35
+SPI1_RX: 36
+SPI1_TX: 37
+SPI2_RX: 38
+SPI2_TX: 39
+SPI3_RX: 40
+SPI3_TX: 41
+TIM1_CH1: 42
+TIM1_CH2: 43
+TIM1_CH3: 44
+TIM1_CH4: 45
+TIM1_TRIG_COM: 46
+TIM1_UP: 47
+TIM2_CH1: 48
+TIM2_CH2: 49
+TIM2_CH3: 50
+TIM2_CH4: 51
+TIM2_TRIG: 52
+TIM2_UP: 53
+TIM3_CH1: 54
+TIM3_CH2: 55
+TIM3_CH3: 56
+TIM3_CH4: 57
+TIM3_TRIG: 58
+TIM3_UP: 59
+TIM6_UP: 60
+TIM7_UP: 61
+TIM15_CH1: 62
+TIM15_CH2: 63
+TIM15_TRIG_COM: 64
+TIM15_UP: 65
+TIM16_CH1: 66
+TIM16_COM: 67
+TIM16_UP: 68
+USART1_RX: 69
+USART1_TX: 70
+USART2_RX: 71
+USART2_TX: 72
+USART3_RX: 73
+USART3_TX: 74
+USART4_RX: 75
+USART4_TX: 76
\ No newline at end of file
diff --git a/data/registers/adc_g4.yaml b/data/registers/adc_g4.yaml
new file mode 100644
index 0000000..57b75d3
--- /dev/null
+++ b/data/registers/adc_g4.yaml
@@ -0,0 +1,743 @@
+block/ADC:
+ description: Analog to Digital Converter
+ items:
+ - name: ISR
+ description: interrupt and status register
+ byte_offset: 0
+ fieldset: ISR
+ - name: IER
+ description: interrupt enable register
+ byte_offset: 4
+ fieldset: IER
+ - name: CR
+ description: control register
+ byte_offset: 8
+ fieldset: CR
+ - name: CFGR
+ description: configuration register 1
+ byte_offset: 12
+ fieldset: CFGR
+ - name: CFGR2
+ description: configuration register 2
+ byte_offset: 16
+ fieldset: CFGR2
+ - name: SMPR
+ description: sampling time register 1
+ byte_offset: 20
+ fieldset: SMPR
+ - name: SMPR2
+ description: sampling time register 2
+ byte_offset: 24
+ fieldset: SMPR2
+ - name: TR1
+ description: analog watchdog threshold register 1
+ byte_offset: 32
+ fieldset: TR1
+ - name: TR2
+ description: analog watchdog threshold register 2
+ byte_offset: 36
+ fieldset: TR2
+ - name: TR3
+ description: analog watchdog threshold register 3
+ byte_offset: 40
+ fieldset: TR3
+ - name: SQR1
+ description: group regular sequencer ranks register 1
+ byte_offset: 48
+ fieldset: SQR1
+ - name: SQR2
+ description: group regular sequencer ranks register 2
+ byte_offset: 52
+ fieldset: SQR2
+ - name: SQR3
+ description: group regular sequencer ranks register 3
+ byte_offset: 56
+ fieldset: SQR3
+ - name: SQR4
+ description: group regular sequencer ranks register 4
+ byte_offset: 60
+ fieldset: SQR4
+ - name: DR
+ description: group regular conversion data register
+ byte_offset: 64
+ access: Read
+ fieldset: DR
+ - name: JSQR
+ description: group injected sequencer register
+ byte_offset: 76
+ fieldset: JSQR
+ - name: OFR
+ description: offset number 1-4 register
+ array:
+ len: 4
+ stride: 4
+ byte_offset: 96
+ fieldset: OFR
+ - name: JDR
+ description: group injected sequencer rank 1-4 register
+ array:
+ len: 4
+ stride: 4
+ byte_offset: 128
+ access: Read
+ fieldset: JDR
+ - name: AWD2CR
+ description: analog watchdog 2 configuration register
+ byte_offset: 160
+ fieldset: AWD2CR
+ - name: AWD3CR
+ description: analog watchdog 3 configuration register
+ byte_offset: 164
+ fieldset: AWD3CR
+ - name: DIFSEL
+ description: channel differential or single-ended mode selection register
+ byte_offset: 176
+ fieldset: DIFSEL
+ - name: CALFACT
+ description: calibration factors register
+ byte_offset: 180
+ fieldset: CALFACT
+ - name: GCOMP
+ description: Gain compensation register
+ byte_offset: 192
+ fieldset: GCOMP
+fieldset/AWD2CR:
+ description: analog watchdog 2 configuration register
+ fields:
+ - name: AWD2CH
+ description: analog watchdog 2 channel selection
+ bit_offset: 0
+ bit_size: 19
+fieldset/AWD3CR:
+ description: analog watchdog 3 configuration register
+ fields:
+ - name: AWD3CH
+ description: analog watchdog 3 channel selection
+ bit_offset: 0
+ bit_size: 19
+fieldset/CALFACT:
+ description: calibration factors register
+ fields:
+ - name: CALFACT_S
+ description: calibration factor in single-ended mode
+ bit_offset: 0
+ bit_size: 7
+ - name: CALFACT_D
+ description: calibration factor in differential mode
+ bit_offset: 16
+ bit_size: 7
+fieldset/CFGR:
+ description: configuration register 1
+ fields:
+ - name: DMAEN
+ description: Direct memory access enable
+ bit_offset: 0
+ bit_size: 1
+ enum: DMAEN
+ - name: DMACFG
+ description: direct memory access configuration
+ bit_offset: 0
+ bit_size: 1
+ enum: DMACFG
+ - name: RES
+ description: data resolution
+ bit_offset: 3
+ bit_size: 2
+ enum: RES
+ - name: EXTSEL
+ description: external trigger selection for regular group
+ bit_offset: 5
+ bit_size: 5
+ - name: EXTEN
+ description: external trigger enable and polarity selection for regular channels
+ bit_offset: 10
+ bit_size: 2
+ enum: EXTEN
+ - name: OVRMOD
+ description: overrun mode
+ bit_offset: 12
+ bit_size: 1
+ enum: OVRMOD
+ - name: CONT
+ description: single / continuous conversion mode for regular conversions
+ bit_offset: 13
+ bit_size: 1
+ - name: AUTDLY
+ description: delayed conversion mode
+ bit_offset: 14
+ bit_size: 1
+ - name: ALIGN
+ description: data alignment
+ bit_offset: 15
+ bit_size: 1
+ - name: DISCEN
+ description: discontinuous mode for regular channels
+ bit_offset: 16
+ bit_size: 1
+ - name: DISCNUM
+ description: discontinuous mode channel count
+ bit_offset: 17
+ bit_size: 3
+ - name: JDISCEN
+ description: discontinuous mode on injected channels
+ bit_offset: 20
+ bit_size: 1
+ - name: JQM
+ description: JSQR queue mode
+ bit_offset: 21
+ bit_size: 1
+ enum: JQM
+ - name: AWD1SGL
+ description: enable the watchdog 1 on a single channel or on all channels
+ bit_offset: 22
+ bit_size: 1
+ enum: AWD1SGL
+ - name: AWD1EN
+ description: analog watchdog 1 enable on regular channels
+ bit_offset: 23
+ bit_size: 1
+ - name: JAWD1EN
+ description: analog watchdog 1 enable on injected channels
+ bit_offset: 24
+ bit_size: 1
+ - name: JAUTO
+ description: automatic injected group conversion
+ bit_offset: 25
+ bit_size: 1
+ - name: AWD1CH
+ description: analog watchdog 1 channel selection
+ bit_offset: 26
+ bit_size: 5
+ - name: JQDIS
+ description: injected queue disable
+ bit_offset: 31
+ bit_size: 1
+fieldset/CFGR2:
+ description: configuration register 2
+ fields:
+ - name: ROVSE
+ description: Regular Oversampling Enable
+ bit_offset: 0
+ bit_size: 1
+ - name: JOVSE
+ description: Injected Oversampling Enable
+ bit_offset: 1
+ bit_size: 1
+ - name: OVSR
+ description: Oversampling ratio
+ bit_offset: 2
+ bit_size: 3
+ - name: OVSS
+ description: Oversampling shift
+ bit_offset: 5
+ bit_size: 4
+ - name: TROVS
+ description: Triggered Regular Oversampling
+ bit_offset: 9
+ bit_size: 1
+ enum: TROVS
+ - name: ROVSM
+ description: Regular Oversampling mode
+ bit_offset: 10
+ bit_size: 1
+ enum: ROVSM
+ - name: GCOMP
+ description: Gain compensation mode
+ bit_offset: 16
+ bit_size: 1
+ - name: SWTRIG
+ description: Software trigger bit for sampling time control trigger mode
+ bit_offset: 25
+ bit_size: 1
+ - name: BULB
+ description: Bulb sampling mode
+ bit_offset: 26
+ bit_size: 1
+ - name: SMPTRIG
+ description: Sampling time control trigger mode
+ bit_offset: 27
+ bit_size: 1
+fieldset/CR:
+ description: control register
+ fields:
+ - name: ADEN
+ description: enable
+ bit_offset: 0
+ bit_size: 1
+ - name: ADDIS
+ description: disable
+ bit_offset: 1
+ bit_size: 1
+ - name: ADSTART
+ description: group regular conversion start
+ bit_offset: 2
+ bit_size: 1
+ - name: JADSTART
+ description: group injected conversion start
+ bit_offset: 3
+ bit_size: 1
+ - name: ADSTP
+ description: group regular conversion stop
+ bit_offset: 4
+ bit_size: 1
+ enum: ADSTP
+ - name: JADSTP
+ description: group injected conversion stop
+ bit_offset: 5
+ bit_size: 1
+ enum: ADSTP
+ - name: ADVREGEN
+ description: voltage regulator enable
+ bit_offset: 28
+ bit_size: 1
+ - name: DEEPPWD
+ description: deep power down enable
+ bit_offset: 29
+ bit_size: 1
+ - name: ADCALDIF
+ description: differential mode for calibration
+ bit_offset: 30
+ bit_size: 1
+ enum: ADCALDIF
+ - name: ADCAL
+ description: calibration
+ bit_offset: 31
+ bit_size: 1
+fieldset/DIFSEL:
+ description: channel differential or single-ended mode selection register
+ fields:
+ - name: DIFSEL
+ description: channel differential or single-ended mode for channel
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 18
+ stride: 1
+ enum: DIFSEL
+fieldset/DR:
+ description: group regular conversion data register
+ fields:
+ - name: RDATA
+ description: group regular conversion data
+ bit_offset: 0
+ bit_size: 16
+fieldset/IER:
+ description: interrupt enable register
+ fields:
+ - name: ADRDYIE
+ description: ready interrupt
+ bit_offset: 0
+ bit_size: 1
+ - name: EOSMPIE
+ description: group regular end of sampling interrupt
+ bit_offset: 1
+ bit_size: 1
+ - name: EOCIE
+ description: group regular end of unitary conversion interrupt
+ bit_offset: 2
+ bit_size: 1
+ - name: EOSIE
+ description: group regular end of sequence conversions interrupt
+ bit_offset: 3
+ bit_size: 1
+ - name: OVRIE
+ description: group regular overrun interrupt
+ bit_offset: 4
+ bit_size: 1
+ - name: JEOCIE
+ description: group injected end of unitary conversion interrupt
+ bit_offset: 5
+ bit_size: 1
+ - name: JEOSIE
+ description: group injected end of sequence conversions interrupt
+ bit_offset: 6
+ bit_size: 1
+ - name: AWD1IE
+ description: analog watchdog 1 interrupt
+ bit_offset: 7
+ bit_size: 1
+ - name: AWD2IE
+ description: analog watchdog 2 interrupt
+ bit_offset: 8
+ bit_size: 1
+ - name: AWD3IE
+ description: analog watchdog 3 interrupt
+ bit_offset: 9
+ bit_size: 1
+ - name: JQOVFIE
+ description: group injected contexts queue overflow interrupt
+ bit_offset: 10
+ bit_size: 1
+fieldset/ISR:
+ description: interrupt and status register
+ fields:
+ - name: ADRDY
+ description: ready flag
+ bit_offset: 0
+ bit_size: 1
+ - name: EOSMP
+ description: group regular end of sampling flag
+ bit_offset: 1
+ bit_size: 1
+ - name: EOC
+ description: group regular end of unitary conversion flag
+ bit_offset: 2
+ bit_size: 1
+ - name: EOS
+ description: group regular end of sequence conversions flag
+ bit_offset: 3
+ bit_size: 1
+ - name: OVR
+ description: group regular overrun flag
+ bit_offset: 4
+ bit_size: 1
+ - name: JEOC
+ description: group injected end of unitary conversion flag
+ bit_offset: 5
+ bit_size: 1
+ - name: JEOS
+ description: group injected end of sequence conversions flag
+ bit_offset: 6
+ bit_size: 1
+ - name: AWD1
+ description: analog watchdog 1 flag
+ bit_offset: 7
+ bit_size: 1
+ - name: AWD2
+ description: analog watchdog 2 flag
+ bit_offset: 8
+ bit_size: 1
+ - name: AWD3
+ description: analog watchdog 3 flag
+ bit_offset: 9
+ bit_size: 1
+ - name: JQOVF
+ description: group injected contexts queue overflow flag
+ bit_offset: 10
+ bit_size: 1
+fieldset/JDR:
+ description: group injected sequencer rank 1-4 register
+ fields:
+ - name: JDATA
+ description: group injected sequencer rank conversion data
+ bit_offset: 0
+ bit_size: 16
+fieldset/JSQR:
+ description: group injected sequencer register
+ fields:
+ - name: JL
+ description: group injected sequencer scan length
+ bit_offset: 0
+ bit_size: 2
+ - name: JEXTSEL
+ description: group injected external trigger source
+ bit_offset: 2
+ bit_size: 5
+ - name: JEXTEN
+ description: group injected external trigger polarity
+ bit_offset: 7
+ bit_size: 2
+ enum: JEXTEN
+ - name: JSQ
+ description: group injected sequencer rank 1-4
+ bit_offset: 9
+ bit_size: 5
+ array:
+ len: 4
+ stride: 6
+fieldset/TR1:
+ description: analog watchdog threshold register 1
+ fields:
+ - name: LT1
+ description: analog watchdog 1 lower threshold
+ bit_offset: 0
+ bit_size: 12
+ - name: AWDFILT
+ description: analog watchdog filtering parameter
+ bit_offset: 12
+ bit_size: 3
+ - name: HT1
+ description: analog watchdog 1 higher threshold
+ bit_offset: 16
+ bit_size: 12
+fieldset/TR2:
+ description: analog watchdog threshold register 2
+ fields:
+ - name: LT2
+ description: analog watchdog 2 lower threshold
+ bit_offset: 0
+ bit_size: 8
+ - name: HT2
+ description: analog watchdog 2 higher threshold
+ bit_offset: 16
+ bit_size: 8
+fieldset/TR3:
+ description: analog watchdog threshold register 3
+ fields:
+ - name: LT3
+ description: analog watchdog 3 lower threshold
+ bit_offset: 0
+ bit_size: 8
+ - name: HT3
+ description: analog watchdog 3 higher threshold
+ bit_offset: 16
+ bit_size: 8
+fieldset/OFR:
+ description: offset number x register
+ fields:
+ - name: OFFSET
+ description: data offset
+ bit_offset: 0
+ bit_size: 12
+ - name: OFFSETPOS
+ description: Positive offset
+ bit_offset: 24
+ bit_size: 1
+ - name: SATEN
+ description: Saturation enable
+ bit_offset: 25
+ bit_size: 1
+ - name: OFFSET1_CH
+ description: Channel selection for the data offset
+ bit_offset: 26
+ bit_size: 5
+ - name: OFFSET_EN
+ description: Offset enable
+ bit_offset: 31
+ bit_size: 1
+fieldset/SMPR:
+ description: sampling time register
+ fields:
+ - name: SMP
+ description: channel n * 10 + x sampling time
+ bit_offset: 0
+ bit_size: 3
+ array:
+ len: 10
+ stride: 3
+ enum: SAMPLE_TIME
+ - name: SMPPLUS
+ description: Addition of one clock cycle to the sampling time
+ bit_offset: 31
+ bit_size: 1
+fieldset/SMPR2:
+ description: sampling time register
+ fields:
+ - name: SMP
+ description: channel n * 10 + x sampling time
+ bit_offset: 0
+ bit_size: 3
+ array:
+ len: 9
+ stride: 3
+ enum: SAMPLE_TIME
+fieldset/SQR1:
+ description: group regular sequencer ranks register 1
+ fields:
+ - name: L
+ description: L
+ bit_offset: 0
+ bit_size: 4
+ - name: SQ
+ description: group regular sequencer rank 1-4
+ bit_offset: 6
+ bit_size: 5
+ array:
+ len: 4
+ stride: 6
+fieldset/SQR2:
+ description: group regular sequencer ranks register 2
+ fields:
+ - name: SQ
+ description: group regular sequencer rank 5-9
+ bit_offset: 0
+ bit_size: 5
+ array:
+ len: 5
+ stride: 6
+fieldset/SQR3:
+ description: group regular sequencer ranks register 3
+ fields:
+ - name: SQ
+ description: group regular sequencer rank 10-14
+ bit_offset: 0
+ bit_size: 5
+ array:
+ len: 5
+ stride: 6
+fieldset/SQR4:
+ description: group regular sequencer ranks register 4
+ fields:
+ - name: SQ
+ description: group regular sequencer rank 15-16
+ bit_offset: 0
+ bit_size: 5
+ array:
+ len: 2
+ stride: 6
+fieldset/GCOMP:
+ description: Gain compensation coefficient
+ fields:
+ - name: GCOMPCOEFF
+ description: Gain compensation coefficient
+ bit_offset: 0
+ bit_size: 14
+enum/ADCALDIF:
+ bit_size: 1
+ variants:
+ - name: SingleEnded
+ description: Calibration for single-ended mode
+ value: 0
+ - name: Differential
+ description: Calibration for differential mode
+ value: 1
+enum/ADSTP:
+ bit_size: 1
+ variants:
+ - name: Stop
+ description: Stop conversion of channel
+ value: 1
+enum/AWD1SGL:
+ bit_size: 1
+ variants:
+ - name: All
+ description: Analog watchdog 1 enabled on all channels
+ value: 0
+ - name: Single
+ description: Analog watchdog 1 enabled on single channel selected in AWD1CH
+ value: 1
+enum/DIFSEL:
+ bit_size: 1
+ variants:
+ - name: SingleEnded
+ description: Input channel is configured in single-ended mode
+ value: 0
+ - name: Differential
+ description: Input channel is configured in differential mode
+ value: 1
+enum/DMAEN:
+ bit_size: 1
+ variants:
+ - name: Disable
+ description: DMA disable
+ value: 0
+ - name: Enable
+ description: DMA enable
+ value: 1
+enum/DMACFG:
+ bit_size: 1
+ variants:
+ - name: OneShotMode
+ description: DMA One Shot mode selected
+ value: 0
+ - name: CircularMode
+ description: DMA Circular mode selected
+ value: 1
+enum/EXTEN:
+ bit_size: 2
+ variants:
+ - name: Disabled
+ description: Trigger detection disabled
+ value: 0
+ - name: RisingEdge
+ description: Trigger detection on the rising edge
+ value: 1
+ - name: FallingEdge
+ description: Trigger detection on the falling edge
+ value: 2
+ - name: BothEdges
+ description: Trigger detection on both the rising and falling edges
+ value: 3
+enum/JEXTEN:
+ bit_size: 2
+ variants:
+ - name: Disabled
+ description: Trigger detection disabled
+ value: 0
+ - name: RisingEdge
+ description: Trigger detection on the rising edge
+ value: 1
+ - name: FallingEdge
+ description: Trigger detection on the falling edge
+ value: 2
+ - name: BothEdges
+ description: Trigger detection on both the rising and falling edges
+ value: 3
+enum/JQM:
+ bit_size: 1
+ variants:
+ - name: Mode0
+ description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
+ value: 0
+ - name: Mode1
+ description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
+ value: 1
+enum/OVRMOD:
+ bit_size: 1
+ variants:
+ - name: Preserve
+ description: Preserve DR register when an overrun is detected
+ value: 0
+ - name: Overwrite
+ description: Overwrite DR register when an overrun is detected
+ value: 1
+enum/RES:
+ bit_size: 2
+ variants:
+ - name: Bits12
+ description: 12-bit resolution
+ value: 0
+ - name: Bits10
+ description: 10-bit resolution
+ value: 1
+ - name: Bits8
+ description: 8-bit resolution
+ value: 2
+ - name: Bits6
+ description: 6-bit resolution
+ value: 3
+enum/ROVSM:
+ bit_size: 1
+ variants:
+ - name: Continued
+ description: Oversampling is temporary stopped and continued after injection sequence
+ value: 0
+ - name: Resumed
+ description: Oversampling is aborted and resumed from start after injection sequence
+ value: 1
+enum/SAMPLE_TIME:
+ bit_size: 3
+ variants:
+ - name: Cycles2_5
+ description: 2.5 clock cycles
+ value: 0
+ - name: Cycles6_5
+ description: 6.5 clock cycles
+ value: 1
+ - name: Cycles12_5
+ description: 12.5 clock cycles
+ value: 2
+ - name: Cycles24_5
+ description: 24.5 clock cycles
+ value: 3
+ - name: Cycles47_5
+ description: 47.5 clock cycles
+ value: 4
+ - name: Cycles92_5
+ description: 92.5 clock cycles
+ value: 5
+ - name: Cycles247_5
+ description: 247.5 clock cycles
+ value: 6
+ - name: Cycles640_5
+ description: 640.5 clock cycles
+ value: 7
+enum/TROVS:
+ bit_size: 1
+ variants:
+ - name: Automatic
+ description: All oversampled conversions for a channel are done consecutively following a trigger
+ value: 0
+ - name: Triggered
+ description: Each oversampled conversion for a channel needs a new trigger
+ value: 1
\ No newline at end of file
diff --git a/data/registers/crc_v2.yaml b/data/registers/crc_v2.yaml
index 8b6ef63..6616d3e 100644
--- a/data/registers/crc_v2.yaml
+++ b/data/registers/crc_v2.yaml
@@ -1,7 +1,7 @@
block/CRC:
description: Cyclic Redundancy Check calculation unit
items:
- - name: DR
+ - name: DR32
description: Data register
byte_offset: 0
- name: DR16
diff --git a/data/registers/crc_v3.yaml b/data/registers/crc_v3.yaml
index 1686d66..9cb0a16 100644
--- a/data/registers/crc_v3.yaml
+++ b/data/registers/crc_v3.yaml
@@ -1,7 +1,7 @@
block/CRC:
description: Cyclic Redundancy Check calculation unit
items:
- - name: DR
+ - name: DR32
description: Data register
byte_offset: 0
- name: DR16
diff --git a/data/registers/exti_u0.yaml b/data/registers/exti_u0.yaml
new file mode 100644
index 0000000..4360d95
--- /dev/null
+++ b/data/registers/exti_u0.yaml
@@ -0,0 +1,79 @@
+block/EXTI:
+ description: External interrupt/event controller
+ items:
+ - name: RTSR
+ description: Rising Trigger selection register
+ array:
+ len: 1
+ stride: 40
+ byte_offset: 0
+ fieldset: LINES
+ - name: FTSR
+ description: Falling Trigger selection register
+ array:
+ len: 1
+ stride: 40
+ byte_offset: 4
+ fieldset: LINES
+ - name: SWIER
+ description: Software interrupt event register
+ array:
+ len: 1
+ stride: 40
+ byte_offset: 8
+ fieldset: LINES
+ - name: RPR
+ description: Rising pending register
+ array:
+ len: 1
+ stride: 40
+ byte_offset: 12
+ fieldset: LINES
+ - name: FPR
+ description: Falling pending register
+ array:
+ len: 1
+ stride: 40
+ byte_offset: 16
+ fieldset: LINES
+ - name: EXTICR
+ description: Configuration register
+ array:
+ len: 4
+ stride: 4
+ byte_offset: 96
+ fieldset: EXTICR
+ - name: IMR
+ description: Interrupt mask register
+ array:
+ len: 2
+ stride: 16
+ byte_offset: 128
+ fieldset: LINES
+ - name: EMR
+ description: Event mask register
+ array:
+ len: 2
+ stride: 16
+ byte_offset: 132
+ fieldset: LINES
+fieldset/EXTICR:
+ description: external interrupt configuration register 1
+ fields:
+ - name: EXTI
+ description: EXTI configuration bits
+ bit_offset: 0
+ bit_size: 8
+ array:
+ len: 4
+ stride: 8
+fieldset/LINES:
+ description: EXTI lines register, 1 bit per line
+ fields:
+ - name: LINE
+ description: EXTI line
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
diff --git a/data/registers/flash_g4.yaml b/data/registers/flash_g4c2.yaml
similarity index 100%
rename from data/registers/flash_g4.yaml
rename to data/registers/flash_g4c2.yaml
diff --git a/data/registers/flash_g4c3.yaml b/data/registers/flash_g4c3.yaml
new file mode 100644
index 0000000..5ef2785
--- /dev/null
+++ b/data/registers/flash_g4c3.yaml
@@ -0,0 +1,414 @@
+block/FLASH:
+ description: Flash
+ items:
+ - name: ACR
+ description: Access control register
+ byte_offset: 0
+ fieldset: ACR
+ - name: PDKEYR
+ description: Power down key register
+ byte_offset: 4
+ access: Write
+ - name: KEYR
+ description: Flash key register
+ byte_offset: 8
+ access: Write
+ - name: OPTKEYR
+ description: Option byte key register
+ byte_offset: 12
+ access: Write
+ - name: SR
+ description: Status register
+ byte_offset: 16
+ fieldset: SR
+ - name: CR
+ description: Flash control register
+ byte_offset: 20
+ fieldset: CR
+ - name: ECCR
+ description: Flash ECC register
+ byte_offset: 24
+ fieldset: ECCR
+ - name: OPTR
+ description: Flash option register
+ byte_offset: 32
+ fieldset: OPTR
+ - name: PCROP1SR
+ description: Flash Bank 1 PCROP Start address register
+ byte_offset: 36
+ fieldset: PCROP1SR
+ - name: PCROP1ER
+ description: Flash Bank 1 PCROP End address register
+ byte_offset: 40
+ fieldset: PCROP1ER
+ - name: WRP1AR
+ description: Flash Bank 1 WRP area A address register
+ byte_offset: 44
+ fieldset: WRP1AR
+ - name: WRP1BR
+ description: Flash Bank 1 WRP area B address register
+ byte_offset: 48
+ fieldset: WRP1BR
+ - name: SEC1R
+ description: securable area bank1 register
+ byte_offset: 112
+ fieldset: SEC1R
+fieldset/ACR:
+ description: Access control register
+ fields:
+ - name: LATENCY
+ description: Latency
+ bit_offset: 0
+ bit_size: 4
+ enum: LATENCY
+ - name: PRFTEN
+ description: Prefetch enable
+ bit_offset: 8
+ bit_size: 1
+ - name: ICEN
+ description: Instruction cache enable
+ bit_offset: 9
+ bit_size: 1
+ - name: DCEN
+ description: Data cache enable
+ bit_offset: 10
+ bit_size: 1
+ - name: ICRST
+ description: Instruction cache reset
+ bit_offset: 11
+ bit_size: 1
+ - name: DCRST
+ description: Data cache reset
+ bit_offset: 12
+ bit_size: 1
+ - name: RUN_PD
+ description: Flash Power-down mode during Low-power run mode
+ bit_offset: 13
+ bit_size: 1
+ - name: SLEEP_PD
+ description: Flash Power-down mode during Low-power sleep mode
+ bit_offset: 14
+ bit_size: 1
+ - name: DBG_SWEN
+ description: Debug software enable
+ bit_offset: 18
+ bit_size: 1
+fieldset/CR:
+ description: Flash control register
+ fields:
+ - name: PG
+ description: Programming
+ bit_offset: 0
+ bit_size: 1
+ - name: PER
+ description: Page erase
+ bit_offset: 1
+ bit_size: 1
+ - name: MER1
+ description: Bank 1 Mass erase
+ bit_offset: 2
+ bit_size: 1
+ - name: PNB
+ description: Page number
+ bit_offset: 3
+ bit_size: 7
+ - name: MER2
+ description: Bank 2 Mass erase
+ bit_offset: 15
+ bit_size: 1
+ - name: STRT
+ description: Start
+ bit_offset: 16
+ bit_size: 1
+ - name: OPTSTRT
+ description: Options modification start
+ bit_offset: 17
+ bit_size: 1
+ - name: FSTPG
+ description: Fast programming
+ bit_offset: 18
+ bit_size: 1
+ - name: EOPIE
+ description: End of operation interrupt enable
+ bit_offset: 24
+ bit_size: 1
+ - name: ERRIE
+ description: Error interrupt enable
+ bit_offset: 25
+ bit_size: 1
+ - name: RDERRIE
+ description: PCROP read error interrupt enable
+ bit_offset: 26
+ bit_size: 1
+ - name: OBL_LAUNCH
+ description: Force the option byte loading
+ bit_offset: 27
+ bit_size: 1
+ - name: SEC_PROT1
+ description: Securable memory area protection enable
+ bit_offset: 28
+ bit_size: 1
+ - name: OPTLOCK
+ description: Options Lock
+ bit_offset: 30
+ bit_size: 1
+ - name: LOCK
+ description: FLASH_CR Lock
+ bit_offset: 31
+ bit_size: 1
+fieldset/ECCR:
+ description: Flash ECC register
+ fields:
+ - name: ADDR_ECC
+ description: ECC fail address
+ bit_offset: 0
+ bit_size: 19
+ - name: BK_ECC
+ description: ECC fail for Corrected ECC Error or Double ECC Error in info block
+ bit_offset: 21
+ bit_size: 1
+ - name: SYSF_ECC
+ description: ECC fail for Corrected ECC Error or Double ECC Error in info block
+ bit_offset: 22
+ bit_size: 1
+ - name: ECCIE
+ description: ECC correction interrupt enable
+ bit_offset: 24
+ bit_size: 1
+ - name: ECCC2
+ description: ECC correction
+ bit_offset: 28
+ bit_size: 1
+ - name: ECCD2
+ description: ECC2 detection
+ bit_offset: 29
+ bit_size: 1
+ - name: ECCC
+ description: ECC correction
+ bit_offset: 30
+ bit_size: 1
+ - name: ECCD
+ description: ECC detection
+ bit_offset: 31
+ bit_size: 1
+fieldset/OPTR:
+ description: Flash option register
+ fields:
+ - name: RDP
+ description: Read protection level
+ bit_offset: 0
+ bit_size: 8
+ enum: RDP
+ - name: BOR_LEV
+ description: BOR reset Level
+ bit_offset: 8
+ bit_size: 3
+ - name: nRST_STOP
+ description: nRST_STOP
+ bit_offset: 12
+ bit_size: 1
+ - name: nRST_STDBY
+ description: nRST_STDBY
+ bit_offset: 13
+ bit_size: 1
+ - name: nRST_SHDW
+ description: nRST_SHDW
+ bit_offset: 14
+ bit_size: 1
+ - name: IDWG_SW
+ description: Independent watchdog selection
+ bit_offset: 16
+ bit_size: 1
+ - name: IWDG_STOP
+ description: Independent watchdog counter freeze in Stop mode
+ bit_offset: 17
+ bit_size: 1
+ - name: IWDG_STDBY
+ description: Independent watchdog counter freeze in Standby mode
+ bit_offset: 18
+ bit_size: 1
+ - name: WWDG_SW
+ description: Window watchdog selection
+ bit_offset: 19
+ bit_size: 1
+ - name: BFB2
+ description: Dual bank boot
+ bit_offset: 20
+ bit_size: 1
+ - name: DBANK
+ description: Dual bank memory mode
+ bit_offset: 22
+ bit_size: 1
+ - name: nBOOT1
+ description: Boot configuration
+ bit_offset: 23
+ bit_size: 1
+ - name: SRAM2_PE
+ description: SRAM2 parity check enable
+ bit_offset: 24
+ bit_size: 1
+ - name: SRAM2_RST
+ description: SRAM2 Erase when system reset
+ bit_offset: 25
+ bit_size: 1
+ - name: nSWBOOT0
+ description: nSWBOOT0
+ bit_offset: 26
+ bit_size: 1
+ - name: nBOOT0
+ description: nBOOT0 option bit
+ bit_offset: 27
+ bit_size: 1
+ - name: NRST_MODE
+ description: NRST_MODE
+ bit_offset: 28
+ bit_size: 2
+ enum: NRST_MODE
+ - name: IRHEN
+ description: Internal reset holder enable bit
+ bit_offset: 30
+ bit_size: 1
+fieldset/PCROP1ER:
+ description: Flash Bank 1 PCROP End address register
+ fields:
+ - name: PCROP1_END
+ description: Bank 1 PCROP area end offset
+ bit_offset: 0
+ bit_size: 15
+ - name: PCROP_RDP
+ description: PCROP area preserved when RDP level decreased
+ bit_offset: 31
+ bit_size: 1
+fieldset/PCROP1SR:
+ description: Flash Bank 1 PCROP Start address register
+ fields:
+ - name: PCROP1_STRT
+ description: Bank 1 PCROP area start offset
+ bit_offset: 0
+ bit_size: 15
+fieldset/SEC1R:
+ description: securable area bank1 register
+ fields:
+ - name: SEC_SIZE1
+ description: SEC_SIZE1
+ bit_offset: 0
+ bit_size: 8
+ - name: BOOT_LOCK
+ description: used to force boot from user area
+ bit_offset: 16
+ bit_size: 1
+fieldset/SR:
+ description: Status register
+ fields:
+ - name: EOP
+ description: End of operation
+ bit_offset: 0
+ bit_size: 1
+ - name: OPERR
+ description: Operation error
+ bit_offset: 1
+ bit_size: 1
+ - name: PROGERR
+ description: Programming error
+ bit_offset: 3
+ bit_size: 1
+ - name: WRPERR
+ description: Write protected error
+ bit_offset: 4
+ bit_size: 1
+ - name: PGAERR
+ description: Programming alignment error
+ bit_offset: 5
+ bit_size: 1
+ - name: SIZERR
+ description: Size error
+ bit_offset: 6
+ bit_size: 1
+ - name: PGSERR
+ description: Programming sequence error
+ bit_offset: 7
+ bit_size: 1
+ - name: MISERR
+ description: Fast programming data miss error
+ bit_offset: 8
+ bit_size: 1
+ - name: FASTERR
+ description: Fast programming error
+ bit_offset: 9
+ bit_size: 1
+ - name: RDERR
+ description: PCROP read error
+ bit_offset: 14
+ bit_size: 1
+ - name: OPTVERR
+ description: Option validity error
+ bit_offset: 15
+ bit_size: 1
+ - name: BSY
+ description: Busy
+ bit_offset: 16
+ bit_size: 1
+fieldset/WRP1AR:
+ description: Flash Bank 1 WRP area A address register
+ fields:
+ - name: WRP1A_STRT
+ description: Bank 1 WRP first area start offset
+ bit_offset: 0
+ bit_size: 7
+ - name: WRP1A_END
+ description: Bank 1 WRP first area A end offset
+ bit_offset: 16
+ bit_size: 7
+fieldset/WRP1BR:
+ description: Flash Bank 1 WRP area B address register
+ fields:
+ - name: WRP1B_STRT
+ description: Bank 1 WRP second area B end offset
+ bit_offset: 0
+ bit_size: 7
+ - name: WRP1B_END
+ description: Bank 1 WRP second area B start offset
+ bit_offset: 16
+ bit_size: 7
+enum/LATENCY:
+ bit_size: 4
+ variants:
+ - name: WS0
+ description: Zero wait states
+ value: 0
+ - name: WS1
+ description: One wait state
+ value: 1
+ - name: WS2
+ description: Two wait states
+ value: 2
+ - name: WS3
+ description: Three wait states
+ value: 3
+ - name: WS4
+ description: Four wait states
+ value: 4
+enum/NRST_MODE:
+ bit_size: 2
+ variants:
+ - name: INPUT_ONLY
+ description: Reset pin is in reset input mode only
+ value: 1
+ - name: GPIO
+ description: Reset pin is in GPIO mode only
+ value: 2
+ - name: INPUT_OUTPUT
+ description: Reset pin is in reset input and output mode
+ value: 3
+enum/RDP:
+ bit_size: 8
+ variants:
+ - name: LEVEL_0
+ description: Read protection not active
+ value: 170
+ - name: LEVEL_1
+ description: Memories read protection active
+ value: 187
+ - name: LEVEL_2
+ description: Chip read protection active
+ value: 204
diff --git a/data/registers/flash_g4c4.yaml b/data/registers/flash_g4c4.yaml
new file mode 100644
index 0000000..0e0c3ed
--- /dev/null
+++ b/data/registers/flash_g4c4.yaml
@@ -0,0 +1,406 @@
+block/FLASH:
+ description: Flash
+ items:
+ - name: ACR
+ description: Access control register
+ byte_offset: 0
+ fieldset: ACR
+ - name: PDKEYR
+ description: Power down key register
+ byte_offset: 4
+ access: Write
+ - name: KEYR
+ description: Flash key register
+ byte_offset: 8
+ access: Write
+ - name: OPTKEYR
+ description: Option byte key register
+ byte_offset: 12
+ access: Write
+ - name: SR
+ description: Status register
+ byte_offset: 16
+ fieldset: SR
+ - name: CR
+ description: Flash control register
+ byte_offset: 20
+ fieldset: CR
+ - name: ECCR
+ description: Flash ECC register
+ byte_offset: 24
+ fieldset: ECCR
+ - name: OPTR
+ description: Flash option register
+ byte_offset: 32
+ fieldset: OPTR
+ - name: PCROP1SR
+ description: Flash Bank 1 PCROP Start address register
+ byte_offset: 36
+ fieldset: PCROP1SR
+ - name: PCROP1ER
+ description: Flash Bank 1 PCROP End address register
+ byte_offset: 40
+ fieldset: PCROP1ER
+ - name: WRP1AR
+ description: Flash Bank 1 WRP area A address register
+ byte_offset: 44
+ fieldset: WRP1AR
+ - name: WRP1BR
+ description: Flash Bank 1 WRP area B address register
+ byte_offset: 48
+ fieldset: WRP1BR
+ - name: SEC1R
+ description: securable area bank1 register
+ byte_offset: 112
+ fieldset: SEC1R
+fieldset/ACR:
+ description: Access control register
+ fields:
+ - name: LATENCY
+ description: Latency
+ bit_offset: 0
+ bit_size: 4
+ enum: LATENCY
+ - name: PRFTEN
+ description: Prefetch enable
+ bit_offset: 8
+ bit_size: 1
+ - name: ICEN
+ description: Instruction cache enable
+ bit_offset: 9
+ bit_size: 1
+ - name: DCEN
+ description: Data cache enable
+ bit_offset: 10
+ bit_size: 1
+ - name: ICRST
+ description: Instruction cache reset
+ bit_offset: 11
+ bit_size: 1
+ - name: DCRST
+ description: Data cache reset
+ bit_offset: 12
+ bit_size: 1
+ - name: RUN_PD
+ description: Flash Power-down mode during Low-power run mode
+ bit_offset: 13
+ bit_size: 1
+ - name: SLEEP_PD
+ description: Flash Power-down mode during Low-power sleep mode
+ bit_offset: 14
+ bit_size: 1
+ - name: DBG_SWEN
+ description: Debug software enable
+ bit_offset: 18
+ bit_size: 1
+fieldset/CR:
+ description: Flash control register
+ fields:
+ - name: PG
+ description: Programming
+ bit_offset: 0
+ bit_size: 1
+ - name: PER
+ description: Page erase
+ bit_offset: 1
+ bit_size: 1
+ - name: MER1
+ description: Bank 1 Mass erase
+ bit_offset: 2
+ bit_size: 1
+ - name: PNB
+ description: Page number
+ bit_offset: 3
+ bit_size: 7
+ - name: STRT
+ description: Start
+ bit_offset: 16
+ bit_size: 1
+ - name: OPTSTRT
+ description: Options modification start
+ bit_offset: 17
+ bit_size: 1
+ - name: FSTPG
+ description: Fast programming
+ bit_offset: 18
+ bit_size: 1
+ - name: EOPIE
+ description: End of operation interrupt enable
+ bit_offset: 24
+ bit_size: 1
+ - name: ERRIE
+ description: Error interrupt enable
+ bit_offset: 25
+ bit_size: 1
+ - name: RDERRIE
+ description: PCROP read error interrupt enable
+ bit_offset: 26
+ bit_size: 1
+ - name: OBL_LAUNCH
+ description: Force the option byte loading
+ bit_offset: 27
+ bit_size: 1
+ - name: SEC_PROT1
+ description: Securable memory area protection enable
+ bit_offset: 28
+ bit_size: 1
+ - name: OPTLOCK
+ description: Options Lock
+ bit_offset: 30
+ bit_size: 1
+ - name: LOCK
+ description: FLASH_CR Lock
+ bit_offset: 31
+ bit_size: 1
+fieldset/ECCR:
+ description: Flash ECC register
+ fields:
+ - name: ADDR_ECC
+ description: ECC fail address
+ bit_offset: 0
+ bit_size: 19
+ - name: BK_ECC
+ description: ECC fail for Corrected ECC Error or Double ECC Error in info block
+ bit_offset: 21
+ bit_size: 1
+ - name: SYSF_ECC
+ description: ECC fail for Corrected ECC Error or Double ECC Error in info block
+ bit_offset: 22
+ bit_size: 1
+ - name: ECCIE
+ description: ECC correction interrupt enable
+ bit_offset: 24
+ bit_size: 1
+ - name: ECCC2
+ description: ECC correction
+ bit_offset: 28
+ bit_size: 1
+ - name: ECCD2
+ description: ECC2 detection
+ bit_offset: 29
+ bit_size: 1
+ - name: ECCC
+ description: ECC correction
+ bit_offset: 30
+ bit_size: 1
+ - name: ECCD
+ description: ECC detection
+ bit_offset: 31
+ bit_size: 1
+fieldset/OPTR:
+ description: Flash option register
+ fields:
+ - name: RDP
+ description: Read protection level
+ bit_offset: 0
+ bit_size: 8
+ enum: RDP
+ - name: BOR_LEV
+ description: BOR reset Level
+ bit_offset: 8
+ bit_size: 3
+ - name: nRST_STOP
+ description: nRST_STOP
+ bit_offset: 12
+ bit_size: 1
+ - name: nRST_STDBY
+ description: nRST_STDBY
+ bit_offset: 13
+ bit_size: 1
+ - name: nRST_SHDW
+ description: nRST_SHDW
+ bit_offset: 14
+ bit_size: 1
+ - name: IDWG_SW
+ description: Independent watchdog selection
+ bit_offset: 16
+ bit_size: 1
+ - name: IWDG_STOP
+ description: Independent watchdog counter freeze in Stop mode
+ bit_offset: 17
+ bit_size: 1
+ - name: IWDG_STDBY
+ description: Independent watchdog counter freeze in Standby mode
+ bit_offset: 18
+ bit_size: 1
+ - name: WWDG_SW
+ description: Window watchdog selection
+ bit_offset: 19
+ bit_size: 1
+ - name: PB4_PUPEN
+ description: PB4 pull-up enable
+ bit_offset: 22
+ bit_size: 1
+ - name: nBOOT1
+ description: Boot configuration
+ bit_offset: 23
+ bit_size: 1
+ - name: SRAM2_PE
+ description: SRAM2 parity check enable
+ bit_offset: 24
+ bit_size: 1
+ - name: SRAM2_RST
+ description: SRAM2 Erase when system reset
+ bit_offset: 25
+ bit_size: 1
+ - name: nSWBOOT0
+ description: nSWBOOT0
+ bit_offset: 26
+ bit_size: 1
+ - name: nBOOT0
+ description: nBOOT0 option bit
+ bit_offset: 27
+ bit_size: 1
+ - name: NRST_MODE
+ description: NRST_MODE
+ bit_offset: 28
+ bit_size: 2
+ enum: NRST_MODE
+ - name: IRHEN
+ description: Internal reset holder enable bit
+ bit_offset: 30
+ bit_size: 1
+fieldset/PCROP1ER:
+ description: Flash Bank 1 PCROP End address register
+ fields:
+ - name: PCROP1_END
+ description: Bank 1 PCROP area end offset
+ bit_offset: 0
+ bit_size: 15
+ - name: PCROP_RDP
+ description: PCROP area preserved when RDP level decreased
+ bit_offset: 31
+ bit_size: 1
+fieldset/PCROP1SR:
+ description: Flash Bank 1 PCROP Start address register
+ fields:
+ - name: PCROP1_STRT
+ description: Bank 1 PCROP area start offset
+ bit_offset: 0
+ bit_size: 15
+fieldset/SEC1R:
+ description: securable area bank1 register
+ fields:
+ - name: SEC_SIZE1
+ description: SEC_SIZE1
+ bit_offset: 0
+ bit_size: 8
+ - name: BOOT_LOCK
+ description: used to force boot from user area
+ bit_offset: 16
+ bit_size: 1
+fieldset/SR:
+ description: Status register
+ fields:
+ - name: EOP
+ description: End of operation
+ bit_offset: 0
+ bit_size: 1
+ - name: OPERR
+ description: Operation error
+ bit_offset: 1
+ bit_size: 1
+ - name: PROGERR
+ description: Programming error
+ bit_offset: 3
+ bit_size: 1
+ - name: WRPERR
+ description: Write protected error
+ bit_offset: 4
+ bit_size: 1
+ - name: PGAERR
+ description: Programming alignment error
+ bit_offset: 5
+ bit_size: 1
+ - name: SIZERR
+ description: Size error
+ bit_offset: 6
+ bit_size: 1
+ - name: PGSERR
+ description: Programming sequence error
+ bit_offset: 7
+ bit_size: 1
+ - name: MISERR
+ description: Fast programming data miss error
+ bit_offset: 8
+ bit_size: 1
+ - name: FASTERR
+ description: Fast programming error
+ bit_offset: 9
+ bit_size: 1
+ - name: RDERR
+ description: PCROP read error
+ bit_offset: 14
+ bit_size: 1
+ - name: OPTVERR
+ description: Option validity error
+ bit_offset: 15
+ bit_size: 1
+ - name: BSY
+ description: Busy
+ bit_offset: 16
+ bit_size: 1
+fieldset/WRP1AR:
+ description: Flash Bank 1 WRP area A address register
+ fields:
+ - name: WRP1A_STRT
+ description: Bank 1 WRP first area start offset
+ bit_offset: 0
+ bit_size: 7
+ - name: WRP1A_END
+ description: Bank 1 WRP first area A end offset
+ bit_offset: 16
+ bit_size: 7
+fieldset/WRP1BR:
+ description: Flash Bank 1 WRP area B address register
+ fields:
+ - name: WRP1B_STRT
+ description: Bank 1 WRP second area B end offset
+ bit_offset: 0
+ bit_size: 7
+ - name: WRP1B_END
+ description: Bank 1 WRP second area B start offset
+ bit_offset: 16
+ bit_size: 7
+enum/LATENCY:
+ bit_size: 4
+ variants:
+ - name: WS0
+ description: Zero wait states
+ value: 0
+ - name: WS1
+ description: One wait state
+ value: 1
+ - name: WS2
+ description: Two wait states
+ value: 2
+ - name: WS3
+ description: Three wait states
+ value: 3
+ - name: WS4
+ description: Four wait states
+ value: 4
+enum/NRST_MODE:
+ bit_size: 2
+ variants:
+ - name: INPUT_ONLY
+ description: Reset pin is in reset input mode only
+ value: 1
+ - name: GPIO
+ description: Reset pin is in GPIO mode only
+ value: 2
+ - name: INPUT_OUTPUT
+ description: Reset pin is in reset input and output mode
+ value: 3
+enum/RDP:
+ bit_size: 8
+ variants:
+ - name: LEVEL_0
+ description: Read protection not active
+ value: 170
+ - name: LEVEL_1
+ description: Memories read protection active
+ value: 187
+ - name: LEVEL_2
+ description: Chip read protection active
+ value: 204
diff --git a/data/registers/flash_h50.yaml b/data/registers/flash_h50.yaml
index 078c346..85177d3 100644
--- a/data/registers/flash_h50.yaml
+++ b/data/registers/flash_h50.yaml
@@ -46,6 +46,7 @@ block/FLASH:
- name: OPTSR_CUR
description: FLASH option status register
byte_offset: 80
+ access: Read
fieldset: OPTSR
- name: OPTSR_PRG
description: FLASH option status register
@@ -54,6 +55,7 @@ block/FLASH:
- name: OPTSR2_CUR
description: FLASH option status register 2
byte_offset: 112
+ access: Read
fieldset: OPTSR2
- name: OPTSR2_PRG
description: FLASH option status register 2
@@ -62,6 +64,7 @@ block/FLASH:
- name: NSBOOTR_CUR
description: FLASH non-secure unique boot entry register
byte_offset: 128
+ access: Read
fieldset: NSBOOTR
- name: NSBOOTR_PRG
description: FLASH non-secure unique boot entry address
@@ -70,6 +73,7 @@ block/FLASH:
- name: OTPBLR_CUR
description: FLASH non-secure OTP block lock
byte_offset: 144
+ access: Read
fieldset: OTPBLR
- name: OTPBLR_PRG
description: FLASH non-secure OTP block lock
@@ -82,6 +86,7 @@ block/FLASH:
- name: WRPSGN1R_CUR
description: FLASH write sector protection for Bank1
byte_offset: 232
+ access: Read
fieldset: WRP
- name: WRPSGN1R_PRG
description: FLASH write sector protection for Bank1
@@ -90,6 +95,7 @@ block/FLASH:
- name: HDP1R_CUR
description: FLASH HDP Bank1 register
byte_offset: 248
+ access: Read
fieldset: HDP1R
- name: HDP1R_PRG
description: FLASH HDP Bank1 register
@@ -110,6 +116,7 @@ block/FLASH:
- name: WRPSGN2R_CUR
description: FLASH write sector protection for Bank2
byte_offset: 488
+ access: Read
fieldset: WRP
- name: WRPSGN2R_PRG
description: FLASH write sector protection for Bank2
@@ -118,6 +125,7 @@ block/FLASH:
- name: HDP2R_CUR
description: FLASH HDP Bank2 register
byte_offset: 504
+ access: Read
fieldset: HDP2R
- name: HDP2R_PRG
description: FLASH HDP Bank2 register
@@ -413,7 +421,6 @@ fieldset/OPTCR:
description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR."
bit_offset: 31
bit_size: 1
- enum: OPTCR_SWAP_BANK
fieldset/OPTSR:
description: FLASH option status register
fields:
@@ -452,9 +459,10 @@ fieldset/OPTSR:
bit_size: 1
enum: OPTSR_NRST_STDBY
- name: PRODUCT_STATE
- description: Life state code (based on Hamming 8,4). More information in .
+ description: Life state code (based on Hamming 8,4).
bit_offset: 8
bit_size: 8
+ enum: PRODUCT_STATE
- name: IO_VDD_HSLV
description: High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V.
bit_offset: 16
@@ -479,7 +487,6 @@ fieldset/OPTSR:
description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not.\r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset."
bit_offset: 31
bit_size: 1
- enum: OPTSR_SWAP_BANK
fieldset/OPTSR2:
description: FLASH option status register 2
fields:
@@ -574,11 +581,11 @@ fieldset/WRP:
enum/BKSEL:
bit_size: 1
variants:
- - name: B_0x0
+ - name: BANK1
description: Bank1 is selected for Bank erase / sector erase / interrupt enable
value: 0
- - name: B_0x1
- description: Bank2 is selected for BER / SER
+ - name: BANK2
+ description: Bank1 is selected for Bank erase / sector erase / interrupt enable
value: 1
enum/CODE_OP:
bit_size: 3
@@ -619,15 +626,6 @@ enum/NSPRIV:
- name: B_0x1
description: access to non secure registers is denied in case of non privileged access.
value: 1
-enum/OPTCR_SWAP_BANK:
- bit_size: 1
- variants:
- - name: B_0x0
- description: Bank1 and Bank2 not swapped
- value: 0
- - name: B_0x1
- description: Bank1 and Bank2 swapped
- value: 1
enum/OPTSR_BKPRAM_ECC:
bit_size: 1
variants:
@@ -715,6 +713,27 @@ enum/OPTSR_NRST_STDBY:
- name: B_0x1
description: no reset generated when entering Standby mode on core domain.
value: 1
+enum/PRODUCT_STATE:
+ bit_size: 8
+ variants:
+ - name: OPEN
+ description: Open
+ value: 0xED
+ - name: PROVISIONING
+ description: Provisioning
+ value: 0x17
+ - name: IROT_PROVISIONED
+ description: iROT-Provisioned
+ value: 0x2E
+ - name: CLOSED
+ description: Closed
+ value: 0x72
+ - name: LOCKED
+ description: Locked
+ value: 0x5C
+ - name: REGRESSION
+ description: Regression
+ value: 0x9A
enum/OPTSR_NRST_STOP:
bit_size: 1
variants:
@@ -733,15 +752,6 @@ enum/OPTSR_SRAM_ECC:
- name: B_0x1
description: SRAM2 ECC check disabled
value: 1
-enum/OPTSR_SWAP_BANK:
- bit_size: 1
- variants:
- - name: B_0x0
- description: Bank1 and Bank2 not swapped
- value: 0
- - name: B_0x1
- description: Bank1 and Bank2 swapped
- value: 1
enum/OPTSR_WWDG_SW:
bit_size: 1
variants:
diff --git a/data/registers/flash_u0.yaml b/data/registers/flash_u0.yaml
new file mode 100644
index 0000000..bd6f427
--- /dev/null
+++ b/data/registers/flash_u0.yaml
@@ -0,0 +1,368 @@
+block/FLASH:
+ description: Mamba FLASH register block
+ items:
+ - name: ACR
+ description: FLASH access control register
+ byte_offset: 0
+ fieldset: ACR
+ - name: KEYR
+ description: FLASH key register
+ byte_offset: 8
+ fieldset: KEYR
+ - name: OPTKEYR
+ description: FLASH option key register
+ byte_offset: 12
+ fieldset: OPTKEYR
+ - name: SR
+ description: FLASH status register
+ byte_offset: 16
+ fieldset: SR
+ - name: CR
+ description: FLASH control register
+ byte_offset: 20
+ fieldset: CR
+ - name: ECCR
+ description: FLASH ECC register
+ byte_offset: 24
+ fieldset: ECCR
+ - name: OPTR
+ description: FLASH option register
+ byte_offset: 32
+ fieldset: OPTR
+ - name: WRP1AR
+ description: FLASH WRP area A address register
+ byte_offset: 44
+ fieldset: WRP1AR
+ - name: WRP1BR
+ description: FLASH WRP area B address register
+ byte_offset: 48
+ fieldset: WRP1BR
+ - name: SECR
+ description: FLASH security register
+ byte_offset: 128
+ fieldset: SECR
+fieldset/ACR:
+ description: FLASH access control register
+ fields:
+ - name: LATENCY
+ description: 'Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read.'
+ bit_offset: 0
+ bit_size: 3
+ - name: PRFTEN
+ description: CPU Prefetch enable
+ bit_offset: 8
+ bit_size: 1
+ - name: ICEN
+ description: CPU Instruction cache enable
+ bit_offset: 9
+ bit_size: 1
+ - name: ICRST
+ description: CPU Instruction cache reset This bit can be written only when the instruction cache is disabled.
+ bit_offset: 11
+ bit_size: 1
+ - name: EMPTY
+ description: Main flash memory area empty This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. The bit can be set and reset by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: DBG_SWEN
+ description: Debug access software enable Software may use this bit to enable/disable the debugger read access.
+ bit_offset: 18
+ bit_size: 1
+fieldset/CR:
+ description: FLASH control register
+ fields:
+ - name: PG
+ description: Flash memory programming enable
+ bit_offset: 0
+ bit_size: 1
+ - name: PER
+ description: Page erase enable
+ bit_offset: 1
+ bit_size: 1
+ - name: MER1
+ description: Mass erase When set, this bit triggers the mass erase, that is, all user pages.
+ bit_offset: 2
+ bit_size: 1
+ - name: PNB
+ description: 'Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the main memory are not allowed.'
+ bit_offset: 3
+ bit_size: 7
+ - name: STRT
+ description: Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero.
+ bit_offset: 16
+ bit_size: 1
+ - name: OPTSTRT
+ description: Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR.
+ bit_offset: 17
+ bit_size: 1
+ - name: FSTPG
+ description: Fast programming enable
+ bit_offset: 18
+ bit_size: 1
+ - name: EOPIE
+ description: End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register.
+ bit_offset: 24
+ bit_size: 1
+ - name: ERRIE
+ description: Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register.
+ bit_offset: 25
+ bit_size: 1
+ - name: RDERRIE
+ description: PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register.
+ bit_offset: 26
+ bit_size: 1
+ - name: OBL_LAUNCH
+ description: Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set.
+ bit_offset: 27
+ bit_size: 1
+ - name: SEC_PROT
+ description: Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset.
+ bit_offset: 28
+ bit_size: 1
+ - name: OPTLOCK
+ description: Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset.
+ bit_offset: 30
+ bit_size: 1
+ - name: LOCK
+ description: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
+ bit_offset: 31
+ bit_size: 1
+fieldset/ECCR:
+ description: FLASH ECC register
+ fields:
+ - name: ADDR_ECC
+ description: ECC fail double-word address offset In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory.
+ bit_offset: 0
+ bit_size: 14
+ - name: SYSF_ECC
+ description: System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory.
+ bit_offset: 20
+ bit_size: 1
+ - name: ECCCIE
+ description: ECC correction interrupt enable
+ bit_offset: 24
+ bit_size: 1
+ - name: ECCC
+ description: ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. Cleared by writing 1.
+ bit_offset: 30
+ bit_size: 1
+ - name: ECCD
+ description: ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. Cleared by writing 1.
+ bit_offset: 31
+ bit_size: 1
+fieldset/KEYR:
+ description: FLASH key register
+ fields:
+ - name: KEY
+ description: 'FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB'
+ bit_offset: 0
+ bit_size: 32
+fieldset/OPTKEYR:
+ description: FLASH option key register
+ fields:
+ - name: OPTKEY
+ description: 'Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F'
+ bit_offset: 0
+ bit_size: 32
+fieldset/OPTR:
+ description: FLASH option register
+ fields:
+ - name: RDP
+ description: 'Read protection level Other: Level 1, memories read protection active'
+ bit_offset: 0
+ bit_size: 8
+ enum: RDP
+ - name: BORR_LEV
+ description: BOR reset level
+ bit_offset: 8
+ bit_size: 3
+ enum: BORR_LEV
+ - name: NRST_STOP
+ description: Reset generated when entering Stop mode
+ bit_offset: 13
+ bit_size: 1
+ - name: NRST_STDBY
+ description: Reset generated when entering Standby mode
+ bit_offset: 14
+ bit_size: 1
+ - name: NRST_SHDW
+ description: Reset generated when entering Shutdown mode
+ bit_offset: 15
+ bit_size: 1
+ - name: IWDG_SW
+ description: Independent watchdog selection
+ bit_offset: 16
+ bit_size: 1
+ - name: IWDG_STOP
+ description: Independent watchdog counter freeze in Stop mode
+ bit_offset: 17
+ bit_size: 1
+ - name: IWDG_STDBY
+ description: Independent watchdog counter freeze in Standby mode
+ bit_offset: 18
+ bit_size: 1
+ - name: WWDG_SW
+ description: Window watchdog selection
+ bit_offset: 19
+ bit_size: 1
+ - name: BDRST
+ description: Backup domain reset
+ bit_offset: 21
+ bit_size: 1
+ - name: RAM_PARITY_CHECK
+ description: SRAM parity check control enable/disable
+ bit_offset: 22
+ bit_size: 1
+ - name: BKPSRAM_HW_ERASE_DISABLE
+ description: Backup SRAM erase prevention
+ bit_offset: 23
+ bit_size: 1
+ - name: NBOOT_SEL
+ description: BOOT0 signal source selection This option bit defines the source of the BOOT0 signal.
+ bit_offset: 24
+ bit_size: 1
+ - name: NBOOT1
+ description: 'Boot configuration Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration.'
+ bit_offset: 25
+ bit_size: 1
+ - name: NBOOT0
+ description: NBOOT0 option bit
+ bit_offset: 26
+ bit_size: 1
+ - name: NRST_MODE
+ description: NRST pin configuration
+ bit_offset: 27
+ bit_size: 2
+ enum: NRST_MODE
+ - name: IRHEN
+ description: Internal reset holder enable bit
+ bit_offset: 29
+ bit_size: 1
+fieldset/SECR:
+ description: FLASH security register
+ fields:
+ - name: HDP1_PEND
+ description: Last page of the first hide protection area
+ bit_offset: 0
+ bit_size: 7
+ - name: BOOT_LOCK
+ description: used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch).
+ bit_offset: 16
+ bit_size: 1
+ - name: HDP1EN
+ description: Hide protection area enable
+ bit_offset: 24
+ bit_size: 8
+fieldset/SR:
+ description: FLASH status register
+ fields:
+ - name: EOP
+ description: End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1.
+ bit_offset: 0
+ bit_size: 1
+ - name: OPERR
+ description: Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing 1.
+ bit_offset: 1
+ bit_size: 1
+ - name: PROGERR
+ description: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1.
+ bit_offset: 3
+ bit_size: 1
+ - name: WRPERR
+ description: Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1.
+ bit_offset: 4
+ bit_size: 1
+ - name: PGAERR
+ description: Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1.
+ bit_offset: 5
+ bit_size: 1
+ - name: SIZERR
+ description: 'Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1.'
+ bit_offset: 6
+ bit_size: 1
+ - name: PGSERR
+ description: Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1.
+ bit_offset: 7
+ bit_size: 1
+ - name: MISSERR
+ description: Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1.
+ bit_offset: 8
+ bit_size: 1
+ - name: FASTERR
+ description: Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1.
+ bit_offset: 9
+ bit_size: 1
+ - name: RDERR
+ description: PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1.
+ bit_offset: 14
+ bit_size: 1
+ - name: OPTVERR
+ description: Option and Engineering bits loading validity error
+ bit_offset: 15
+ bit_size: 1
+ - name: BSY1
+ description: Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs.
+ bit_offset: 16
+ bit_size: 1
+ - name: CFGBSY
+ description: Programming or erase configuration busy. This flag is set and cleared by hardware. It is set when the first word is sent for program or when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared when the flash memory program or erase operation completes or ends with an error. When set, launching any other operation through the FLASH control register (FLASH_CR) is impossible, and must be postponed (a programming or erase operation is ongoing). When cleared, the program and erase settings in the FLASH control register (FLASH_CR) can be modified.
+ bit_offset: 18
+ bit_size: 1
+fieldset/WRP1AR:
+ description: FLASH WRP area A address register
+ fields:
+ - name: WRP1A_STRT
+ description: 'WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.'
+ bit_offset: 0
+ bit_size: 7
+ - name: WRP1A_END
+ description: 'WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.'
+ bit_offset: 16
+ bit_size: 7
+fieldset/WRP1BR:
+ description: FLASH WRP area B address register
+ fields:
+ - name: WRP1B_STRT
+ description: 'WRP area B start offset This bitfield contains the offset of the first page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.'
+ bit_offset: 0
+ bit_size: 7
+ - name: WRP1B_END
+ description: 'WRP area B end offset This bitfield contains the offset of the last page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.'
+ bit_offset: 16
+ bit_size: 7
+enum/BORR_LEV:
+ bit_size: 3
+ variants:
+ - name: Level1
+ description: BOR rising level 1 with threshold around 2.1 V
+ value: 0
+ - name: Level2
+ description: BOR rising level 2 with threshold around 2.3 V
+ value: 1
+ - name: Level3
+ description: BOR rising level 3 with threshold around 2.6 V
+ value: 2
+ - name: Level4
+ description: BOR rising level 4 with threshold around 2.9 V
+ value: 3
+enum/NRST_MODE:
+ bit_size: 2
+ variants:
+ - name: OnlyInput
+ description: 'Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin.'
+ value: 1
+ - name: OnlyInternal
+ description: 'Standard GPIO: only internal RESET is possible'
+ value: 2
+ - name: Bidirectional
+ description: 'Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode'
+ value: 3
+enum/RDP:
+ bit_size: 8
+ variants:
+ - name: Level0
+ description: Level 0, read protection not active
+ value: 170
+ - name: Level2
+ description: Level 2, chip read protection active
+ value: 204
diff --git a/data/registers/hsem_v1.yaml b/data/registers/hsem_v1.yaml
new file mode 100644
index 0000000..0089381
--- /dev/null
+++ b/data/registers/hsem_v1.yaml
@@ -0,0 +1,144 @@
+block/HSEM:
+ description: Hardware semaphore (HSEM).
+ items:
+ - name: R
+ description: HSEM register HSEM_R%s HSEM_R31.
+ array:
+ len: 32
+ stride: 4
+ byte_offset: 0
+ fieldset: R
+ - name: RLR
+ description: HSEM Read lock register.
+ array:
+ len: 32
+ stride: 4
+ byte_offset: 128
+ access: Read
+ fieldset: RLR
+ - name: IER
+ description: HSEM Interrupt enable register.
+ byte_offset: 256
+ fieldset: IER
+ array:
+ len: 2
+ stride: 16
+ - name: ICR
+ description: HSEM Interrupt clear register.
+ byte_offset: 260
+ fieldset: ICR
+ array:
+ len: 2
+ stride: 16
+ - name: ISR
+ description: HSEM Interrupt status register.
+ byte_offset: 264
+ access: Read
+ fieldset: ISR
+ array:
+ len: 2
+ stride: 16
+ - name: MISR
+ description: HSEM Masked interrupt status register.
+ byte_offset: 268
+ access: Read
+ fieldset: MISR
+ array:
+ len: 2
+ stride: 16
+ - name: CR
+ description: HSEM Clear register.
+ byte_offset: 320
+ fieldset: CR
+ - name: KEYR
+ description: HSEM Interrupt clear register.
+ byte_offset: 324
+ fieldset: KEYR
+fieldset/CR:
+ description: HSEM Clear register.
+ fields:
+ - name: COREID
+ description: COREID of semaphores to be cleared.
+ bit_offset: 8
+ bit_size: 4
+ - name: KEY
+ description: Semaphore clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/KEYR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: KEY
+ description: Semaphore Clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/R:
+ description: HSEM register HSEM_R%s HSEM_R31.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: Semaphore COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/RLR:
+ description: HSEM Read lock register.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: Semaphore COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/IER:
+ description: HSEM Interrupt enable register.
+ fields:
+ - name: ISE
+ description: Interrupt semaphore x enable bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
+fieldset/ICR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: ISC
+ description: Interrupt semaphore x clear bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
+fieldset/ISR:
+ description: HSEM Interrupt status register.
+ fields:
+ - name: ISF
+ description: Interrupt semaphore x status bit before enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
+fieldset/MISR:
+ description: HSEM Masked interrupt status register.
+ fields:
+ - name: MISF
+ description: masked interrupt semaphore x status bit after enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
diff --git a/data/registers/hsem_v2.yaml b/data/registers/hsem_v2.yaml
new file mode 100644
index 0000000..3ec588e
--- /dev/null
+++ b/data/registers/hsem_v2.yaml
@@ -0,0 +1,145 @@
+block/HSEM:
+ description: HSEM.
+ items:
+ - name: R
+ description: HSEM register HSEM_R%s HSEM_R31.
+ array:
+ len: 32
+ stride: 4
+ byte_offset: 0
+ fieldset: R
+ - name: RLR
+ description: HSEM Read lock register.
+ array:
+ len: 32
+ stride: 4
+ byte_offset: 128
+ access: Read
+ fieldset: RLR
+ - name: IER
+ description: HSEM Interrupt enable register.
+ byte_offset: 256
+ fieldset: IER
+ array:
+ len: 1
+ stride: 16
+ - name: ICR
+ description: HSEM Interrupt clear register.
+ byte_offset: 260
+ access: Read
+ fieldset: ICR
+ array:
+ len: 1
+ stride: 16
+ - name: ISR
+ description: HSEM Interrupt status register.
+ byte_offset: 264
+ access: Read
+ fieldset: ISR
+ array:
+ len: 1
+ stride: 16
+ - name: MISR
+ description: HSEM Masked interrupt status register.
+ byte_offset: 268
+ access: Read
+ fieldset: MISR
+ array:
+ len: 1
+ stride: 16
+ - name: CR
+ description: HSEM Clear register.
+ byte_offset: 320
+ fieldset: CR
+ - name: KEYR
+ description: HSEM Interrupt clear register.
+ byte_offset: 324
+ fieldset: KEYR
+fieldset/CR:
+ description: HSEM Clear register.
+ fields:
+ - name: COREID
+ description: COREID of semaphores to be cleared.
+ bit_offset: 8
+ bit_size: 4
+ - name: KEY
+ description: Semaphore clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/KEYR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: KEY
+ description: Semaphore Clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/R:
+ description: HSEM register HSEM_R%s HSEM_R31.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: Semaphore COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/RLR:
+ description: HSEM Read lock register.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: Semaphore COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/IER:
+ description: HSEM Interrupt enable register.
+ fields:
+ - name: ISE
+ description: Interrupt semaphore x enable bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
+fieldset/ICR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: ISC
+ description: Interrupt semaphore x clear bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
+fieldset/ISR:
+ description: HSEM Interrupt status register.
+ fields:
+ - name: ISF
+ description: Interrupt semaphore x status bit before enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
+fieldset/MISR:
+ description: HSEM Masked interrupt status register.
+ fields:
+ - name: MISF
+ description: masked interrupt semaphore x status bit after enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 32
+ stride: 1
diff --git a/data/registers/hsem_v3.yaml b/data/registers/hsem_v3.yaml
new file mode 100644
index 0000000..f754a68
--- /dev/null
+++ b/data/registers/hsem_v3.yaml
@@ -0,0 +1,145 @@
+block/HSEM:
+ description: Hardware semaphore.
+ items:
+ - name: R
+ description: HSEM register HSEM_R%s HSEM_R31.
+ array:
+ len: 16
+ stride: 4
+ byte_offset: 0
+ fieldset: R
+ - name: RLR
+ description: HSEM Read lock register.
+ array:
+ len: 16
+ stride: 4
+ byte_offset: 128
+ access: Read
+ fieldset: RLR
+ - name: IER
+ description: HSEM Interrupt enable register.
+ byte_offset: 256
+ fieldset: IER
+ array:
+ len: 2
+ stride: 16
+ - name: ICR
+ description: HSEM Interrupt clear register.
+ byte_offset: 260
+ fieldset: ICR
+ array:
+ len: 2
+ stride: 16
+ - name: ISR
+ description: HSEM Interrupt status register.
+ byte_offset: 264
+ access: Read
+ fieldset: ISR
+ array:
+ len: 2
+ stride: 16
+ - name: MISR
+ description: HSEM Masked interrupt status register.
+ byte_offset: 268
+ access: Read
+ fieldset: MISR
+ array:
+ len: 2
+ stride: 16
+ - name: CR
+ description: HSEM Clear register.
+ byte_offset: 320
+ access: Write
+ fieldset: CR
+ - name: KEYR
+ description: HSEM Interrupt clear register.
+ byte_offset: 324
+ fieldset: KEYR
+fieldset/CR:
+ description: HSEM Clear register.
+ fields:
+ - name: COREID
+ description: COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: KEY
+ description: Semaphore clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/KEYR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: KEY
+ description: Semaphore Clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/R:
+ description: HSEM register HSEM_R%s HSEM_R31.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/RLR:
+ description: HSEM Read lock register.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/IER:
+ description: HSEM Interrupt enable register.
+ fields:
+ - name: ISE
+ description: Interrupt semaphore x enable bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/ICR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: ISC
+ description: Interrupt semaphore x clear bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/ISR:
+ description: HSEM Interrupt status register.
+ fields:
+ - name: ISF
+ description: Interrupt semaphore x status bit before enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/MISR:
+ description: HSEM Masked interrupt status register.
+ fields:
+ - name: MISF
+ description: masked interrupt semaphore x status bit after enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
diff --git a/data/registers/hsem_v4.yaml b/data/registers/hsem_v4.yaml
new file mode 100644
index 0000000..1c0794a
--- /dev/null
+++ b/data/registers/hsem_v4.yaml
@@ -0,0 +1,145 @@
+block/HSEM:
+ description: Hardware semaphore.
+ items:
+ - name: R
+ description: HSEM register HSEM_R%s HSEM_R31.
+ array:
+ len: 16
+ stride: 4
+ byte_offset: 0
+ fieldset: R
+ - name: RLR
+ description: HSEM Read lock register.
+ array:
+ len: 16
+ stride: 4
+ byte_offset: 128
+ access: Read
+ fieldset: RLR
+ - name: IER
+ description: HSEM Interrupt enable register.
+ byte_offset: 256
+ fieldset: IER
+ array:
+ len: 1
+ stride: 16
+ - name: ICR
+ description: HSEM Interrupt clear register.
+ byte_offset: 260
+ fieldset: ICR
+ array:
+ len: 1
+ stride: 16
+ - name: ISR
+ description: HSEM Interrupt status register.
+ byte_offset: 264
+ access: Read
+ fieldset: ISR
+ array:
+ len: 1
+ stride: 16
+ - name: MISR
+ description: HSEM Masked interrupt status register.
+ byte_offset: 268
+ access: Read
+ fieldset: MISR
+ array:
+ len: 1
+ stride: 16
+ - name: CR
+ description: HSEM Clear register.
+ byte_offset: 320
+ access: Write
+ fieldset: CR
+ - name: KEYR
+ description: HSEM Interrupt clear register.
+ byte_offset: 324
+ fieldset: KEYR
+fieldset/ICR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: ISC
+ description: Interrupt(N) semaphore n clear bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/IER:
+ description: HSEM Interrupt enable register.
+ fields:
+ - name: ISE
+ description: Interrupt semaphore n enable bit.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/ISR:
+ description: HSEM Interrupt status register.
+ fields:
+ - name: ISF
+ description: Interrupt(N) semaphore n status bit before enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/MISR:
+ description: HSEM Masked interrupt status register.
+ fields:
+ - name: MISF
+ description: masked interrupt(N) semaphore n status bit after enable (mask).
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 16
+ stride: 1
+fieldset/CR:
+ description: HSEM Clear register.
+ fields:
+ - name: COREID
+ description: COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: KEY
+ description: Semaphore clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/KEYR:
+ description: HSEM Interrupt clear register.
+ fields:
+ - name: KEY
+ description: Semaphore Clear Key.
+ bit_offset: 16
+ bit_size: 16
+fieldset/R:
+ description: HSEM register HSEM_R%s HSEM_R31.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: Semaphore COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
+fieldset/RLR:
+ description: HSEM Read lock register.
+ fields:
+ - name: PROCID
+ description: Semaphore ProcessID.
+ bit_offset: 0
+ bit_size: 8
+ - name: COREID
+ description: Semaphore COREID.
+ bit_offset: 8
+ bit_size: 4
+ - name: LOCK
+ description: Lock indication.
+ bit_offset: 31
+ bit_size: 1
diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml
new file mode 100644
index 0000000..614eb21
--- /dev/null
+++ b/data/registers/lptim_v2a.yaml
@@ -0,0 +1,324 @@
+block/LPTIM:
+ description: Low power timer.
+ items:
+ - name: ISR
+ description: Interrupt and Status Register.
+ byte_offset: 0
+ access: Read
+ fieldset: ISR
+ - name: ICR
+ description: Interrupt Clear Register.
+ byte_offset: 4
+ access: Write
+ fieldset: ICR
+ - name: IER
+ description: Interrupt Enable Register.
+ byte_offset: 8
+ fieldset: IER
+ - name: CFGR
+ description: Configuration Register.
+ byte_offset: 12
+ fieldset: CFGR
+ - name: CR
+ description: Control Register.
+ byte_offset: 16
+ fieldset: CR
+ - name: CMP
+ description: Compare Register.
+ byte_offset: 20
+ fieldset: CMP
+ - name: ARR
+ description: Autoreload Register.
+ byte_offset: 24
+ fieldset: ARR
+ - name: CNT
+ description: Counter Register.
+ byte_offset: 28
+ access: Read
+ fieldset: CNT
+ - name: OR
+ description: LPTIM option register.
+ byte_offset: 32
+ - name: RCR
+ description: LPTIM repetition register.
+ byte_offset: 40
+ fieldset: RCR
+fieldset/ARR:
+ description: Autoreload Register.
+ fields:
+ - name: ARR
+ description: Auto reload value.
+ bit_offset: 0
+ bit_size: 16
+fieldset/CFGR:
+ description: Configuration Register.
+ fields:
+ - name: CKSEL
+ description: Clock selector.
+ bit_offset: 0
+ bit_size: 1
+ enum: CKSEL
+ - name: CKPOL
+ description: Clock Polarity.
+ bit_offset: 1
+ bit_size: 2
+ enum: CKPOL
+ - name: CKFLT
+ description: Configurable digital filter for external clock.
+ bit_offset: 3
+ bit_size: 2
+ enum: Filter
+ - name: TRGFLT
+ description: Configurable digital filter for trigger.
+ bit_offset: 6
+ bit_size: 2
+ enum: Filter
+ - name: PRESC
+ description: Clock prescaler.
+ bit_offset: 9
+ bit_size: 3
+ enum: PRESC
+ - name: TRIGSEL
+ description: Trigger selector.
+ bit_offset: 13
+ bit_size: 3
+ - name: TRIGEN
+ description: Trigger enable and polarity.
+ bit_offset: 17
+ bit_size: 2
+ - name: TIMOUT
+ description: Timeout enable.
+ bit_offset: 19
+ bit_size: 1
+ - name: WAVE
+ description: Waveform shape.
+ bit_offset: 20
+ bit_size: 1
+ - name: WAVPOL
+ description: Waveform shape polarity.
+ bit_offset: 21
+ bit_size: 1
+ - name: PRELOAD
+ description: Registers update mode.
+ bit_offset: 22
+ bit_size: 1
+ - name: COUNTMODE
+ description: counter mode enabled.
+ bit_offset: 23
+ bit_size: 1
+ - name: ENC
+ description: Encoder mode enable.
+ bit_offset: 24
+ bit_size: 1
+fieldset/CMP:
+ description: Compare Register.
+ fields:
+ - name: CMP
+ description: Compare value.
+ bit_offset: 0
+ bit_size: 16
+fieldset/CNT:
+ description: Counter Register.
+ fields:
+ - name: CNT
+ description: Counter value.
+ bit_offset: 0
+ bit_size: 16
+fieldset/CR:
+ description: Control Register.
+ fields:
+ - name: ENABLE
+ description: LPTIM Enable.
+ bit_offset: 0
+ bit_size: 1
+ - name: SNGSTRT
+ description: LPTIM start in single mode.
+ bit_offset: 1
+ bit_size: 1
+ - name: CNTSTRT
+ description: Timer start in continuous mode.
+ bit_offset: 2
+ bit_size: 1
+ - name: RSTARE
+ description: Reset after read enable.
+ bit_offset: 3
+ bit_size: 1
+ - name: COUNTRST
+ description: Counter reset.
+ bit_offset: 4
+ bit_size: 1
+fieldset/ICR:
+ description: Interrupt Clear Register.
+ fields:
+ - name: CMPMCF
+ description: compare match Clear Flag.
+ bit_offset: 0
+ bit_size: 1
+ - name: ARRMCF
+ description: Autoreload match Clear Flag.
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTTRIGCF
+ description: External trigger valid edge Clear Flag.
+ bit_offset: 2
+ bit_size: 1
+ - name: CMPOKCF
+ description: Compare register update OK Clear Flag.
+ bit_offset: 3
+ bit_size: 1
+ - name: ARROKCF
+ description: Autoreload register update OK Clear Flag.
+ bit_offset: 4
+ bit_size: 1
+ - name: UPCF
+ description: Direction change to UP Clear Flag.
+ bit_offset: 5
+ bit_size: 1
+ - name: DOWNCF
+ description: Direction change to down Clear Flag.
+ bit_offset: 6
+ bit_size: 1
+ - name: UECF
+ description: Update event clear flag.
+ bit_offset: 7
+ bit_size: 1
+ - name: REPOKCF
+ description: Repetition register update OK clear flag.
+ bit_offset: 8
+ bit_size: 1
+fieldset/IER:
+ description: Interrupt Enable Register.
+ fields:
+ - name: CMPMIE
+ description: Compare match Interrupt Enable.
+ bit_offset: 0
+ bit_size: 1
+ - name: ARRMIE
+ description: Autoreload match Interrupt Enable.
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTTRIGIE
+ description: External trigger valid edge Interrupt Enable.
+ bit_offset: 2
+ bit_size: 1
+ - name: CMPOKIE
+ description: Compare register update OK Interrupt Enable.
+ bit_offset: 3
+ bit_size: 1
+ - name: ARROKIE
+ description: Autoreload register update OK Interrupt Enable.
+ bit_offset: 4
+ bit_size: 1
+ - name: UPIE
+ description: Direction change to UP Interrupt Enable.
+ bit_offset: 5
+ bit_size: 1
+ - name: DOWNIE
+ description: Direction change to down Interrupt Enable.
+ bit_offset: 6
+ bit_size: 1
+ - name: UEIE
+ description: Update event interrupt enable.
+ bit_offset: 7
+ bit_size: 1
+ - name: REPOKIE
+ description: REPOKIE.
+ bit_offset: 8
+ bit_size: 1
+fieldset/ISR:
+ description: Interrupt and Status Register.
+ fields:
+ - name: CMPM
+ description: Compare match.
+ bit_offset: 0
+ bit_size: 1
+ - name: ARRM
+ description: Autoreload match.
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTTRIG
+ description: External trigger edge event.
+ bit_offset: 2
+ bit_size: 1
+ - name: CMPOK
+ description: Compare register update OK.
+ bit_offset: 3
+ bit_size: 1
+ - name: ARROK
+ description: Autoreload register update OK.
+ bit_offset: 4
+ bit_size: 1
+ - name: UP
+ description: Counter direction change down to up.
+ bit_offset: 5
+ bit_size: 1
+ - name: DOWN
+ description: Counter direction change up to down.
+ bit_offset: 6
+ bit_size: 1
+ - name: UE
+ description: LPTIM update event occurred.
+ bit_offset: 7
+ bit_size: 1
+ - name: REPOK
+ description: Repetition register update Ok.
+ bit_offset: 8
+ bit_size: 1
+fieldset/RCR:
+ description: LPTIM repetition register.
+ fields:
+ - name: REP
+ description: Repetition register value.
+ bit_offset: 0
+ bit_size: 8
+enum/CKPOL:
+ bit_size: 2
+ variants:
+ - name: Rising
+ description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.
+ value: 0
+ - name: Falling
+ description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.
+ value: 1
+ - name: Both
+ description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
+ value: 2
+enum/CKSEL:
+ bit_size: 1
+ variants:
+ - name: Internal
+ description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
+ value: 0
+ - name: External
+ description: LPTIM is clocked by an external clock source through the LPTIM external Input1
+ value: 1
+enum/Filter:
+ bit_size: 2
+ variants:
+ - name: Count1
+ value: 0
+ - name: Count2
+ value: 1
+ - name: Count4
+ value: 2
+ - name: Count8
+ value: 3
+enum/PRESC:
+ bit_size: 3
+ variants:
+ - name: Div1
+ value: 0
+ - name: Div2
+ value: 1
+ - name: Div4
+ value: 2
+ - name: Div8
+ value: 3
+ - name: Div16
+ value: 4
+ - name: Div32
+ value: 5
+ - name: Div64
+ value: 6
+ - name: Div128
+ value: 7
diff --git a/data/registers/lptim_v2b.yaml b/data/registers/lptim_v2b.yaml
new file mode 100644
index 0000000..de86cb0
--- /dev/null
+++ b/data/registers/lptim_v2b.yaml
@@ -0,0 +1,568 @@
+block/LPTIM_ADV:
+ extends: LPTIM_BASIC
+ description: Low power timer with Output Compare
+ items:
+ - name: ISR
+ description: LPTIM interrupt and status register.
+ byte_offset: 0
+ fieldset: ISR_ADV
+ - name: ICR
+ description: LPTIM interrupt clear register.
+ byte_offset: 4
+ fieldset: ICR_ADV
+ - name: DIER
+ description: LPTIM interrupt enable register.
+ byte_offset: 8
+ fieldset: DIER_ADV
+ - name: CCR
+ description: LPTIM compare register 1.
+ array:
+ len: 2
+ stride: 32
+ byte_offset: 20
+ fieldset: CCR
+ - name: CCMR
+ description: LPTIM capture/compare mode register 1.
+ byte_offset: 44
+ fieldset: CCMR
+block/LPTIM_BASIC:
+ description: Low power timer with Output Compare
+ items:
+ - name: ISR
+ description: LPTIM interrupt and status register.
+ byte_offset: 0
+ fieldset: ISR_BASIC
+ - name: ICR
+ description: LPTIM interrupt clear register.
+ byte_offset: 4
+ fieldset: ICR_BASIC
+ - name: DIER
+ description: LPTIM interrupt enable register.
+ byte_offset: 8
+ fieldset: DIER_BASIC
+ - name: CFGR
+ description: LPTIM configuration register.
+ byte_offset: 12
+ fieldset: CFGR
+ - name: CR
+ description: LPTIM control register.
+ byte_offset: 16
+ fieldset: CR
+ - name: CCR
+ description: LPTIM compare register 1.
+ array:
+ len: 1
+ stride: 32
+ byte_offset: 20
+ fieldset: CCR
+ - name: ARR
+ description: LPTIM autoreload register.
+ byte_offset: 24
+ fieldset: ARR
+ - name: CNT
+ description: LPTIM counter register.
+ byte_offset: 28
+ fieldset: CNT
+ - name: CFGR2
+ description: LPTIM configuration register 2.
+ byte_offset: 36
+ fieldset: CFGR2
+ - name: RCR
+ description: LPTIM repetition register.
+ byte_offset: 40
+ fieldset: RCR
+fieldset/ARR:
+ description: LPTIM autoreload register.
+ fields:
+ - name: ARR
+ description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.
+ bit_offset: 0
+ bit_size: 16
+fieldset/CCMR:
+ description: LPTIM capture/compare mode register 1.
+ fields:
+ - name: CCSEL
+ description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 2
+ stride: 16
+ enum: CCSEL
+ - name: CCE
+ description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not.
+ bit_offset: 1
+ bit_size: 1
+ array:
+ len: 2
+ stride: 16
+ - name: CCP_Input
+ description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.
+ bit_offset: 2
+ bit_size: 2
+ array:
+ len: 2
+ stride: 16
+ enum: CCP_Input
+ - name: CCP_Output
+ description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.
+ bit_offset: 2
+ bit_size: 2
+ array:
+ len: 2
+ stride: 16
+ enum: CCP_Output
+ - name: ICPSC
+ description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).
+ bit_offset: 8
+ bit_size: 2
+ array:
+ len: 2
+ stride: 16
+ enum: Filter
+ - name: ICF
+ description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.
+ bit_offset: 12
+ bit_size: 2
+ array:
+ len: 2
+ stride: 16
+ enum: Filter
+fieldset/CCR:
+ description: LPTIM compare register 1.
+ fields:
+ - name: CCR
+ description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.'
+ bit_offset: 0
+ bit_size: 16
+fieldset/CFGR:
+ description: LPTIM configuration register.
+ fields:
+ - name: CKSEL
+ description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:.
+ bit_offset: 0
+ bit_size: 1
+ enum: CKSEL
+ - name: CKPOL
+ description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.'
+ bit_offset: 1
+ bit_size: 2
+ enum: CKPOL
+ - name: CKFLT
+ description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.
+ bit_offset: 3
+ bit_size: 2
+ enum: Filter
+ - name: TRGFLT
+ description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.
+ bit_offset: 6
+ bit_size: 2
+ enum: Filter
+ - name: PRESC
+ description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.
+ bit_offset: 9
+ bit_size: 3
+ enum: PRESC
+ - name: TRIGSEL
+ description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.'
+ bit_offset: 13
+ bit_size: 3
+ - name: TRIGEN
+ description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.
+ bit_offset: 17
+ bit_size: 2
+ enum: TRIGEN
+ - name: TIMOUT
+ description: Timeout enable The TIMOUT bit controls the Timeout feature.
+ bit_offset: 19
+ bit_size: 1
+ - name: WAVE
+ description: Waveform shape The WAVE bit controls the output shape.
+ bit_offset: 20
+ bit_size: 1
+ - name: WAVPOL
+ description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.'
+ bit_offset: 21
+ bit_size: 1
+ - name: PRELOAD
+ description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.
+ bit_offset: 22
+ bit_size: 1
+ - name: COUNTMODE
+ description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.
+ bit_offset: 23
+ bit_size: 1
+ - name: ENC
+ description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 24
+ bit_size: 1
+fieldset/CFGR2:
+ description: LPTIM configuration register 2.
+ fields:
+ - name: INSEL
+ description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.
+ bit_offset: 0
+ bit_size: 2
+ array:
+ len: 2
+ stride: 4
+ - name: ICSEL
+ description: LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to.
+ bit_offset: 16
+ bit_size: 2
+ array:
+ len: 2
+ stride: 4
+fieldset/CNT:
+ description: LPTIM counter register.
+ fields:
+ - name: CNT
+ description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
+ bit_offset: 0
+ bit_size: 16
+fieldset/CR:
+ description: LPTIM control register.
+ fields:
+ - name: ENABLE
+ description: LPTIM enable The ENABLE bit is set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: SNGSTRT
+ description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.
+ bit_offset: 1
+ bit_size: 1
+ - name: CNTSTRT
+ description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.
+ bit_offset: 2
+ bit_size: 1
+ - name: COUNTRST
+ description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
+ bit_offset: 3
+ bit_size: 1
+ - name: RSTARE
+ description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.
+ bit_offset: 4
+ bit_size: 1
+fieldset/DIER_ADV:
+ extends: DIER_BASIC
+ description: LPTIM interrupt enable register.
+ fields:
+ - name: CCIE
+ description: Capture/compare 1 interrupt enable.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 2
+ stride: 9
+ - name: CMPOKIE
+ description: Compare register 1 update OK interrupt enable.
+ bit_offset: 3
+ bit_size: 1
+ array:
+ len: 2
+ stride: 16
+ - name: CCOIE
+ description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
+ bit_offset: 12
+ bit_size: 1
+ array:
+ len: 2
+ stride: 1
+ - name: CCDE
+ description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
+ bit_offset: 16
+ bit_size: 1
+ array:
+ len: 2
+ stride: 9
+fieldset/DIER_BASIC:
+ description: LPTIM interrupt enable register.
+ fields:
+ - name: CCIE
+ description: Capture/compare 1 interrupt enable.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 1
+ stride: 9
+ - name: ARRMIE
+ description: Autoreload match Interrupt Enable.
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTTRIGIE
+ description: External trigger valid edge Interrupt Enable.
+ bit_offset: 2
+ bit_size: 1
+ - name: CMPOKIE
+ description: Compare register 1 update OK interrupt enable.
+ bit_offset: 3
+ bit_size: 1
+ array:
+ len: 1
+ stride: 16
+ - name: ARROKIE
+ description: Autoreload register update OK Interrupt Enable.
+ bit_offset: 4
+ bit_size: 1
+ - name: UPIE
+ description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 5
+ bit_size: 1
+ - name: DOWNIE
+ description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 6
+ bit_size: 1
+ - name: UEIE
+ description: Update event interrupt enable.
+ bit_offset: 7
+ bit_size: 1
+ - name: REPOKIE
+ description: Repetition register update OK interrupt Enable.
+ bit_offset: 8
+ bit_size: 1
+fieldset/ICR_ADV:
+ extends: ICR_BASIC
+ description: LPTIM interrupt clear register.
+ fields:
+ - name: CCCF
+ description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 2
+ stride: 9
+ - name: CMPOKCF
+ description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
+ bit_offset: 3
+ bit_size: 1
+ array:
+ len: 2
+ stride: 16
+ - name: CCOCF
+ description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
+ bit_offset: 12
+ bit_size: 1
+ array:
+ len: 2
+ stride: 1
+fieldset/ICR_BASIC:
+ description: LPTIM interrupt clear register.
+ fields:
+ - name: CCCF
+ description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 1
+ stride: 9
+ - name: ARRMCF
+ description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTTRIGCF
+ description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.
+ bit_offset: 2
+ bit_size: 1
+ - name: CMPOKCF
+ description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
+ bit_offset: 3
+ bit_size: 1
+ array:
+ len: 1
+ stride: 16
+ - name: ARROKCF
+ description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
+ bit_offset: 4
+ bit_size: 1
+ - name: UPCF
+ description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 5
+ bit_size: 1
+ - name: DOWNCF
+ description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 6
+ bit_size: 1
+ - name: UECF
+ description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.
+ bit_offset: 7
+ bit_size: 1
+ - name: REPOKCF
+ description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.
+ bit_offset: 8
+ bit_size: 1
+ - name: DIEROKCF
+ description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
+ bit_offset: 24
+ bit_size: 1
+fieldset/ISR_ADV:
+ extends: ISR_BASIC
+ description: LPTIM interrupt and status register.
+ fields:
+ - name: CCIF
+ description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 2
+ stride: 9
+ - name: CMPOK
+ description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
+ bit_offset: 3
+ bit_size: 1
+ array:
+ len: 2
+ stride: 16
+ - name: CCOF
+ description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
+ bit_offset: 12
+ bit_size: 1
+ array:
+ len: 2
+ stride: 1
+fieldset/ISR_BASIC:
+ description: LPTIM interrupt and status register.
+ fields:
+ - name: CCIF
+ description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
+ bit_offset: 0
+ bit_size: 1
+ array:
+ len: 1
+ stride: 9
+ - name: ARRM
+ description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTTRIG
+ description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
+ bit_offset: 2
+ bit_size: 1
+ - name: CMPOK
+ description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
+ bit_offset: 3
+ bit_size: 1
+ array:
+ len: 1
+ stride: 16
+ - name: ARROK
+ description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
+ bit_offset: 4
+ bit_size: 1
+ - name: UP
+ description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 5
+ bit_size: 1
+ - name: DOWN
+ description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+ bit_offset: 6
+ bit_size: 1
+ - name: UE
+ description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
+ bit_offset: 7
+ bit_size: 1
+ - name: REPOK
+ description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.
+ bit_offset: 8
+ bit_size: 1
+ - name: DIEROK
+ description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
+ bit_offset: 24
+ bit_size: 1
+fieldset/RCR:
+ description: LPTIM repetition register.
+ fields:
+ - name: REP
+ description: Repetition register value REP is the repetition value for the LPTIM.
+ bit_offset: 0
+ bit_size: 8
+enum/CCP_Input:
+ bit_size: 2
+ variants:
+ - name: Rising
+ value: 0
+ - name: Falling
+ value: 1
+ - name: Both
+ value: 3
+enum/CCP_Output:
+ bit_size: 2
+ variants:
+ - name: ActiveHigh
+ value: 0
+ - name: ActiveLow
+ value: 1
+enum/CCSEL:
+ bit_size: 1
+ variants:
+ - name: OutputCompare
+ description: channel is configured in output PWM mode
+ value: 0
+ - name: InputCapture
+ description: channel is configured in input capture mode
+ value: 1
+enum/CKPOL:
+ bit_size: 2
+ variants:
+ - name: Rising
+ description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.
+ value: 0
+ - name: Falling
+ description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.
+ value: 1
+ - name: Both
+ description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
+ value: 2
+enum/CKSEL:
+ bit_size: 1
+ variants:
+ - name: Internal
+ description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
+ value: 0
+ - name: External
+ description: LPTIM is clocked by an external clock source through the LPTIM external Input1
+ value: 1
+enum/Filter:
+ bit_size: 2
+ variants:
+ - name: Count1
+ value: 0
+ - name: Count2
+ value: 1
+ - name: Count4
+ value: 2
+ - name: Count8
+ value: 3
+enum/PRESC:
+ bit_size: 3
+ variants:
+ - name: Div1
+ value: 0
+ - name: Div2
+ value: 1
+ - name: Div4
+ value: 2
+ - name: Div8
+ value: 3
+ - name: Div16
+ value: 4
+ - name: Div32
+ value: 5
+ - name: Div64
+ value: 6
+ - name: Div128
+ value: 7
+enum/TRIGEN:
+ bit_size: 2
+ variants:
+ - name: Software
+ description: software trigger (counting start is initiated by software)
+ value: 0
+ - name: RisingEdge
+ description: rising edge is the active edge
+ value: 1
+ - name: FallingEdge
+ description: falling edge is the active edge
+ value: 2
+ - name: BothEdge
+ description: both edges are active edges
+ value: 3
diff --git a/data/registers/pwr_u0.yaml b/data/registers/pwr_u0.yaml
new file mode 100644
index 0000000..778a451
--- /dev/null
+++ b/data/registers/pwr_u0.yaml
@@ -0,0 +1,978 @@
+block/PWR:
+ description: PWR register block
+ items:
+ - name: CR1
+ description: Power control register 1
+ byte_offset: 0
+ fieldset: CR1
+ - name: CR2
+ description: Power control register 2
+ byte_offset: 4
+ fieldset: CR2
+ - name: CR3
+ description: Power control register 3
+ byte_offset: 8
+ fieldset: CR3
+ - name: CR4
+ description: Power control register 4
+ byte_offset: 12
+ fieldset: CR4
+ - name: SR1
+ description: Power status register 1
+ byte_offset: 16
+ fieldset: SR1
+ - name: SR2
+ description: Power status register 2
+ byte_offset: 20
+ fieldset: SR2
+ - name: SCR
+ description: Power status clear register
+ byte_offset: 24
+ fieldset: SCR
+ - name: PUCRA
+ description: Power Port A pull-up control register
+ byte_offset: 32
+ fieldset: PUCRA
+ - name: PDCRA
+ description: Power Port A pull-down control register
+ byte_offset: 36
+ fieldset: PDCRA
+ - name: PUCRB
+ description: Power Port B pull-up control register
+ byte_offset: 40
+ fieldset: PUCRB
+ - name: PDCRB
+ description: Power Port B pull-down control register
+ byte_offset: 44
+ fieldset: PDCRB
+ - name: PUCRC
+ description: Power Port C pull-up control register
+ byte_offset: 48
+ fieldset: PUCRC
+ - name: PDCRC
+ description: Power Port C pull-down control register
+ byte_offset: 52
+ fieldset: PDCRC
+ - name: PUCRD
+ description: Power Port D pull-up control register
+ byte_offset: 56
+ fieldset: PUCRD
+ - name: PDCRD
+ description: Power Port D pull-down control register
+ byte_offset: 60
+ fieldset: PDCRD
+ - name: PUCRE
+ description: Power Port E pull-up control register
+ byte_offset: 64
+ fieldset: PUCRE
+ - name: PDCRE
+ description: Power Port E pull-down control register
+ byte_offset: 68
+ fieldset: PDCRE
+ - name: PUCRF
+ description: Power Port F pull-up control register
+ byte_offset: 72
+ fieldset: PUCRF
+ - name: PDCRF
+ description: Power Port F pull-down control register
+ byte_offset: 76
+ fieldset: PDCRF
+fieldset/CR1:
+ description: Power control register 1
+ fields:
+ - name: LPMS
+ description: 'Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.'
+ bit_offset: 0
+ bit_size: 3
+ enum: LPMS
+ - name: FPD_STOP
+ description: Flash memory powered down during Stop mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode.
+ bit_offset: 3
+ bit_size: 1
+ - name: FPD_LPRUN
+ description: Flash memory powered down during Low-power run mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode.
+ bit_offset: 4
+ bit_size: 1
+ - name: FPD_LPSLP
+ description: Flash memory powered down during Low-power sleep mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode.
+ bit_offset: 5
+ bit_size: 1
+ - name: DBP
+ description: Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.
+ bit_offset: 8
+ bit_size: 1
+ - name: VOS
+ description: Voltage scaling range selection
+ bit_offset: 9
+ bit_size: 2
+ enum: VOS
+ - name: LPR
+ description: 'Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.'
+ bit_offset: 14
+ bit_size: 1
+fieldset/CR2:
+ description: Power control register 2
+ fields:
+ - name: PVDE
+ description: 'Programmable voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset.'
+ bit_offset: 0
+ bit_size: 1
+ - name: PLS
+ description: 'Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset.'
+ bit_offset: 1
+ bit_size: 3
+ enum: PLS
+ - name: PVME1
+ description: 'Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.21V'
+ bit_offset: 4
+ bit_size: 1
+ - name: PVME3
+ description: 'Peripheral voltage monitoring 3 enable: VDDA vs. 1.621V'
+ bit_offset: 5
+ bit_size: 1
+ - name: PVME4
+ description: 'Peripheral voltage monitoring 4 enable: VDDA vs. 1.861V'
+ bit_offset: 6
+ bit_size: 1
+ - name: USV
+ description: VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not.
+ bit_offset: 10
+ bit_size: 1
+fieldset/CR3:
+ description: Power control register 3
+ fields:
+ - name: EWUP1
+ description: Enable Wake-up pin WKUP1 When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: EWUP2
+ description: Enable Wake-up pin WKUP2 When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: EWUP3
+ description: Enable Wake-up pin WKUP3 When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: EWUP4
+ description: Enable Wake-up pin WKUP4 When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: EWUP5
+ description: Enable Wake-up pin WKUP5 When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: EWUP7
+ description: Enable Wake-up pin WKUP7. When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: RRS
+ description: SRAM2 retention in Standby mode
+ bit_offset: 8
+ bit_size: 1
+ - name: ENULP
+ description: Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes.
+ bit_offset: 9
+ bit_size: 1
+ - name: APC
+ description: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode.
+ bit_offset: 10
+ bit_size: 1
+ - name: EIWUL
+ description: Enable internal wake-up line
+ bit_offset: 15
+ bit_size: 1
+fieldset/CR4:
+ description: Power control register 4
+ fields:
+ - name: WP1
+ description: Wake-up pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
+ bit_offset: 0
+ bit_size: 1
+ - name: WP2
+ description: Wake-up pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
+ bit_offset: 1
+ bit_size: 1
+ - name: WP3
+ description: Wake-up pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
+ bit_offset: 2
+ bit_size: 1
+ - name: WP4
+ description: Wake-up pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
+ bit_offset: 3
+ bit_size: 1
+ - name: WP5
+ description: Wake-up pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
+ bit_offset: 4
+ bit_size: 1
+ - name: WP7
+ description: Wake-up pin WKUP7 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP7
+ bit_offset: 6
+ bit_size: 1
+ - name: VBE
+ description: VBAT battery charging enable
+ bit_offset: 8
+ bit_size: 1
+ - name: VBRS
+ description: VBAT battery charging resistor selection
+ bit_offset: 9
+ bit_size: 1
+fieldset/PDCRA:
+ description: Power Port A pull-down control register
+ fields:
+ - name: PD0
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: PD1
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: PD2
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: PD3
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: PD4
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: PD5
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 5
+ bit_size: 1
+ - name: PD6
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: PD7
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 7
+ bit_size: 1
+ - name: PD8
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 8
+ bit_size: 1
+ - name: PD9
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 9
+ bit_size: 1
+ - name: PD10
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 10
+ bit_size: 1
+ - name: PD11
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 11
+ bit_size: 1
+ - name: PD12
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 12
+ bit_size: 1
+ - name: PD13
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 13
+ bit_size: 1
+ - name: PD14
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 14
+ bit_size: 1
+ - name: PD15
+ description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 15
+ bit_size: 1
+fieldset/PDCRB:
+ description: Power Port B pull-down control register
+ fields:
+ - name: PD0
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: PD1
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: PD2
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: PD3
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: PD4
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: PD5
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 5
+ bit_size: 1
+ - name: PD6
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: PD7
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 7
+ bit_size: 1
+ - name: PD8
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 8
+ bit_size: 1
+ - name: PD9
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 9
+ bit_size: 1
+ - name: PD10
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 10
+ bit_size: 1
+ - name: PD11
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 11
+ bit_size: 1
+ - name: PD12
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 12
+ bit_size: 1
+ - name: PD13
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 13
+ bit_size: 1
+ - name: PD14
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 14
+ bit_size: 1
+ - name: PD15
+ description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 15
+ bit_size: 1
+fieldset/PDCRC:
+ description: Power Port C pull-down control register
+ fields:
+ - name: PD0
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: PD1
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: PD2
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: PD3
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: PD4
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: PD5
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 5
+ bit_size: 1
+ - name: PD6
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: PD7
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 7
+ bit_size: 1
+ - name: PD8
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 8
+ bit_size: 1
+ - name: PD9
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 9
+ bit_size: 1
+ - name: PD10
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 10
+ bit_size: 1
+ - name: PD11
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 11
+ bit_size: 1
+ - name: PD12
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 12
+ bit_size: 1
+ - name: PD13
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 13
+ bit_size: 1
+ - name: PD14
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 14
+ bit_size: 1
+ - name: PD15
+ description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 15
+ bit_size: 1
+fieldset/PDCRD:
+ description: Power Port D pull-down control register
+ fields:
+ - name: PD0
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: PD1
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: PD2
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: PD3
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: PD4
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: PD5
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 5
+ bit_size: 1
+ - name: PD6
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: PD8
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 8
+ bit_size: 1
+ - name: PD9
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 9
+ bit_size: 1
+ - name: PD10
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 10
+ bit_size: 1
+ - name: PD11
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 11
+ bit_size: 1
+ - name: PD12
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 12
+ bit_size: 1
+ - name: PD13
+ description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 13
+ bit_size: 1
+fieldset/PDCRE:
+ description: Power Port E pull-down control register
+ fields:
+ - name: PD3
+ description: Port E pull-down bit 3 When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: PD7
+ description: Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 7
+ bit_size: 1
+ - name: PD8
+ description: Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 8
+ bit_size: 1
+ - name: PD9
+ description: Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 9
+ bit_size: 1
+fieldset/PDCRF:
+ description: Power Port F pull-down control register
+ fields:
+ - name: PD0
+ description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: PD1
+ description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: PD2
+ description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: PD3
+ description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+fieldset/PUCRA:
+ description: Power Port A pull-up control register
+ fields:
+ - name: PU0
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 0
+ bit_size: 1
+ - name: PU1
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 1
+ bit_size: 1
+ - name: PU2
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 2
+ bit_size: 1
+ - name: PU3
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 3
+ bit_size: 1
+ - name: PU4
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 4
+ bit_size: 1
+ - name: PU5
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 5
+ bit_size: 1
+ - name: PU6
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 6
+ bit_size: 1
+ - name: PU7
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 7
+ bit_size: 1
+ - name: PU8
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 8
+ bit_size: 1
+ - name: PU9
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 9
+ bit_size: 1
+ - name: PU10
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 10
+ bit_size: 1
+ - name: PU11
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 11
+ bit_size: 1
+ - name: PU12
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 12
+ bit_size: 1
+ - name: PU13
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 13
+ bit_size: 1
+ - name: PU14
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 14
+ bit_size: 1
+ - name: PU15
+ description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 15
+ bit_size: 1
+fieldset/PUCRB:
+ description: Power Port B pull-up control register
+ fields:
+ - name: PU0
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: PU1
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: PU2
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: PU3
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: PU4
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: PU5
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 5
+ bit_size: 1
+ - name: PU6
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: PU7
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 7
+ bit_size: 1
+ - name: PU8
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 8
+ bit_size: 1
+ - name: PU9
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 9
+ bit_size: 1
+ - name: PU10
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 10
+ bit_size: 1
+ - name: PU11
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 11
+ bit_size: 1
+ - name: PU12
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 12
+ bit_size: 1
+ - name: PU13
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 13
+ bit_size: 1
+ - name: PU14
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 14
+ bit_size: 1
+ - name: PU15
+ description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
+ bit_offset: 15
+ bit_size: 1
+fieldset/PUCRC:
+ description: Power Port C pull-up control register
+ fields:
+ - name: PU0
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 0
+ bit_size: 1
+ - name: PU1
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 1
+ bit_size: 1
+ - name: PU2
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 2
+ bit_size: 1
+ - name: PU3
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 3
+ bit_size: 1
+ - name: PU4
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 4
+ bit_size: 1
+ - name: PU5
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 5
+ bit_size: 1
+ - name: PU6
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 6
+ bit_size: 1
+ - name: PU7
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 7
+ bit_size: 1
+ - name: PU8
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 8
+ bit_size: 1
+ - name: PU9
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 9
+ bit_size: 1
+ - name: PU10
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 10
+ bit_size: 1
+ - name: PU11
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 11
+ bit_size: 1
+ - name: PU12
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 12
+ bit_size: 1
+ - name: PU13
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 13
+ bit_size: 1
+ - name: PU14
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 14
+ bit_size: 1
+ - name: PU15
+ description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 15
+ bit_size: 1
+fieldset/PUCRD:
+ description: Power Port D pull-up control register
+ fields:
+ - name: PU0
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 0
+ bit_size: 1
+ - name: PU1
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 1
+ bit_size: 1
+ - name: PU2
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 2
+ bit_size: 1
+ - name: PU3
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 3
+ bit_size: 1
+ - name: PU4
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 4
+ bit_size: 1
+ - name: PU5
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 5
+ bit_size: 1
+ - name: PU6
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 6
+ bit_size: 1
+ - name: PU8
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 8
+ bit_size: 1
+ - name: PU9
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 9
+ bit_size: 1
+ - name: PU10
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 10
+ bit_size: 1
+ - name: PU11
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 11
+ bit_size: 1
+ - name: PU12
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 12
+ bit_size: 1
+ - name: PU13
+ description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 13
+ bit_size: 1
+fieldset/PUCRE:
+ description: Power Port E pull-up control register
+ fields:
+ - name: PU3
+ description: Port E pull-up bit 3 When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 3
+ bit_size: 1
+ - name: PU7
+ description: Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 7
+ bit_size: 1
+ - name: PU8
+ description: Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 8
+ bit_size: 1
+ - name: PU9
+ description: Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 9
+ bit_size: 1
+fieldset/PUCRF:
+ description: Power Port F pull-up control register
+ fields:
+ - name: PU0
+ description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 0
+ bit_size: 1
+ - name: PU1
+ description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 1
+ bit_size: 1
+ - name: PU2
+ description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 2
+ bit_size: 1
+ - name: PU3
+ description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
+ bit_offset: 3
+ bit_size: 1
+fieldset/SCR:
+ description: Power status clear register
+ fields:
+ - name: CWUF1
+ description: Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
+ bit_offset: 0
+ bit_size: 1
+ - name: CWUF2
+ description: Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register.
+ bit_offset: 1
+ bit_size: 1
+ - name: CWUF3
+ description: Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register.
+ bit_offset: 2
+ bit_size: 1
+ - name: CWUF4
+ description: Clear wake-up flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register.
+ bit_offset: 3
+ bit_size: 1
+ - name: CWUF5
+ description: Clear wake-up flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register.
+ bit_offset: 4
+ bit_size: 1
+ - name: CWUF7
+ description: Clear wake-up flag 7 Setting this bit clears the WUF7 flag in the PWR_SR1 register.
+ bit_offset: 6
+ bit_size: 1
+ - name: CSBF
+ description: Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register.
+ bit_offset: 8
+ bit_size: 1
+fieldset/SR1:
+ description: Power status register 1
+ fields:
+ - name: WUF1
+ description: Wake-up flag 1 This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register.
+ bit_offset: 0
+ bit_size: 1
+ - name: WUF2
+ description: Wake-up flag 2 This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register.
+ bit_offset: 1
+ bit_size: 1
+ - name: WUF3
+ description: Wake-up flag 3 This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register.
+ bit_offset: 2
+ bit_size: 1
+ - name: WUF4
+ description: Wake-up flag 4 This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register.
+ bit_offset: 3
+ bit_size: 1
+ - name: WUF5
+ description: Wake-up flag 5 This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register.
+ bit_offset: 4
+ bit_size: 1
+ - name: WUF7
+ description: Wake-up flag 7 This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register.
+ bit_offset: 6
+ bit_size: 1
+ - name: SBF
+ description: Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
+ bit_offset: 8
+ bit_size: 1
+ - name: STOPF
+ description: Stop Flags These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
+ bit_offset: 9
+ bit_size: 3
+ enum: STOPF
+ - name: WUFI
+ description: Wake-up flag internal This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared.
+ bit_offset: 15
+ bit_size: 1
+fieldset/SR2:
+ description: Power status register 2
+ fields:
+ - name: FLASH_RDY
+ description: 'Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory.'
+ bit_offset: 7
+ bit_size: 1
+ - name: REGLPS
+ description: Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased.
+ bit_offset: 8
+ bit_size: 1
+ - name: REGLPF
+ description: Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready.
+ bit_offset: 9
+ bit_size: 1
+ - name: VOSF
+ description: Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.
+ bit_offset: 10
+ bit_size: 1
+ - name: PVDO
+ description: Programmable voltage detector output
+ bit_offset: 11
+ bit_size: 1
+ - name: PVMO1
+ description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time.'
+ bit_offset: 12
+ bit_size: 1
+ - name: PVMO3
+ description: 'Peripheral voltage monitoring output: VDDA vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time.'
+ bit_offset: 14
+ bit_size: 1
+ - name: PVMO4
+ description: 'Peripheral voltage monitoring output: VDDA vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time.'
+ bit_offset: 15
+ bit_size: 1
+enum/LPMS:
+ bit_size: 3
+ variants:
+ - name: Stop0
+ description: Stop 0 mode
+ value: 0
+ - name: Stop1
+ description: Stop 1 mode
+ value: 1
+ - name: Stop2
+ description: Stop 2 mode
+ value: 2
+ - name: Standby
+ description: Standby mode
+ value: 3
+enum/PLS:
+ bit_size: 3
+ variants:
+ - name: B_0x0
+ description: VPVD0 around 2.01V
+ value: 0
+ - name: B_0x1
+ description: VPVD1 around 2.21V
+ value: 1
+ - name: B_0x2
+ description: VPVD2 around 2.41V
+ value: 2
+ - name: B_0x3
+ description: VPVD3 around 2.51V
+ value: 3
+ - name: B_0x4
+ description: VPVD4 around 2.61V
+ value: 4
+ - name: B_0x5
+ description: VPVD5 around 2.81V
+ value: 5
+ - name: B_0x6
+ description: VPVD6 around 2.91V
+ value: 6
+ - name: B_0x7
+ description: External input analog voltage PVD_IN (compared internally to VREFINT)
+ value: 7
+enum/STOPF:
+ bit_size: 3
+ variants:
+ - name: None
+ description: The device did not enter any Stop mode.
+ value: 0
+ - name: Stop0
+ description: The device entered in Stop 0 mode.
+ value: 4
+ - name: Stop1
+ description: The device entered in Stop 1 mode.
+ value: 5
+ - name: Stop2
+ description: The device entered in Stop 2 mode.
+ value: 6
+enum/VOS:
+ bit_size: 2
+ variants:
+ - name: Range1
+ description: Range 1
+ value: 1
+ - name: Range2
+ description: Range 2
+ value: 2
diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml
index c58645e..554992a 100644
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@@ -486,8 +486,8 @@ fieldset/AHB3ENR:
description: FMC Peripheral Clocks Enable
bit_offset: 12
bit_size: 1
- - name: QUADSPIEN
- description: QUADSPI and QUADSPI Delay Clock Enable
+ - name: OCTOSPI1EN
+ description: OCTOSPI1 and OCTOSPI1 Delay Clock Enable
bit_offset: 14
bit_size: 1
- name: SDMMC1EN
@@ -549,8 +549,8 @@ fieldset/AHB3LPENR:
description: FMC Peripheral Clocks Enable During CSleep Mode
bit_offset: 12
bit_size: 1
- - name: QUADSPILPEN
- description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode
+ - name: OCTOSPI1LPEN
+ description: OCTOSPI1 and OCTOSPI1 Delay Clock Enable During CSleep Mode
bit_offset: 14
bit_size: 1
- name: SDMMC1LPEN
@@ -608,8 +608,8 @@ fieldset/AHB3RSTR:
description: FMC block reset
bit_offset: 12
bit_size: 1
- - name: QUADSPIRST
- description: QUADSPI and QUADSPI delay block reset
+ - name: OCTOSPI1RST
+ description: OCTOSPI1 and OCTOSPI1 delay block reset
bit_offset: 14
bit_size: 1
- name: SDMMC1RST
diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml
index c07e84d..17e9f27 100644
--- a/data/registers/rcc_l4plus.yaml
+++ b/data/registers/rcc_l4plus.yaml
@@ -311,7 +311,7 @@ fieldset/AHB2ENR:
description: Random Number Generator clock enable
bit_offset: 18
bit_size: 1
- - name: OSPIMEN
+ - name: OCTOSPIMEN
description: OctoSPI IO manager clock enable
bit_offset: 20
bit_size: 1
@@ -390,7 +390,7 @@ fieldset/AHB2RSTR:
description: Random number generator reset
bit_offset: 18
bit_size: 1
- - name: OSPIMRST
+ - name: OCTOSPIMRST
description: OCTOSPI IO manager reset
bit_offset: 20
bit_size: 1
@@ -485,7 +485,7 @@ fieldset/AHB2SMENR:
description: Random Number Generator clocks enable during Sleep and Stop modes
bit_offset: 18
bit_size: 1
- - name: OSPIMSMEN
+ - name: OCTOSPIMSMEN
description: OctoSPI IO manager clocks enable during Sleep and Stop modes
bit_offset: 20
bit_size: 1
@@ -504,11 +504,11 @@ fieldset/AHB3ENR:
description: Flexible memory controller clock enable
bit_offset: 0
bit_size: 1
- - name: OSPI1EN
+ - name: OCTOSPI1EN
description: OctoSPI1 memory interface clock enable
bit_offset: 8
bit_size: 1
- - name: OSPI2EN
+ - name: OCTOSPI2EN
description: OSPI2EN memory interface clock enable
bit_offset: 9
bit_size: 1
@@ -519,11 +519,11 @@ fieldset/AHB3RSTR:
description: Flexible memory controller reset
bit_offset: 0
bit_size: 1
- - name: OSPI1RST
+ - name: OCTOSPI1RST
description: OctoSPI1 memory interface reset
bit_offset: 8
bit_size: 1
- - name: OSPI2RST
+ - name: OCTOSPI2RST
description: OctOSPI2 memory interface reset
bit_offset: 9
bit_size: 1
@@ -534,11 +534,11 @@ fieldset/AHB3SMENR:
description: Flexible memory controller clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- - name: OSPI1SMEN
+ - name: OCTOSPI1SMEN
description: OctoSPI1 memory interface clocks enable during Sleep and Stop modes
bit_offset: 8
bit_size: 1
- - name: OCTOSPI2
+ - name: OCTOSPI2SMEN
description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes
bit_offset: 9
bit_size: 1
@@ -1197,11 +1197,11 @@ fieldset/CCIPR2:
description: division factor for LTDC clock
bit_offset: 16
bit_size: 2
- - name: OSPISEL
+ - name: OCTOSPISEL
description: Octospi clock source selection
bit_offset: 20
bit_size: 2
- enum: OSPISEL
+ enum: OCTOSPISEL
fieldset/CFGR:
description: Clock configuration register
fields:
@@ -1962,7 +1962,7 @@ enum/MSIRGSEL:
- name: CR
description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register
value: 1
-enum/OSPISEL:
+enum/OCTOSPISEL:
bit_size: 2
variants:
- name: SYS
diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml
index 947f3c3..d77b0cd 100644
--- a/data/registers/rcc_l5.yaml
+++ b/data/registers/rcc_l5.yaml
@@ -556,8 +556,8 @@ fieldset/AHB3ENR:
description: Flexible memory controller clock enable
bit_offset: 0
bit_size: 1
- - name: OSPI1EN
- description: OSPI1EN
+ - name: OCTOSPI1EN
+ description: OCTOSPI1EN
bit_offset: 8
bit_size: 1
fieldset/AHB3RSTR:
@@ -567,8 +567,8 @@ fieldset/AHB3RSTR:
description: Flexible memory controller reset
bit_offset: 0
bit_size: 1
- - name: OSPI1RST
- description: OSPI1RST
+ - name: OCTOSPI1RST
+ description: OCTOSPI1RST
bit_offset: 8
bit_size: 1
fieldset/AHB3SECSR:
@@ -578,8 +578,8 @@ fieldset/AHB3SECSR:
description: FSMCSECF
bit_offset: 0
bit_size: 1
- - name: OSPI1SECF
- description: OSPI1SECF
+ - name: OCTOSPI1SECF
+ description: OCTOSPI1SECF
bit_offset: 8
bit_size: 1
fieldset/AHB3SMENR:
@@ -589,8 +589,8 @@ fieldset/AHB3SMENR:
description: Flexible memory controller clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- - name: OSPI1SMEN
- description: OSPI1SMEN
+ - name: OCTOSPI1SMEN
+ description: OCTOSPI1SMEN
bit_offset: 8
bit_size: 1
fieldset/APB1ENR1:
@@ -1412,7 +1412,7 @@ fieldset/CCIPR2:
description: SDMMC clock selection
bit_offset: 14
bit_size: 1
- - name: OSPISEL
+ - name: OCTOSPISEL
description: Octospi clock source selection
bit_offset: 20
bit_size: 2
diff --git a/data/registers/rcc_u0.yaml b/data/registers/rcc_u0.yaml
new file mode 100644
index 0000000..c1dbd8e
--- /dev/null
+++ b/data/registers/rcc_u0.yaml
@@ -0,0 +1,1911 @@
+block/RCC:
+ description: RCC address block description.
+ items:
+ - name: CR
+ description: Clock control register.
+ byte_offset: 0
+ fieldset: CR
+ - name: ICSCR
+ description: Internal clock sources calibration register.
+ byte_offset: 4
+ fieldset: ICSCR
+ - name: CFGR
+ description: Clock configuration register.
+ byte_offset: 8
+ fieldset: CFGR
+ - name: PLLCFGR
+ description: PLL configuration register.
+ byte_offset: 12
+ fieldset: PLLCFGR
+ - name: CIER
+ description: Clock interrupt enable register.
+ byte_offset: 24
+ fieldset: CIER
+ - name: CIFR
+ description: Clock interrupt flag register.
+ byte_offset: 28
+ fieldset: CIFR
+ - name: CICR
+ description: Clock interrupt clear register.
+ byte_offset: 32
+ fieldset: CICR
+ - name: AHBRSTR
+ description: AHB peripheral reset register.
+ byte_offset: 40
+ fieldset: AHBRSTR
+ - name: GPIORSTR
+ description: I/O port reset register.
+ byte_offset: 44
+ fieldset: GPIORSTR
+ - name: APBRSTR1
+ description: APB peripheral reset register 1.
+ byte_offset: 56
+ fieldset: APBRSTR1
+ - name: APBRSTR2
+ description: APB peripheral reset register 2.
+ byte_offset: 64
+ fieldset: APBRSTR2
+ - name: AHBENR
+ description: AHB peripheral clock enable register.
+ byte_offset: 72
+ fieldset: AHBENR
+ - name: GPIOENR
+ description: I/O port clock enable register.
+ byte_offset: 76
+ fieldset: GPIOENR
+ - name: DBGCFGR
+ description: Debug configuration register.
+ byte_offset: 80
+ fieldset: DBGCFGR
+ - name: APBENR1
+ description: APB peripheral clock enable register 1.
+ byte_offset: 88
+ fieldset: APBENR1
+ - name: APBENR2
+ description: APB peripheral clock enable register 2.
+ byte_offset: 96
+ fieldset: APBENR2
+ - name: AHBSMENR
+ description: AHB peripheral clock enable in Sleep/Stop mode register.
+ byte_offset: 104
+ fieldset: AHBSMENR
+ - name: GPIOSMENR
+ description: I/O port in Sleep mode clock enable register.
+ byte_offset: 108
+ fieldset: GPIOSMENR
+ - name: APBSMENR1
+ description: APB peripheral clock enable in Sleep/Stop mode register 1.
+ byte_offset: 120
+ fieldset: APBSMENR1
+ - name: APBSMENR2
+ description: APB peripheral clock enable in Sleep/Stop mode register 2.
+ byte_offset: 128
+ fieldset: APBSMENR2
+ - name: CCIPR
+ description: Peripherals independent clock configuration register.
+ byte_offset: 136
+ fieldset: CCIPR
+ - name: BDCR
+ description: RTC domain control register.
+ byte_offset: 144
+ fieldset: BDCR
+ - name: CSR
+ description: Control/status register.
+ byte_offset: 148
+ fieldset: CSR
+ - name: CRRCR
+ description: RCC clock recovery RC register.
+ byte_offset: 152
+ fieldset: CRRCR
+fieldset/AHBENR:
+ description: AHB peripheral clock enable register.
+ fields:
+ - name: DMA1EN
+ description: DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled.
+ bit_offset: 0
+ bit_size: 1
+ - name: DMA2EN
+ description: DMA2 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled.
+ bit_offset: 1
+ bit_size: 1
+ - name: FLASHEN
+ description: Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the flash memory is in power down mode.
+ bit_offset: 8
+ bit_size: 1
+ - name: CRCEN
+ description: CRC clock enable Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: AESEN
+ description: AES hardware accelerator Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: RNGEN
+ description: Random number generator clock enable Set and cleared by software.
+ bit_offset: 18
+ bit_size: 1
+ - name: TSCEN
+ description: Touch sensing controller clock enable Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+fieldset/AHBRSTR:
+ description: AHB peripheral reset register.
+ fields:
+ - name: DMA1RST
+ description: DMA1 and DMAMUX reset Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: DMA2RST
+ description: DMA2 and DMAMUX reset Set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: FLASHRST
+ description: Flash memory interface reset Set and cleared by software. This bit can only be set when the flash memory is in power down mode.
+ bit_offset: 8
+ bit_size: 1
+ - name: CRCRST
+ description: CRC reset Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: AESRST
+ description: AES hardware accelerator reset Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: RNGRST
+ description: Random number generator reset Set and cleared by software.
+ bit_offset: 18
+ bit_size: 1
+ - name: TSCRST
+ description: Touch sensing controller reset Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+fieldset/AHBSMENR:
+ description: AHB peripheral clock enable in Sleep/Stop mode register.
+ fields:
+ - name: DMA1SMEN
+ description: DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.
+ bit_offset: 0
+ bit_size: 1
+ - name: DMA2SMEN
+ description: DMA2 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.
+ bit_offset: 1
+ bit_size: 1
+ - name: FLASHSMEN
+ description: Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the flash memory is in power down mode.
+ bit_offset: 8
+ bit_size: 1
+ - name: SRAMSMEN
+ description: SRAM clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 9
+ bit_size: 1
+ - name: CRCSMEN
+ description: CRC clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: AESSMEN
+ description: AES hardware accelerator clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: RNGSMEN
+ description: RNG clock enable during Sleep and Stop mode Set and cleared by software.
+ bit_offset: 18
+ bit_size: 1
+ - name: TSCSMEN
+ description: TSC clock enable during Sleep and Stop mode Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+fieldset/APBENR1:
+ description: APB peripheral clock enable register 1.
+ fields:
+ - name: TIM2EN
+ description: TIM2 timer clock enable Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM3EN
+ description: TIM3 timer clock enable Set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: TIM6EN
+ description: TIM6 timer clock enable Set and cleared by software.
+ bit_offset: 4
+ bit_size: 1
+ - name: TIM7EN
+ description: TIM7 timer clock enable Set and cleared by software.
+ bit_offset: 5
+ bit_size: 1
+ - name: LPUART2EN
+ description: LPUART2 clock enable Set and cleared by software.
+ bit_offset: 7
+ bit_size: 1
+ - name: LCDEN
+ description: LCD clock enable(1) Set and cleared by software.
+ bit_offset: 9
+ bit_size: 1
+ - name: RTCAPBEN
+ description: RTC APB clock enable Set and cleared by software.
+ bit_offset: 10
+ bit_size: 1
+ - name: WWDGEN
+ description: WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0.
+ bit_offset: 11
+ bit_size: 1
+ - name: LPUART3EN
+ description: LPUART3 clock enable Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: USBEN
+ description: USB clock enable(1) Set and cleared by software.
+ bit_offset: 13
+ bit_size: 1
+ - name: SPI2EN
+ description: SPI2 clock enable Set and cleared by software.
+ bit_offset: 14
+ bit_size: 1
+ - name: SPI3EN
+ description: SPI3 clock enable(1) Set and cleared by software.
+ bit_offset: 15
+ bit_size: 1
+ - name: CRSEN
+ description: CRS clock enable(1) Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: USART2EN
+ description: USART2 clock enable Set and cleared by software.
+ bit_offset: 17
+ bit_size: 1
+ - name: USART3EN
+ description: USART3 clock enable Set and cleared by software.
+ bit_offset: 18
+ bit_size: 1
+ - name: USART4EN
+ description: USART4 clock enable Set and cleared by software.
+ bit_offset: 19
+ bit_size: 1
+ - name: LPUART1EN
+ description: LPUART1 clock enable Set and cleared by software.
+ bit_offset: 20
+ bit_size: 1
+ - name: I2C1EN
+ description: I2C1 clock enable Set and cleared by software.
+ bit_offset: 21
+ bit_size: 1
+ - name: I2C2EN
+ description: I2C2 clock enable Set and cleared by software.
+ bit_offset: 22
+ bit_size: 1
+ - name: I2C3EN
+ description: I2C3 clock enable Set and cleared by software.
+ bit_offset: 23
+ bit_size: 1
+ - name: OPAMPEN
+ description: OPAMP clock enable Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+ - name: I2C4EN
+ description: I2C4EN clock enable(1) Set and cleared by software.
+ bit_offset: 25
+ bit_size: 1
+ - name: LPTIM3EN
+ description: LPTIM3 clock enable Set and cleared by software.
+ bit_offset: 26
+ bit_size: 1
+ - name: PWREN
+ description: Power interface clock enable Set and cleared by software.
+ bit_offset: 28
+ bit_size: 1
+ - name: DAC1EN
+ description: DAC1 interface clock enable Set and cleared by software.
+ bit_offset: 29
+ bit_size: 1
+ - name: LPTIM2EN
+ description: LPTIM2 clock enable Set and cleared by software.
+ bit_offset: 30
+ bit_size: 1
+ - name: LPTIM1EN
+ description: LPTIM1 clock enable Set and cleared by software.
+ bit_offset: 31
+ bit_size: 1
+fieldset/APBENR2:
+ description: APB peripheral clock enable register 2.
+ fields:
+ - name: SYSCFGEN
+ description: SYSCFG, COMP and VREFBUF clock enable Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM1EN
+ description: TIM1 timer clock enable Set and cleared by software.
+ bit_offset: 11
+ bit_size: 1
+ - name: SPI1EN
+ description: SPI1 clock enable Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: USART1EN
+ description: USART1 clock enable Set and cleared by software.
+ bit_offset: 14
+ bit_size: 1
+ - name: TIM15EN
+ description: TIM15 timer clock enable Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: TIM16EN
+ description: TIM16 timer clock enable Set and cleared by software.
+ bit_offset: 17
+ bit_size: 1
+ - name: ADCEN
+ description: ADC clock enable Set and cleared by software.
+ bit_offset: 20
+ bit_size: 1
+fieldset/APBRSTR1:
+ description: APB peripheral reset register 1.
+ fields:
+ - name: TIM2RST
+ description: TIM2 timer reset Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM3RST
+ description: TIM3 timer reset Set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: TIM6RST
+ description: TIM6 timer reset Set and cleared by software.
+ bit_offset: 4
+ bit_size: 1
+ - name: TIM7RST
+ description: TIM7 timer reset Set and cleared by software.
+ bit_offset: 5
+ bit_size: 1
+ - name: LPUART2RST
+ description: LPUART2 reset Set and cleared by software.
+ bit_offset: 7
+ bit_size: 1
+ - name: LCDRST
+ description: LCD reset(1) Set and cleared by software.
+ bit_offset: 9
+ bit_size: 1
+ - name: LPUART3RST
+ description: LPUART3 reset(1) Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: USBRST
+ description: USB reset(1) Set and cleared by software.
+ bit_offset: 13
+ bit_size: 1
+ - name: SPI2RST
+ description: SPI2 reset Set and cleared by software.
+ bit_offset: 14
+ bit_size: 1
+ - name: SPI3RST
+ description: SPI3 reset(1) Set and cleared by software.
+ bit_offset: 15
+ bit_size: 1
+ - name: CRSRST
+ description: CRS reset(1) Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: USART2RST
+ description: USART2 reset Set and cleared by software.
+ bit_offset: 17
+ bit_size: 1
+ - name: USART3RST
+ description: USART3 reset Set and cleared by software.
+ bit_offset: 18
+ bit_size: 1
+ - name: USART4RST
+ description: USART4 reset Set and cleared by software.
+ bit_offset: 19
+ bit_size: 1
+ - name: LPUART1RST
+ description: LPUART1 reset Set and cleared by software.
+ bit_offset: 20
+ bit_size: 1
+ - name: I2C1RST
+ description: I2C1 reset Set and cleared by software.
+ bit_offset: 21
+ bit_size: 1
+ - name: I2C2RST
+ description: I2C2 reset Set and cleared by software.
+ bit_offset: 22
+ bit_size: 1
+ - name: I2C3RST
+ description: I2C3 reset Set and cleared by software.
+ bit_offset: 23
+ bit_size: 1
+ - name: OPAMPRST
+ description: OPAMP reset Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+ - name: I2C4RST
+ description: I2C4 reset(1) Set and cleared by software.
+ bit_offset: 25
+ bit_size: 1
+ - name: LPTIM3RST
+ description: LPTIM3 reset Set and cleared by software.
+ bit_offset: 26
+ bit_size: 1
+ - name: PWRRST
+ description: Power interface reset Set and cleared by software.
+ bit_offset: 28
+ bit_size: 1
+ - name: DAC1RST
+ description: DAC1 interface reset Set and cleared by software.
+ bit_offset: 29
+ bit_size: 1
+ - name: LPTIM2RST
+ description: Low Power Timer 2 reset Set and cleared by software.
+ bit_offset: 30
+ bit_size: 1
+ - name: LPTIM1RST
+ description: Low Power Timer 1 reset Set and cleared by software.
+ bit_offset: 31
+ bit_size: 1
+fieldset/APBRSTR2:
+ description: APB peripheral reset register 2.
+ fields:
+ - name: SYSCFGRST
+ description: SYSCFG, COMP and VREFBUF reset Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM1RST
+ description: TIM1 timer reset Set and cleared by software.
+ bit_offset: 11
+ bit_size: 1
+ - name: SPI1RST
+ description: SPI1 reset Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: USART1RST
+ description: USART1 reset Set and cleared by software.
+ bit_offset: 14
+ bit_size: 1
+ - name: TIM15RST
+ description: TIM15 timer reset Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: TIM16RST
+ description: TIM16 timer reset Set and cleared by software.
+ bit_offset: 17
+ bit_size: 1
+ - name: ADCRST
+ description: ADC reset Set and cleared by software.
+ bit_offset: 20
+ bit_size: 1
+fieldset/APBSMENR1:
+ description: APB peripheral clock enable in Sleep/Stop mode register 1.
+ fields:
+ - name: TIM2SMEN
+ description: TIM2 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM3SMEN
+ description: TIM3 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: TIM6SMEN
+ description: TIM6 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 4
+ bit_size: 1
+ - name: TIM7SMEN
+ description: TIM7 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 5
+ bit_size: 1
+ - name: LPUART2SMEN
+ description: LPUART2 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 7
+ bit_size: 1
+ - name: LCDSMEN
+ description: LCD clock enable during Sleep mode(1) Set and cleared by software.
+ bit_offset: 9
+ bit_size: 1
+ - name: RTCAPBSMEN
+ description: RTC APB clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 10
+ bit_size: 1
+ - name: WWDGSMEN
+ description: WWDG clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 11
+ bit_size: 1
+ - name: LPUART3SMEN
+ description: LPUART3 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: USBSMEN
+ description: USB clock enable during Sleep mode(1) Set and cleared by software.
+ bit_offset: 13
+ bit_size: 1
+ - name: SPI2SMEN
+ description: SPI2 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 14
+ bit_size: 1
+ - name: SPI3SMEN
+ description: SPI3 clock enable during Sleep mode(1) Set and cleared by software.
+ bit_offset: 15
+ bit_size: 1
+ - name: CRSSMEN
+ description: CRS clock enable during Sleep and Stop modes(1) Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: USART2SMEN
+ description: USART2 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 17
+ bit_size: 1
+ - name: USART3SMEN
+ description: USART3 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 18
+ bit_size: 1
+ - name: USART4SMEN
+ description: USART4 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 19
+ bit_size: 1
+ - name: LPUART1SMEN
+ description: LPUART1 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 20
+ bit_size: 1
+ - name: I2C1SMEN
+ description: I2C1 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 21
+ bit_size: 1
+ - name: I2C2SMEN
+ description: I2C2 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 22
+ bit_size: 1
+ - name: I2C3SMEN
+ description: I2C3 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 23
+ bit_size: 1
+ - name: OPAMPSMEN
+ description: OPAMP clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+ - name: I2C4SMEN
+ description: I2C4 clock enable during Sleep mode(1) Set and cleared by software.
+ bit_offset: 25
+ bit_size: 1
+ - name: LPTIM3SMEN
+ description: Low power timer 3 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 26
+ bit_size: 1
+ - name: PWRSMEN
+ description: Power interface clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 28
+ bit_size: 1
+ - name: DAC1SMEN
+ description: DAC1 interface clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 29
+ bit_size: 1
+ - name: LPTIM2SMEN
+ description: Low Power Timer 2 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 30
+ bit_size: 1
+ - name: LPTIM1SMEN
+ description: Low Power Timer 1 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 31
+ bit_size: 1
+fieldset/APBSMENR2:
+ description: APB peripheral clock enable in Sleep/Stop mode register 2.
+ fields:
+ - name: SYSCFGSMEN
+ description: SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM1SMEN
+ description: TIM1 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 11
+ bit_size: 1
+ - name: SPI1SMEN
+ description: SPI1 clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 12
+ bit_size: 1
+ - name: USART1SMEN
+ description: USART1 clock enable during Sleep and Stop modes Set and cleared by software.
+ bit_offset: 14
+ bit_size: 1
+ - name: TIM15SMEN
+ description: TIM15 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 16
+ bit_size: 1
+ - name: TIM16SMEN
+ description: TIM16 timer clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 17
+ bit_size: 1
+ - name: ADCSMEN
+ description: ADC clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 20
+ bit_size: 1
+fieldset/BDCR:
+ description: RTC domain control register.
+ fields:
+ - name: LSEON
+ description: LSE oscillator enable Set and cleared by software to enable LSE oscillator:.
+ bit_offset: 0
+ bit_size: 1
+ - name: LSERDY
+ description: 'LSE oscillator ready Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.'
+ bit_offset: 1
+ bit_size: 1
+ - name: LSEBYP
+ description: LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0).
+ bit_offset: 2
+ bit_size: 1
+ - name: LSEDRV
+ description: 'LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.'
+ bit_offset: 3
+ bit_size: 2
+ enum: LSEDRV
+ - name: LSECSSON
+ description: 'CSS on LSE enable Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit.'
+ bit_offset: 5
+ bit_size: 1
+ - name: LSECSSD
+ description: CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 321kHz oscillator (LSE):.
+ bit_offset: 6
+ bit_size: 1
+ - name: LSESYSEN
+ description: LSE clock enable for system usage This bit must be set by software to enable the LSE clock for a system usage.
+ bit_offset: 7
+ bit_size: 1
+ - name: RTCSEL
+ description: 'RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00.'
+ bit_offset: 8
+ bit_size: 2
+ enum: RTCSEL
+ - name: LSESYSRDY
+ description: LSE clock ready for system usage This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. Cleared by hardware to indicate that the LSE clock is not ready to be used by the system.
+ bit_offset: 11
+ bit_size: 1
+ - name: RTCEN
+ description: RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP.
+ bit_offset: 15
+ bit_size: 1
+ - name: BDRST
+ description: RTC domain software reset Set and cleared by software to reset the RTC domain:.
+ bit_offset: 16
+ bit_size: 1
+ - name: LSCOEN
+ description: Low-speed clock output (LSCO) enable Set and cleared by software.
+ bit_offset: 24
+ bit_size: 1
+ - name: LSCOSEL
+ description: Low-speed clock output selection Set and cleared by software to select the low-speed output clock:.
+ bit_offset: 25
+ bit_size: 1
+ enum: LSCOSEL
+fieldset/CCIPR:
+ description: Peripherals independent clock configuration register.
+ fields:
+ - name: USART1SEL
+ description: USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:.
+ bit_offset: 0
+ bit_size: 2
+ enum: USART1SEL
+ - name: USART2SEL
+ description: USART2 clock source selection This bitfield is controlled by software to select USART2 clock source as follows:.
+ bit_offset: 2
+ bit_size: 2
+ enum: USART2SEL
+ - name: LPUART3SEL
+ description: LPUART3 clock source selection(1) This bitfield is controlled by software to select LPUART3 clock source as follows:.
+ bit_offset: 6
+ bit_size: 2
+ enum: LPUART3SEL
+ - name: LPUART2SEL
+ description: LPUART2 clock source selection This bitfield is controlled by software to select LPUART2 clock source as follows:.
+ bit_offset: 8
+ bit_size: 2
+ enum: LPUART2SEL
+ - name: LPUART1SEL
+ description: LPUART1 clock source selection This bitfield is controlled by software to select LPUART1 clock source as follows:.
+ bit_offset: 10
+ bit_size: 2
+ enum: LPUART1SEL
+ - name: I2C1SEL
+ description: I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:.
+ bit_offset: 12
+ bit_size: 2
+ enum: I2C1SEL
+ - name: I2C3SEL
+ description: I2C3 clock source selection This bitfield is controlled by software to select I2C3 clock source as follows:.
+ bit_offset: 16
+ bit_size: 2
+ enum: I2C3SEL
+ - name: LPTIM1SEL
+ description: LPTIM1 clock source selection This bitfield is controlled by software to select LPTIM1 clock source as follows:.
+ bit_offset: 18
+ bit_size: 2
+ enum: LPTIM1SEL
+ - name: LPTIM2SEL
+ description: LPTIM2 clock source selection This bitfield is controlled by software to select LPTIM2 clock source as follows:.
+ bit_offset: 20
+ bit_size: 2
+ enum: LPTIM2SEL
+ - name: LPTIM3SEL
+ description: LPTIM3 clock source selection This bitfield is controlled by software to select LPTIM3 clock source as follows:.
+ bit_offset: 22
+ bit_size: 2
+ enum: LPTIM3SEL
+ - name: TIM1SEL
+ description: TIM1 clock source selection This bit is set and cleared by software. It selects TIM1 clock source as follows:.
+ bit_offset: 24
+ bit_size: 1
+ enum: TIM1SEL
+ - name: TIM15SEL
+ description: TIM15 clock source selection This bit is set and cleared by software. It selects TIM15 clock source as follows:.
+ bit_offset: 25
+ bit_size: 1
+ enum: TIM15SEL
+ - name: CLK48SEL
+ description: 481MHz clock source selection This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG:.
+ bit_offset: 26
+ bit_size: 2
+ enum: CLK48SEL
+ - name: ADCSEL
+ description: ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:.
+ bit_offset: 28
+ bit_size: 2
+ enum: ADCSEL
+fieldset/CFGR:
+ description: Clock configuration register.
+ fields:
+ - name: SW
+ description: 'System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.'
+ bit_offset: 0
+ bit_size: 3
+ enum: SW
+ - name: SWS
+ description: 'System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved.'
+ bit_offset: 3
+ bit_size: 3
+ enum: SW
+ - name: HPRE
+ description: 'AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.'
+ bit_offset: 8
+ bit_size: 4
+ enum: HPRE
+ - name: PPRE
+ description: 'APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1.'
+ bit_offset: 12
+ bit_size: 3
+ enum: PPRE
+ - name: STOPWUCK
+ description: 'Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10).'
+ bit_offset: 15
+ bit_size: 1
+ - name: MCO2SEL
+ description: 'Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.'
+ bit_offset: 16
+ bit_size: 4
+ enum: MCOSEL
+ - name: MCO2PRE
+ description: 'Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... Others: reserved It is highly recommended to set this field before the MCO2 output is enabled.'
+ bit_offset: 20
+ bit_size: 4
+ enum: MCOPRE
+ - name: MCOSEL
+ description: 'Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.'
+ bit_offset: 24
+ bit_size: 4
+ enum: MCOSEL
+ - name: MCOPRE
+ description: 'Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... Others: reserved It is highly recommended to set this field before the MCO output is enabled.'
+ bit_offset: 28
+ bit_size: 4
+ enum: MCOPRE
+fieldset/CICR:
+ description: Clock interrupt clear register.
+ fields:
+ - name: LSIRDYC
+ description: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag.
+ bit_offset: 0
+ bit_size: 1
+ - name: LSERDYC
+ description: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag.
+ bit_offset: 1
+ bit_size: 1
+ - name: MSIRDYC
+ description: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag.
+ bit_offset: 2
+ bit_size: 1
+ - name: HSIRDYC
+ description: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag.
+ bit_offset: 3
+ bit_size: 1
+ - name: HSERDYC
+ description: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag.
+ bit_offset: 4
+ bit_size: 1
+ - name: PLLRDYC
+ description: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag.
+ bit_offset: 5
+ bit_size: 1
+ - name: CSSC
+ description: Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag.
+ bit_offset: 8
+ bit_size: 1
+ - name: LSECSSC
+ description: LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag.
+ bit_offset: 9
+ bit_size: 1
+ - name: HSI48RDYC
+ description: HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag.
+ bit_offset: 10
+ bit_size: 1
+fieldset/CIER:
+ description: Clock interrupt enable register.
+ fields:
+ - name: LSIRDYIE
+ description: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:.
+ bit_offset: 0
+ bit_size: 1
+ - name: LSERDYIE
+ description: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:.
+ bit_offset: 1
+ bit_size: 1
+ - name: MSIRDYIE
+ description: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization.
+ bit_offset: 2
+ bit_size: 1
+ - name: HSIRDYIE
+ description: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:.
+ bit_offset: 3
+ bit_size: 1
+ - name: HSERDYIE
+ description: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:.
+ bit_offset: 4
+ bit_size: 1
+ - name: PLLRDYIE
+ description: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock:.
+ bit_offset: 5
+ bit_size: 1
+ - name: LSECSSIE
+ description: LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE.
+ bit_offset: 9
+ bit_size: 1
+ - name: HSI48RDYIE
+ description: HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator.
+ bit_offset: 10
+ bit_size: 1
+fieldset/CIFR:
+ description: Clock interrupt flag register.
+ fields:
+ - name: LSIRDYF
+ description: LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit.
+ bit_offset: 0
+ bit_size: 1
+ - name: LSERDYF
+ description: LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit.
+ bit_offset: 1
+ bit_size: 1
+ - name: MSIRDYF
+ description: MSI ready interrupt flag Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. Cleared by software setting the MSIRDYC bit.
+ bit_offset: 2
+ bit_size: 1
+ - name: HSIRDYF
+ description: HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit.
+ bit_offset: 3
+ bit_size: 1
+ - name: HSERDYF
+ description: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit.
+ bit_offset: 4
+ bit_size: 1
+ - name: PLLRDYF
+ description: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYIE is set. Cleared by software setting the PLLRDYC bit.
+ bit_offset: 5
+ bit_size: 1
+ - name: CSSF
+ description: HSE clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit.
+ bit_offset: 8
+ bit_size: 1
+ - name: LSECSSF
+ description: LSE clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit.
+ bit_offset: 9
+ bit_size: 1
+ - name: HSI48RDYF
+ description: HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit.
+ bit_offset: 10
+ bit_size: 1
+fieldset/CR:
+ description: Clock control register.
+ fields:
+ - name: MSION
+ description: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock.
+ bit_offset: 0
+ bit_size: 1
+ - name: MSIRDY
+ description: 'MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.'
+ bit_offset: 1
+ bit_size: 1
+ - name: MSIPLLEN
+ description: MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register).
+ bit_offset: 2
+ bit_size: 1
+ - name: MSIRGSEL
+ description: MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register.
+ bit_offset: 3
+ bit_size: 1
+ enum: MSIRGSEL
+ - name: MSIRANGE
+ description: 'MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0).'
+ bit_offset: 4
+ bit_size: 4
+ enum: MSIRANGE
+ - name: HSION
+ description: HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby, or Shutdown mode. Forced by hardware to keep the HSI oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock).
+ bit_offset: 8
+ bit_size: 1
+ - name: HSIKERON
+ description: HSI always enable for peripheral kernels. Set and cleared by software to force HSI ON even in Stop modes. The HSI can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI as kernel clock. Keeping the HSI ON in Stop mode allows avoiding to slow down the communication speed because of the HSI startup time. This bit has no effect on HSION value.
+ bit_offset: 9
+ bit_size: 1
+ - name: HSIRDY
+ description: 'HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI clock cycles.'
+ bit_offset: 10
+ bit_size: 1
+ - name: HSIASFS
+ description: HSI automatic start from Stop Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI is parallel of the system wake-up.
+ bit_offset: 11
+ bit_size: 1
+ - name: HSEON
+ description: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
+ bit_offset: 16
+ bit_size: 1
+ - name: HSERDY
+ description: 'HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.'
+ bit_offset: 17
+ bit_size: 1
+ - name: HSEBYP
+ description: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
+ bit_offset: 18
+ bit_size: 1
+ - name: CSSON
+ description: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.
+ bit_offset: 19
+ bit_size: 1
+ - name: PLLON
+ description: PLL enable Set and cleared by software to enable the PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock.
+ bit_offset: 24
+ bit_size: 1
+ - name: PLLRDY
+ description: PLL clock ready flag Set by hardware to indicate that the PLL is locked.
+ bit_offset: 25
+ bit_size: 1
+fieldset/CRRCR:
+ description: RCC clock recovery RC register.
+ fields:
+ - name: HSI48ON
+ description: HSI48 RC oscillator enable(1).
+ bit_offset: 0
+ bit_size: 1
+ - name: HSI48RDY
+ description: HSI48 clock ready flag(1) The flag is set when the HSI48 clock is ready for use.
+ bit_offset: 1
+ bit_size: 1
+ - name: HSI48CAL
+ description: HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
+ bit_offset: 7
+ bit_size: 9
+fieldset/CSR:
+ description: Control/status register.
+ fields:
+ - name: LSION
+ description: LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:.
+ bit_offset: 0
+ bit_size: 1
+ - name: LSIRDY
+ description: 'LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.'
+ bit_offset: 1
+ bit_size: 1
+ - name: LSIPREDIV
+ description: Internal low-speed oscillator pre-divided by 128 Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit.
+ bit_offset: 2
+ bit_size: 1
+ enum: LSIPREDIV
+ - name: MSISRANGE
+ description: 'MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. Others: Reserved Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency.'
+ bit_offset: 8
+ bit_size: 4
+ enum: MSISRANGE
+ - name: RMVF
+ description: Remove reset flags Set by software to clear the reset flags.
+ bit_offset: 23
+ bit_size: 1
+ - name: OBLRSTF
+ description: Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit.
+ bit_offset: 25
+ bit_size: 1
+ - name: PINRSTF
+ description: Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit.
+ bit_offset: 26
+ bit_size: 1
+ - name: PWRRSTF
+ description: BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit.
+ bit_offset: 27
+ bit_size: 1
+ - name: SFTRSTF
+ description: Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit.
+ bit_offset: 28
+ bit_size: 1
+ - name: IWDGRSTF
+ description: Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit.
+ bit_offset: 29
+ bit_size: 1
+ - name: WWDGRSTF
+ description: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit.
+ bit_offset: 30
+ bit_size: 1
+ - name: LPWRRSTF
+ description: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared.
+ bit_offset: 31
+ bit_size: 1
+fieldset/DBGCFGR:
+ description: Debug configuration register.
+ fields:
+ - name: DBGEN
+ description: Debug support clock enable Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: DBGRST
+ description: Debug support reset Set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+fieldset/ICSCR:
+ description: Internal clock sources calibration register.
+ fields:
+ - name: MSICAL
+ description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
+ bit_offset: 0
+ bit_size: 8
+ - name: MSITRIM
+ description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.
+ bit_offset: 8
+ bit_size: 8
+ - name: HSICAL
+ description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
+ bit_offset: 16
+ bit_size: 8
+ - name: HSITRIM
+ description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%.
+ bit_offset: 24
+ bit_size: 7
+fieldset/GPIOENR:
+ description: I/O port clock enable register.
+ fields:
+ - name: GPIOAEN
+ description: I/O port A clock enable This bit is set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: GPIOBEN
+ description: I/O port B clock enable This bit is set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: GPIOCEN
+ description: I/O port C clock enable This bit is set and cleared by software.
+ bit_offset: 2
+ bit_size: 1
+ - name: GPIODEN
+ description: I/O port D clock enable This bit is set and cleared by software.
+ bit_offset: 3
+ bit_size: 1
+ - name: GPIOEEN
+ description: I/O port E clock enable(1) This bit is set and cleared by software.
+ bit_offset: 4
+ bit_size: 1
+ - name: GPIOFEN
+ description: I/O port F clock enable This bit is set and cleared by software.
+ bit_offset: 5
+ bit_size: 1
+fieldset/GPIORSTR:
+ description: I/O port reset register.
+ fields:
+ - name: GPIOARST
+ description: I/O port A reset This bit is set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: GPIOBRST
+ description: I/O port B reset This bit is set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: GPIOCRST
+ description: I/O port C reset This bit is set and cleared by software.
+ bit_offset: 2
+ bit_size: 1
+ - name: GPIODRST
+ description: I/O port D reset This bit is set and cleared by software.
+ bit_offset: 3
+ bit_size: 1
+ - name: GPIOERST
+ description: I/O port E reset This bit is set and cleared by software.
+ bit_offset: 4
+ bit_size: 1
+ - name: GPIOFRST
+ description: I/O port F reset This bit is set and cleared by software.
+ bit_offset: 5
+ bit_size: 1
+fieldset/GPIOSMENR:
+ description: I/O port in Sleep mode clock enable register.
+ fields:
+ - name: GPIOASMEN
+ description: I/O port A clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 0
+ bit_size: 1
+ - name: GPIOBSMEN
+ description: I/O port B clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 1
+ bit_size: 1
+ - name: GPIOCSMEN
+ description: I/O port C clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 2
+ bit_size: 1
+ - name: GPIODSMEN
+ description: I/O port D clock enable during Sleep mode(1) Set and cleared by software.
+ bit_offset: 3
+ bit_size: 1
+ - name: GPIOESMEN
+ description: I/O port E clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 4
+ bit_size: 1
+ - name: GPIOFSMEN
+ description: I/O port F clock enable during Sleep mode Set and cleared by software.
+ bit_offset: 5
+ bit_size: 1
+fieldset/PLLCFGR:
+ description: PLL configuration register.
+ fields:
+ - name: PLLSRC
+ description: 'PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power.'
+ bit_offset: 0
+ bit_size: 2
+ enum: PLLSRC
+ - name: PLLM
+ description: 'Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz.'
+ bit_offset: 4
+ bit_size: 3
+ enum: PLLM
+ - name: PLLN
+ description: 'PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: ... ... The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz.'
+ bit_offset: 8
+ bit_size: 7
+ enum: PLLN
+ - name: PLLPEN
+ description: 'PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power.'
+ bit_offset: 16
+ bit_size: 1
+ - name: PLLP
+ description: 'PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: ... The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.'
+ bit_offset: 17
+ bit_size: 5
+ enum: PLLP
+ - name: PLLQEN
+ description: 'PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power.'
+ bit_offset: 24
+ bit_size: 1
+ - name: PLLQ
+ description: 'PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.'
+ bit_offset: 25
+ bit_size: 3
+ enum: PLLQ
+ - name: PLLREN
+ description: 'PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power.'
+ bit_offset: 28
+ bit_size: 1
+ - name: PLLR
+ description: 'PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock.'
+ bit_offset: 29
+ bit_size: 3
+ enum: PLLR
+enum/ADCSEL:
+ bit_size: 2
+ variants:
+ - name: SYS
+ value: 0
+ - name: PLL1_P
+ value: 1
+ - name: HSI
+ value: 2
+enum/CLK48SEL:
+ bit_size: 2
+ variants:
+ - name: DISABLE
+ value: 0
+ - name: MSI
+ value: 1
+ - name: PLL1_Q
+ value: 2
+ - name: HSI48
+ value: 3
+enum/HPRE:
+ bit_size: 4
+ variants:
+ - name: Div1
+ value: 0
+ - name: Div2
+ value: 8
+ - name: Div4
+ value: 9
+ - name: Div8
+ value: 10
+ - name: Div16
+ value: 11
+ - name: Div64
+ value: 12
+ - name: Div128
+ value: 13
+ - name: Div256
+ value: 14
+ - name: Div512
+ value: 15
+enum/I2C1SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+enum/I2C3SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+enum/LPTIM1SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: LSI
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/LPTIM2SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: LSI
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/LPTIM3SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: LSI
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/LPUART1SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/LPUART2SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/LPUART3SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/LSCOSEL:
+ bit_size: 1
+ variants:
+ - name: LSI
+ value: 0
+ - name: LSE
+ value: 1
+enum/LSEDRV:
+ bit_size: 2
+ variants:
+ - name: Low
+ description: Low driving capability
+ value: 0
+ - name: MediumLow
+ description: Medium low driving capability
+ value: 1
+ - name: MediumHigh
+ description: Medium high driving capability
+ value: 2
+ - name: High
+ description: High driving capability
+ value: 3
+enum/LSIPREDIV:
+ bit_size: 1
+ variants:
+ - name: Div1
+ value: 0
+ - name: Div128
+ value: 1
+enum/MCOPRE:
+ bit_size: 4
+ variants:
+ - name: Div1
+ value: 0
+ - name: Div2
+ value: 1
+ - name: Div4
+ value: 2
+ - name: Div8
+ value: 3
+ - name: Div16
+ value: 4
+ - name: Div32
+ value: 5
+ - name: Div64
+ value: 6
+ - name: Div128
+ value: 7
+ - name: Div256
+ value: 8
+ - name: Div512
+ value: 9
+ - name: Div1024
+ value: 10
+enum/MCOSEL:
+ bit_size: 4
+ variants:
+ - name: DISABLE
+ value: 0
+ - name: SYS
+ value: 1
+ - name: MSI
+ value: 2
+ - name: HSI
+ value: 3
+ - name: HSE
+ value: 4
+ - name: PLL1_R
+ value: 5
+ - name: LSI
+ value: 6
+ - name: LSE
+ value: 7
+ - name: HSI48
+ value: 8
+ - name: RTC
+ value: 9
+ - name: RTC_WKUP
+ value: 10
+enum/MSIRANGE:
+ bit_size: 4
+ variants:
+ - name: Range100K
+ description: range 0 around 100 kHz
+ value: 0
+ - name: Range200K
+ description: range 1 around 200 kHz
+ value: 1
+ - name: Range400K
+ description: range 2 around 400 kHz
+ value: 2
+ - name: Range800K
+ description: range 3 around 800 kHz
+ value: 3
+ - name: Range1M
+ description: range 4 around 1 MHz
+ value: 4
+ - name: Range2M
+ description: range 5 around 2 MHz
+ value: 5
+ - name: Range4M
+ description: range 6 around 4 MHz
+ value: 6
+ - name: Range8M
+ description: range 7 around 8 MHz
+ value: 7
+ - name: Range16M
+ description: range 8 around 16 MHz
+ value: 8
+ - name: Range24M
+ description: range 9 around 24 MHz
+ value: 9
+ - name: Range32M
+ description: range 10 around 32 MHz
+ value: 10
+ - name: Range48M
+ description: range 11 around 48 MHz
+ value: 11
+enum/MSIRGSEL:
+ bit_size: 1
+ variants:
+ - name: CSR
+ description: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register
+ value: 0
+ - name: CR
+ description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register
+ value: 1
+enum/MSISRANGE:
+ bit_size: 4
+ variants:
+ - name: RANGE_81MHz
+ value: 4
+enum/PLLM:
+ bit_size: 3
+ variants:
+ - name: Div1
+ value: 0
+ - name: Div2
+ value: 1
+ - name: Div3
+ value: 2
+ - name: Div4
+ value: 3
+ - name: Div5
+ value: 4
+ - name: Div6
+ value: 5
+ - name: Div7
+ value: 6
+ - name: Div8
+ value: 7
+enum/PLLN:
+ bit_size: 7
+ variants:
+ - name: Mul4
+ value: 4
+ - name: Mul5
+ value: 5
+ - name: Mul6
+ value: 6
+ - name: Mul7
+ value: 7
+ - name: Mul8
+ value: 8
+ - name: Mul9
+ value: 9
+ - name: Mul10
+ value: 10
+ - name: Mul11
+ value: 11
+ - name: Mul12
+ value: 12
+ - name: Mul13
+ value: 13
+ - name: Mul14
+ value: 14
+ - name: Mul15
+ value: 15
+ - name: Mul16
+ value: 16
+ - name: Mul17
+ value: 17
+ - name: Mul18
+ value: 18
+ - name: Mul19
+ value: 19
+ - name: Mul20
+ value: 20
+ - name: Mul21
+ value: 21
+ - name: Mul22
+ value: 22
+ - name: Mul23
+ value: 23
+ - name: Mul24
+ value: 24
+ - name: Mul25
+ value: 25
+ - name: Mul26
+ value: 26
+ - name: Mul27
+ value: 27
+ - name: Mul28
+ value: 28
+ - name: Mul29
+ value: 29
+ - name: Mul30
+ value: 30
+ - name: Mul31
+ value: 31
+ - name: Mul32
+ value: 32
+ - name: Mul33
+ value: 33
+ - name: Mul34
+ value: 34
+ - name: Mul35
+ value: 35
+ - name: Mul36
+ value: 36
+ - name: Mul37
+ value: 37
+ - name: Mul38
+ value: 38
+ - name: Mul39
+ value: 39
+ - name: Mul40
+ value: 40
+ - name: Mul41
+ value: 41
+ - name: Mul42
+ value: 42
+ - name: Mul43
+ value: 43
+ - name: Mul44
+ value: 44
+ - name: Mul45
+ value: 45
+ - name: Mul46
+ value: 46
+ - name: Mul47
+ value: 47
+ - name: Mul48
+ value: 48
+ - name: Mul49
+ value: 49
+ - name: Mul50
+ value: 50
+ - name: Mul51
+ value: 51
+ - name: Mul52
+ value: 52
+ - name: Mul53
+ value: 53
+ - name: Mul54
+ value: 54
+ - name: Mul55
+ value: 55
+ - name: Mul56
+ value: 56
+ - name: Mul57
+ value: 57
+ - name: Mul58
+ value: 58
+ - name: Mul59
+ value: 59
+ - name: Mul60
+ value: 60
+ - name: Mul61
+ value: 61
+ - name: Mul62
+ value: 62
+ - name: Mul63
+ value: 63
+ - name: Mul64
+ value: 64
+ - name: Mul65
+ value: 65
+ - name: Mul66
+ value: 66
+ - name: Mul67
+ value: 67
+ - name: Mul68
+ value: 68
+ - name: Mul69
+ value: 69
+ - name: Mul70
+ value: 70
+ - name: Mul71
+ value: 71
+ - name: Mul72
+ value: 72
+ - name: Mul73
+ value: 73
+ - name: Mul74
+ value: 74
+ - name: Mul75
+ value: 75
+ - name: Mul76
+ value: 76
+ - name: Mul77
+ value: 77
+ - name: Mul78
+ value: 78
+ - name: Mul79
+ value: 79
+ - name: Mul80
+ value: 80
+ - name: Mul81
+ value: 81
+ - name: Mul82
+ value: 82
+ - name: Mul83
+ value: 83
+ - name: Mul84
+ value: 84
+ - name: Mul85
+ value: 85
+ - name: Mul86
+ value: 86
+ - name: Mul87
+ value: 87
+ - name: Mul88
+ value: 88
+ - name: Mul89
+ value: 89
+ - name: Mul90
+ value: 90
+ - name: Mul91
+ value: 91
+ - name: Mul92
+ value: 92
+ - name: Mul93
+ value: 93
+ - name: Mul94
+ value: 94
+ - name: Mul95
+ value: 95
+ - name: Mul96
+ value: 96
+ - name: Mul97
+ value: 97
+ - name: Mul98
+ value: 98
+ - name: Mul99
+ value: 99
+ - name: Mul100
+ value: 100
+ - name: Mul101
+ value: 101
+ - name: Mul102
+ value: 102
+ - name: Mul103
+ value: 103
+ - name: Mul104
+ value: 104
+ - name: Mul105
+ value: 105
+ - name: Mul106
+ value: 106
+ - name: Mul107
+ value: 107
+ - name: Mul108
+ value: 108
+ - name: Mul109
+ value: 109
+ - name: Mul110
+ value: 110
+ - name: Mul111
+ value: 111
+ - name: Mul112
+ value: 112
+ - name: Mul113
+ value: 113
+ - name: Mul114
+ value: 114
+ - name: Mul115
+ value: 115
+ - name: Mul116
+ value: 116
+ - name: Mul117
+ value: 117
+ - name: Mul118
+ value: 118
+ - name: Mul119
+ value: 119
+ - name: Mul120
+ value: 120
+ - name: Mul121
+ value: 121
+ - name: Mul122
+ value: 122
+ - name: Mul123
+ value: 123
+ - name: Mul124
+ value: 124
+ - name: Mul125
+ value: 125
+ - name: Mul126
+ value: 126
+ - name: Mul127
+ value: 127
+enum/PLLP:
+ bit_size: 5
+ variants:
+ - name: Div2
+ value: 1
+ - name: Div3
+ value: 2
+ - name: Div4
+ value: 3
+ - name: Div5
+ value: 4
+ - name: Div6
+ value: 5
+ - name: Div7
+ value: 6
+ - name: Div8
+ value: 7
+ - name: Div9
+ value: 8
+ - name: Div10
+ value: 9
+ - name: Div11
+ value: 10
+ - name: Div12
+ value: 11
+ - name: Div13
+ value: 12
+ - name: Div14
+ value: 13
+ - name: Div15
+ value: 14
+ - name: Div16
+ value: 15
+ - name: Div17
+ value: 16
+ - name: Div18
+ value: 17
+ - name: Div19
+ value: 18
+ - name: Div20
+ value: 19
+ - name: Div21
+ value: 20
+ - name: Div22
+ value: 21
+ - name: Div23
+ value: 22
+ - name: Div24
+ value: 23
+ - name: Div25
+ value: 24
+ - name: Div26
+ value: 25
+ - name: Div27
+ value: 26
+ - name: Div28
+ value: 27
+ - name: Div29
+ value: 28
+ - name: Div30
+ value: 29
+ - name: Div31
+ value: 30
+ - name: Div32
+ value: 31
+enum/PLLQ:
+ bit_size: 3
+ variants:
+ - name: Div2
+ value: 1
+ - name: Div3
+ value: 2
+ - name: Div4
+ value: 3
+ - name: Div5
+ value: 4
+ - name: Div6
+ value: 5
+ - name: Div7
+ value: 6
+ - name: Div8
+ value: 7
+enum/PLLR:
+ bit_size: 3
+ variants:
+ - name: Div2
+ value: 1
+ - name: Div3
+ value: 2
+ - name: Div4
+ value: 3
+ - name: Div5
+ value: 4
+ - name: Div6
+ value: 5
+ - name: Div7
+ value: 6
+ - name: Div8
+ value: 7
+enum/PLLSRC:
+ bit_size: 2
+ variants:
+ - name: DISABLE
+ value: 0
+ - name: MSI
+ value: 1
+ - name: HSI
+ value: 2
+ - name: HSE
+ value: 3
+enum/PPRE:
+ bit_size: 3
+ variants:
+ - name: Div1
+ description: HCLK not divided
+ value: 0
+ - name: Div2
+ description: HCLK divided by 2
+ value: 4
+ - name: Div4
+ description: HCLK divided by 4
+ value: 5
+ - name: Div8
+ description: HCLK divided by 8
+ value: 6
+ - name: Div16
+ description: HCLK divided by 16
+ value: 7
+enum/RTCSEL:
+ bit_size: 2
+ variants:
+ - name: DISABLE
+ value: 0
+ - name: LSE
+ value: 1
+ - name: LSI
+ value: 2
+ - name: HSE
+ value: 3
+enum/SW:
+ bit_size: 3
+ variants:
+ - name: MSI
+ value: 0
+ - name: HSI
+ value: 1
+ - name: HSE
+ value: 2
+ - name: PLL1_R
+ value: 3
+ - name: LSI
+ value: 4
+ - name: LSE
+ value: 5
+enum/TIM15SEL:
+ bit_size: 1
+ variants:
+ - name: PCLK1_TIM
+ value: 0
+ - name: PLL1_Q
+ value: 1
+enum/TIM1SEL:
+ bit_size: 1
+ variants:
+ - name: PCLK1_TIM
+ value: 0
+ - name: PLL1_Q
+ value: 1
+enum/USART1SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
+enum/USART2SEL:
+ bit_size: 2
+ variants:
+ - name: PCLK1
+ value: 0
+ - name: SYS
+ value: 1
+ - name: HSI
+ value: 2
+ - name: LSE
+ value: 3
diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml
index 6ccf388..4a63940 100644
--- a/data/registers/spi_v2.yaml
+++ b/data/registers/spi_v2.yaml
@@ -13,10 +13,14 @@ block/SPI:
description: status register
byte_offset: 8
fieldset: SR
- - name: DR
- description: data register
+ - name: DR16
+ description: data register - half-word sized
byte_offset: 12
- fieldset: DR
+ bit_size: 16
+ - name: DR8
+ description: data register - byte sized
+ byte_offset: 12
+ bit_size: 8
- name: CRCPR
description: CRC polynomial register
byte_offset: 16
@@ -171,13 +175,6 @@ fieldset/CRCPR:
description: CRC polynomial register
bit_offset: 0
bit_size: 16
-fieldset/DR:
- description: data register
- fields:
- - name: DR
- description: Data register
- bit_offset: 0
- bit_size: 16
fieldset/I2SCFGR:
description: I2S configuration register
fields:
diff --git a/data/registers/spi_v3.yaml b/data/registers/spi_v3.yaml
index 6947ed4..4afed99 100644
--- a/data/registers/spi_v3.yaml
+++ b/data/registers/spi_v3.yaml
@@ -31,16 +31,34 @@ block/SPI:
byte_offset: 24
access: Write
fieldset: IFCR
- - name: TXDR
+ - name: TXDR32
description: Transmit Data Register
byte_offset: 32
access: Write
- fieldset: TXDR
- - name: RXDR
+ - name: TXDR16
+ description: Transmit Data Register - half-word sized
+ byte_offset: 32
+ bit_size: 16
+ access: Write
+ - name: TXDR8
+ description: Transmit Data Register - byte sized
+ byte_offset: 32
+ bit_size: 8
+ access: Write
+ - name: RXDR32
description: Receive Data Register
byte_offset: 48
access: Read
- fieldset: RXDR
+ - name: RXDR16
+ description: Receive Data Register - half-word sized
+ byte_offset: 48
+ bit_size: 16
+ access: Read
+ - name: RXDR8
+ description: Receive Data Register - byte sized
+ byte_offset: 48
+ bit_size: 8
+ access: Read
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
@@ -324,13 +342,6 @@ fieldset/RXCRC:
description: CRC register for receiver
bit_offset: 0
bit_size: 32
-fieldset/RXDR:
- description: Receive Data Register
- fields:
- - name: RXDR
- description: Receive data register
- bit_offset: 0
- bit_size: 32
fieldset/SR:
description: Status Register
fields:
@@ -407,13 +418,6 @@ fieldset/TXCRC:
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
-fieldset/TXDR:
- description: Transmit Data Register
- fields:
- - name: TXDR
- description: Transmit data register
- bit_offset: 0
- bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields:
diff --git a/data/registers/spi_v4.yaml b/data/registers/spi_v4.yaml
index a2c2566..78a74eb 100644
--- a/data/registers/spi_v4.yaml
+++ b/data/registers/spi_v4.yaml
@@ -31,16 +31,34 @@ block/SPI:
byte_offset: 24
access: Write
fieldset: IFCR
- - name: TXDR
+ - name: TXDR32
description: Transmit Data Register
byte_offset: 32
access: Write
- fieldset: TXDR
- - name: RXDR
+ - name: TXDR16
+ description: Transmit Data Register - half-word sized
+ byte_offset: 32
+ bit_size: 16
+ access: Write
+ - name: TXDR8
+ description: Transmit Data Register - byte sized
+ byte_offset: 32
+ bit_size: 8
+ access: Write
+ - name: RXDR32
description: Receive Data Register
byte_offset: 48
access: Read
- fieldset: RXDR
+ - name: RXDR16
+ description: Receive Data Register - half-word sized
+ byte_offset: 48
+ bit_size: 16
+ access: Read
+ - name: RXDR8
+ description: Receive Data Register - byte sized
+ byte_offset: 48
+ bit_size: 8
+ access: Read
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
@@ -323,13 +341,6 @@ fieldset/RXCRC:
description: CRC register for receiver
bit_offset: 0
bit_size: 32
-fieldset/RXDR:
- description: Receive Data Register
- fields:
- - name: RXDR
- description: Receive data register
- bit_offset: 0
- bit_size: 32
fieldset/SR:
description: Status Register
fields:
@@ -402,13 +413,6 @@ fieldset/TXCRC:
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
-fieldset/TXDR:
- description: Transmit Data Register
- fields:
- - name: TXDR
- description: Transmit data register
- bit_offset: 0
- bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields:
diff --git a/data/registers/spi_v5.yaml b/data/registers/spi_v5.yaml
index fce0632..8155eca 100644
--- a/data/registers/spi_v5.yaml
+++ b/data/registers/spi_v5.yaml
@@ -34,16 +34,34 @@ block/SPI:
- name: AUTOCR
byte_offset: 28
fieldset: AUTOCR
- - name: TXDR
+ - name: TXDR32
description: Transmit Data Register
byte_offset: 32
access: Write
- fieldset: TXDR
- - name: RXDR
+ - name: TXDR16
+ description: Transmit Data Register - half-word sized
+ byte_offset: 32
+ bit_size: 16
+ access: Write
+ - name: TXDR8
+ description: Transmit Data Register - byte sized
+ byte_offset: 32
+ bit_size: 8
+ access: Write
+ - name: RXDR32
description: Receive Data Register
byte_offset: 48
access: Read
- fieldset: RXDR
+ - name: RXDR16
+ description: Receive Data Register - half-word sized
+ byte_offset: 48
+ bit_size: 16
+ access: Read
+ - name: RXDR8
+ description: Receive Data Register - byte sized
+ byte_offset: 48
+ bit_size: 8
+ access: Read
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
@@ -348,13 +366,6 @@ fieldset/RXCRC:
description: CRC register for receiver
bit_offset: 0
bit_size: 32
-fieldset/RXDR:
- description: Receive Data Register
- fields:
- - name: RXDR
- description: Receive data register
- bit_offset: 0
- bit_size: 32
fieldset/SR:
description: Status Register
fields:
@@ -427,13 +438,6 @@ fieldset/TXCRC:
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
-fieldset/TXDR:
- description: Transmit Data Register
- fields:
- - name: TXDR
- description: Transmit data register
- bit_offset: 0
- bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields:
diff --git a/data/registers/syscfg_u0.yaml b/data/registers/syscfg_u0.yaml
new file mode 100644
index 0000000..1688672
--- /dev/null
+++ b/data/registers/syscfg_u0.yaml
@@ -0,0 +1,752 @@
+block/SYSCFG:
+ description: SYSCFG register block
+ items:
+ - name: CFGR1
+ description: SYSCFG configuration register 1
+ byte_offset: 0
+ fieldset: CFGR1
+ - name: CFGR2
+ description: SYSCFG configuration register 2
+ byte_offset: 24
+ fieldset: CFGR2
+ - name: SCSR
+ description: SYSCFG SRAM2 control and status register
+ byte_offset: 28
+ fieldset: SCSR
+ - name: SKR
+ description: SYSCFG SRAM2 key register
+ byte_offset: 32
+ fieldset: SKR
+ - name: TSCCR
+ description: SYSCFG TSC comparator register
+ byte_offset: 36
+ fieldset: TSCCR
+ - name: ITLINE0
+ description: SYSCFG interrupt line 0 status register
+ byte_offset: 128
+ fieldset: ITLINE0
+ - name: ITLINE1
+ description: SYSCFG interrupt line 1 status register
+ byte_offset: 132
+ fieldset: ITLINE1
+ - name: ITLINE2
+ description: SYSCFG interrupt line 2 status register
+ byte_offset: 136
+ fieldset: ITLINE2
+ - name: ITLINE3
+ description: SYSCFG interrupt line 3 status register
+ byte_offset: 140
+ fieldset: ITLINE3
+ - name: ITLINE4
+ description: SYSCFG interrupt line 4 status register
+ byte_offset: 144
+ fieldset: ITLINE4
+ - name: ITLINE5
+ description: SYSCFG interrupt line 5 status register
+ byte_offset: 148
+ fieldset: ITLINE5
+ - name: ITLINE6
+ description: SYSCFG interrupt line 6 status register
+ byte_offset: 152
+ fieldset: ITLINE6
+ - name: ITLINE7
+ description: SYSCFG interrupt line 7 status register
+ byte_offset: 156
+ fieldset: ITLINE7
+ - name: ITLINE8
+ description: SYSCFG interrupt line 8 status register
+ byte_offset: 160
+ fieldset: ITLINE8
+ - name: ITLINE9
+ description: SYSCFG interrupt line 9 status register
+ byte_offset: 164
+ fieldset: ITLINE9
+ - name: ITLINE10
+ description: SYSCFG interrupt line 10 status register
+ byte_offset: 168
+ fieldset: ITLINE10
+ - name: ITLINE11
+ description: SYSCFG interrupt line 11 status register
+ byte_offset: 172
+ fieldset: ITLINE11
+ - name: ITLINE12
+ description: SYSCFG interrupt line 12 status register
+ byte_offset: 176
+ fieldset: ITLINE12
+ - name: ITLINE13
+ description: SYSCFG interrupt line 13 status register
+ byte_offset: 180
+ fieldset: ITLINE13
+ - name: ITLINE14
+ description: SYSCFG interrupt line 14 status register
+ byte_offset: 184
+ fieldset: ITLINE14
+ - name: ITLINE15
+ description: SYSCFG interrupt line 15 status register
+ byte_offset: 188
+ fieldset: ITLINE15
+ - name: ITLINE16
+ description: SYSCFG interrupt line 16 status register
+ byte_offset: 192
+ fieldset: ITLINE16
+ - name: ITLINE17
+ description: SYSCFG interrupt line 17 status register
+ byte_offset: 196
+ fieldset: ITLINE17
+ - name: ITLINE18
+ description: SYSCFG interrupt line 18 status register
+ byte_offset: 200
+ fieldset: ITLINE18
+ - name: ITLINE19
+ description: SYSCFG interrupt line 19 status register
+ byte_offset: 204
+ fieldset: ITLINE19
+ - name: ITLINE20
+ description: SYSCFG interrupt line 20 status register
+ byte_offset: 208
+ fieldset: ITLINE20
+ - name: ITLINE21
+ description: SYSCFG interrupt line 21 status register
+ byte_offset: 212
+ fieldset: ITLINE21
+ - name: ITLINE22
+ description: SYSCFG interrupt line 22 status register
+ byte_offset: 216
+ fieldset: ITLINE22
+ - name: ITLINE23
+ description: SYSCFG interrupt line 23 status register
+ byte_offset: 220
+ fieldset: ITLINE23
+ - name: ITLINE24
+ description: SYSCFG interrupt line 24 status register
+ byte_offset: 224
+ fieldset: ITLINE24
+ - name: ITLINE25
+ description: SYSCFG interrupt line 25 status register
+ byte_offset: 228
+ fieldset: ITLINE25
+ - name: ITLINE26
+ description: SYSCFG interrupt line 26 status register
+ byte_offset: 232
+ fieldset: ITLINE26
+ - name: ITLINE27
+ description: SYSCFG interrupt line 27 status register
+ byte_offset: 236
+ fieldset: ITLINE27
+ - name: ITLINE28
+ description: SYSCFG interrupt line 28 status register
+ byte_offset: 240
+ fieldset: ITLINE28
+ - name: ITLINE29
+ description: SYSCFG interrupt line 29 status register
+ byte_offset: 244
+ fieldset: ITLINE29
+ - name: ITLINE30
+ description: SYSCFG interrupt line 30 status register
+ byte_offset: 248
+ fieldset: ITLINE30
+ - name: ITLINE31
+ description: SYSCFG interrupt line 31 status register
+ byte_offset: 252
+ fieldset: ITLINE31
+fieldset/CFGR1:
+ description: SYSCFG configuration register 1
+ fields:
+ - name: MEM_MODE
+ description: 'Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000'
+ bit_offset: 0
+ bit_size: 2
+ enum: MEM_MODE
+ - name: PA11_RMP
+ description: |-
+ PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port.
+ 0: No remap (PA11)
+ 1: Remap (PA9)
+ bit_offset: 3
+ bit_size: 1
+ - name: PA12_RMP
+ description: |-
+ PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port.
+ 0: No remap (PA12)
+ 1: Remap (PA10)
+ bit_offset: 4
+ bit_size: 1
+ - name: IR_POL
+ description: IR output polarity selection
+ bit_offset: 5
+ bit_size: 1
+ - name: IR_MOD
+ description: 'IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:'
+ bit_offset: 6
+ bit_size: 2
+ enum: IR_MOD
+ - name: BOOSTEN
+ description: 'I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high VDD, setting to 1 for low VDD (less than 2.4 V).'
+ bit_offset: 8
+ bit_size: 1
+ - name: I2C_PB6_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 16
+ bit_size: 1
+ - name: I2C_PB7_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 17
+ bit_size: 1
+ - name: I2C_PB8_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 18
+ bit_size: 1
+ - name: I2C_PB9_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 19
+ bit_size: 1
+ - name: I2C_PA9_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 22
+ bit_size: 1
+ - name: I2C_PA10_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 23
+ bit_size: 1
+ - name: I2C3_FMP
+ description: |-
+ Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
+ 0: Disable
+ 1: Enable
+ bit_offset: 24
+ bit_size: 1
+fieldset/CFGR2:
+ description: SYSCFG configuration register 2
+ fields:
+ - name: CCL
+ description: Cortex1-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex1-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.
+ bit_offset: 0
+ bit_size: 1
+ - name: SPL
+ description: SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input.
+ bit_offset: 1
+ bit_size: 1
+ - name: PVDL
+ description: PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.
+ bit_offset: 2
+ bit_size: 1
+ - name: ECCL
+ description: ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input.
+ bit_offset: 3
+ bit_size: 1
+ - name: BKPL
+ description: Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input.
+ bit_offset: 4
+ bit_size: 1
+ - name: BKPF
+ description: Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.
+ bit_offset: 7
+ bit_size: 1
+ - name: SPF
+ description: SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1.
+ bit_offset: 8
+ bit_size: 1
+fieldset/ITLINE0:
+ description: SYSCFG interrupt line 0 status register
+ fields:
+ - name: WWDG
+ description: Window watchdog interrupt pending flag
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE1:
+ description: SYSCFG interrupt line 1 status register
+ fields:
+ - name: PVDOUT
+ description: PVD supply monitoring interrupt request pending (EXTI line 16).
+ bit_offset: 0
+ bit_size: 1
+ - name: PVMOUT1
+ description: VDDUSB supply monitoring interrupt request pending (EXTI line 19)
+ bit_offset: 1
+ bit_size: 1
+ - name: PVMOUT3
+ description: ADC supply monitoring interrupt request pending (EXTI line 20)
+ bit_offset: 2
+ bit_size: 1
+ - name: PVMOUT4
+ description: DAC supply monitoring interrupt request pending (EXTI line 21)
+ bit_offset: 3
+ bit_size: 1
+fieldset/ITLINE10:
+ description: SYSCFG interrupt line 10 status register
+ fields:
+ - name: DMA1_CH2
+ description: DMA1 channel 2 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: DMA1_CH3
+ description: DMA1 channel 3 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE11:
+ description: SYSCFG interrupt line 11 status register
+ fields:
+ - name: DMAMUX
+ description: DMAMUX interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: DMA1_CH4
+ description: DMA1 channel 4 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+ - name: DMA1_CH5
+ description: DMA1 channel 5 interrupt request pending
+ bit_offset: 2
+ bit_size: 1
+ - name: DMA1_CH6
+ description: DMA1 channel 6 interrupt request pending
+ bit_offset: 3
+ bit_size: 1
+ - name: DMA1_CH7
+ description: DMA1 channel 7 interrupt request pending
+ bit_offset: 4
+ bit_size: 1
+ - name: DMA2_CH1
+ description: DMA2 channel 1 interrupt request pending
+ bit_offset: 5
+ bit_size: 1
+ - name: DMA2_CH2
+ description: DMA2 channel 2 interrupt request pending
+ bit_offset: 6
+ bit_size: 1
+ - name: DMA2_CH3
+ description: DMA2 channel 3 interrupt request pending
+ bit_offset: 7
+ bit_size: 1
+ - name: DMA2_CH4
+ description: DMA2 channel 4 interrupt request pending
+ bit_offset: 8
+ bit_size: 1
+ - name: DMA2_CH5
+ description: DMA2 channel 5 interrupt request pending
+ bit_offset: 9
+ bit_size: 1
+fieldset/ITLINE12:
+ description: SYSCFG interrupt line 12 status register
+ fields:
+ - name: ADC
+ description: ADC interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: COMP1
+ description: Comparator 1 interrupt request pending (EXTI line 17)
+ bit_offset: 1
+ bit_size: 1
+ - name: COMP2
+ description: Comparator 2 interrupt request pending (EXTI line 18)
+ bit_offset: 2
+ bit_size: 1
+fieldset/ITLINE13:
+ description: SYSCFG interrupt line 13 status register
+ fields:
+ - name: TIM1_CCU
+ description: Timer 1 commutation interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM1_TRG
+ description: Timer 1 trigger interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+ - name: TIM1_UPD
+ description: Timer 1 update interrupt request pending
+ bit_offset: 2
+ bit_size: 1
+ - name: TIM1_BRK
+ description: Timer 1 break interrupt request pending
+ bit_offset: 3
+ bit_size: 1
+fieldset/ITLINE14:
+ description: SYSCFG interrupt line 14 status register
+ fields:
+ - name: TIM1_CC1
+ description: Timer 1 capture compare 1 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: TIM1_CC2
+ description: Timer 1 capture compare 2 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+ - name: TIM1_CC3
+ description: Timer 1 capture compare 3 interrupt request pending
+ bit_offset: 2
+ bit_size: 1
+ - name: TIM1_CC4
+ description: Timer 1 capture compare 4 interrupt request pending
+ bit_offset: 3
+ bit_size: 1
+fieldset/ITLINE15:
+ description: SYSCFG interrupt line 15 status register
+ fields:
+ - name: TIM2
+ description: Timer 2 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE16:
+ description: SYSCFG interrupt line 16 status register
+ fields:
+ - name: TIM3
+ description: Timer 3 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE17:
+ description: SYSCFG interrupt line 17 status register
+ fields:
+ - name: TIM6
+ description: Timer 6 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: DAC
+ description: DAC underrun interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+ - name: LPTIM1
+ description: Low-power timer 1 interrupt request pending (EXTI line 29)
+ bit_offset: 2
+ bit_size: 1
+fieldset/ITLINE18:
+ description: SYSCFG interrupt line 18 status register
+ fields:
+ - name: TIM7
+ description: Timer 7 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: LPTIM2
+ description: Low-power timer 2 interrupt request pending (EXTI line 30)
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE19:
+ description: SYSCFG interrupt line 19 status register
+ fields:
+ - name: TIM15
+ description: Timer 15 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: LPTIM3
+ description: Low-power timer 3 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE2:
+ description: SYSCFG interrupt line 2 status register
+ fields:
+ - name: TAMP
+ description: Tamper interrupt request pending (EXTI line 21)
+ bit_offset: 0
+ bit_size: 1
+ - name: RTC
+ description: RTC interrupt request pending (EXTI line 19)
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE20:
+ description: SYSCFG interrupt line 20 status register
+ fields:
+ - name: TIM16
+ description: Timer 16 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE21:
+ description: SYSCFG interrupt line 21 status register
+ fields:
+ - name: TSC_MCE
+ description: TSC max count error interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: TSC_EOA
+ description: TSC end of acquisition interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE22:
+ description: SYSCFG interrupt line 22 status register
+ fields:
+ - name: LCD
+ description: LCD interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE23:
+ description: SYSCFG interrupt line 23 status register
+ fields:
+ - name: I2C1
+ description: I2C1 interrupt request pending (EXTI line 33)
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE24:
+ description: SYSCFG interrupt line 24 status register
+ fields:
+ - name: I2C2
+ description: I2C2 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: I2C4
+ description: I2C4 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+ - name: I2C3
+ description: I2C3 interrupt request pending (EXTI line 23)
+ bit_offset: 2
+ bit_size: 1
+fieldset/ITLINE25:
+ description: SYSCFG interrupt line 25 status register
+ fields:
+ - name: SPI1
+ description: SPI1 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE26:
+ description: SYSCFG interrupt line 26 status register
+ fields:
+ - name: SPI2
+ description: SPI2 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: SPI3
+ description: SPI3 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE27:
+ description: SYSCFG interrupt line 27 status register
+ fields:
+ - name: USART1
+ description: USART1 interrupt request pending, combined with EXTI line 25
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE28:
+ description: SYSCFG interrupt line 28 status register
+ fields:
+ - name: USART2
+ description: USART2 interrupt request pending (EXTI line 35)
+ bit_offset: 0
+ bit_size: 1
+ - name: LPUART2
+ description: LPUART2 interrupt request pending (EXTI line 31)
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE29:
+ description: SYSCFG interrupt line 29 status register
+ fields:
+ - name: USART3
+ description: USART3 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: LPUART1
+ description: LPUART1 interrupt request pending (EXTI line 30)
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE3:
+ description: SYSCFG interrupt line 3 status register
+ fields:
+ - name: FLASH_ITF
+ description: Flash interface interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: FLASH_ECC
+ description: Flash interface ECC interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE30:
+ description: SYSCFG interrupt line 30 status register
+ fields:
+ - name: USART4
+ description: USART4 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: LPUART3
+ description: LPUART3 interrupt request pending (EXTI line 32)
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE31:
+ description: SYSCFG interrupt line 31 status register
+ fields:
+ - name: RNG
+ description: RNG interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: AES
+ description: AES interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE4:
+ description: SYSCFG interrupt line 4 status register
+ fields:
+ - name: RCC
+ description: Reset and clock control interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: CRS
+ description: CRS interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE5:
+ description: SYSCFG interrupt line 5 status register
+ fields:
+ - name: EXTI0
+ description: EXTI line 0 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: EXTI1
+ description: EXTI line 1 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE6:
+ description: SYSCFG interrupt line 6 status register
+ fields:
+ - name: EXTI2
+ description: EXTI line 2 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: EXTI3
+ description: EXTI line 3 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+fieldset/ITLINE7:
+ description: SYSCFG interrupt line 7 status register
+ fields:
+ - name: EXTI4
+ description: EXTI line 4 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+ - name: EXTI5
+ description: EXTI line 5 interrupt request pending
+ bit_offset: 1
+ bit_size: 1
+ - name: EXTI6
+ description: EXTI line 6 interrupt request pending
+ bit_offset: 2
+ bit_size: 1
+ - name: EXTI7
+ description: EXTI line 7 interrupt request pending
+ bit_offset: 3
+ bit_size: 1
+ - name: EXTI8
+ description: EXTI line 8 interrupt request pending
+ bit_offset: 4
+ bit_size: 1
+ - name: EXTI9
+ description: EXTI line 9 interrupt request pending
+ bit_offset: 5
+ bit_size: 1
+ - name: EXTI10
+ description: EXTI line 10 interrupt request pending
+ bit_offset: 6
+ bit_size: 1
+ - name: EXTI11
+ description: EXTI line 11 interrupt request pending
+ bit_offset: 7
+ bit_size: 1
+ - name: EXTI12
+ description: EXTI line 12 interrupt request pending
+ bit_offset: 8
+ bit_size: 1
+ - name: EXTI13
+ description: EXTI line 13 interrupt request pending
+ bit_offset: 9
+ bit_size: 1
+ - name: EXTI14
+ description: EXTI line 14 interrupt request pending
+ bit_offset: 10
+ bit_size: 1
+ - name: EXTI15
+ description: EXTI line 15 interrupt request pending
+ bit_offset: 11
+ bit_size: 1
+fieldset/ITLINE8:
+ description: SYSCFG interrupt line 8 status register
+ fields:
+ - name: USB
+ description: USB interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/ITLINE9:
+ description: SYSCFG interrupt line 9 status register
+ fields:
+ - name: DMA1_CH1
+ description: DMA1 channel 1 interrupt request pending
+ bit_offset: 0
+ bit_size: 1
+fieldset/SCSR:
+ description: SYSCFG SRAM2 control and status register
+ fields:
+ - name: SRAM2ER
+ description: 'SRAM2 erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.'
+ bit_offset: 0
+ bit_size: 1
+ - name: SRAM2BSY
+ description: SRAM2 busy by erase operation
+ bit_offset: 1
+ bit_size: 1
+fieldset/SKR:
+ description: SYSCFG SRAM2 key register
+ fields:
+ - name: KEY
+ description: 'SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: Write 0xCA into KEY[7:0] Write 0x53 into KEY[7:0] Writing a wrong key reactivates the write protection.'
+ bit_offset: 0
+ bit_size: 8
+fieldset/TSCCR:
+ description: SYSCFG TSC comparator register
+ fields:
+ - name: G2_IO1
+ description: Comparator mode for group 2 on I/O 1
+ bit_offset: 0
+ bit_size: 1
+ - name: G2_IO3
+ description: Comparator mode for group 2 on I/O 3
+ bit_offset: 1
+ bit_size: 1
+ - name: G4_IO3
+ description: Comparator mode for group 4 on I/O 3
+ bit_offset: 2
+ bit_size: 1
+ - name: G6_IO1
+ description: Comparator mode for group 6 on I/O 1
+ bit_offset: 3
+ bit_size: 1
+ - name: G7_IO1
+ description: Comparator mode for group 7 on I/O 1
+ bit_offset: 4
+ bit_size: 1
+ - name: TSC_IOCTRL
+ description: I/O control in comparator mode The I/O control in comparator mode can be overwritten by hardware.
+ bit_offset: 5
+ bit_size: 1
+enum/IR_MOD:
+ bit_size: 2
+ variants:
+ - name: TIM16
+ description: TIM16
+ value: 0
+ - name: USART1
+ description: USART1
+ value: 1
+ - name: USART2
+ description: USART2
+ value: 2
+enum/MEM_MODE:
+ bit_size: 2
+ variants:
+ - name: System_Flash
+ description: System flash memory mapped at 0x000010000
+ value: 1
+ - name: SRAM
+ description: Embedded SRAM mapped at 0x000010000
+ value: 3
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index 1fd1893..cfa12e0 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -58,7 +58,9 @@ mod xml {
}
pub struct Chip {
+ #[allow(dead_code)]
flash: u32,
+ #[allow(dead_code)]
ram: u32,
group_idx: usize,
packages: Vec,
@@ -210,7 +212,7 @@ impl PeriMatcher {
("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")),
("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")),
- ("STM32G4.*:ADC:.*", ("adc", "v4", "ADC")),
+ ("STM32G4.*:ADC:.*", ("adc", "g4", "ADC")),
("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
(".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")),
(".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")),
@@ -247,6 +249,7 @@ impl PeriMatcher {
("syscfg", "h7od", "SYSCFG"),
),
("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")),
+ ("STM32U0.*:SYSCFG:.*", ("syscfg", "u0", "SYSCFG")),
("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")),
("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")),
("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
@@ -342,6 +345,7 @@ impl PeriMatcher {
("STM32L4[PQRS].*:RCC:.*", ("rcc", "l4plus", "RCC")),
("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")),
("STM32L5.*:RCC:.*", ("rcc", "l5", "RCC")),
+ ("STM32U0.*:RCC:.*", ("rcc", "u0", "RCC")),
("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")),
("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")),
("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")),
@@ -357,6 +361,7 @@ impl PeriMatcher {
("STM32C0.*:EXTI:.*", ("exti", "c0", "EXTI")),
("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")),
("STM32H7.*:EXTI:.*", ("exti", "h7", "EXTI")),
+ ("STM32U0.*:EXTI:.*", ("exti", "u0", "EXTI")),
("STM32U5.*:EXTI:.*", ("exti", "u5", "EXTI")),
("STM32WB.*:EXTI:.*", ("exti", "w", "EXTI")),
("STM32WL5.*:EXTI:.*", ("exti", "w", "EXTI")),
@@ -394,6 +399,7 @@ impl PeriMatcher {
("STM32L1.*:PWR:.*", ("pwr", "l1", "PWR")),
("STM32L4.*:PWR:.*", ("pwr", "l4", "PWR")),
("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")),
+ ("STM32U0.*:PWR:.*", ("pwr", "u0", "PWR")),
("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")),
("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")),
("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")),
@@ -413,13 +419,16 @@ impl PeriMatcher {
("STM32L1.*:FLASH:.*", ("flash", "l1", "FLASH")),
("STM32L4.*:FLASH:.*", ("flash", "l4", "FLASH")),
("STM32L5.*:FLASH:.*", ("flash", "l5", "FLASH")),
+ ("STM32U0.*:FLASH:.*", ("flash", "u0", "FLASH")),
("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")),
("STM32WBA.*:FLASH:.*", ("flash", "wba", "FLASH")),
("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")),
("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")),
("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")),
("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")),
- ("STM32G4.*:FLASH:.*", ("flash", "g4", "FLASH")),
+ ("STM32G4(3|4).*:FLASH:.*", ("flash", "g4c2", "FLASH")),
+ ("STM32G4(7|8).*:FLASH:.*", ("flash", "g4c3", "FLASH")),
+ ("STM32G4(9|A).*:FLASH:.*", ("flash", "g4c4", "FLASH")),
("STM32H50.*:FLASH:.*", ("flash", "h50", "FLASH")),
("STM32H5.*:FLASH:.*", ("flash", "h5", "FLASH")),
("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")),
@@ -482,18 +491,25 @@ impl PeriMatcher {
("STM32L.*:TIM(9|21|22):.*", ("timer", "v1", "TIM_2CH")),
("STM32L.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")),
("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")),
+ ("STM32L5.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")),
("STM32L.*:LPTIM(1|2|3):.*", ("lptim", "v1", "LPTIM")),
// AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials
// timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials
("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")),
- ("STM32(G4|H5|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")),
- ("STM32(G4|H5|U5|WBA).*:TIM(2|5|23|24):.*", ("timer", "v2", "TIM_GP32")),
- ("STM32(G4|H5|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")),
- ("STM32(G4|H5|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")),
- ("STM32(G4|H5|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")),
- ("STM32(G4|H5|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")),
- ("STM32(G4|H5|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")),
- ("STM32(G4|H5|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")),
+ (
+ "STM32(G4|H5|U0|U5|WBA).*:TIM(2|5|23|24):.*",
+ ("timer", "v2", "TIM_GP32"),
+ ),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")),
+ ("STM32(G4|H5|U0|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")),
+ ("STM32WL.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")),
+ ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")),
+ ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")),
("STM32G4.*:HRTIM1:.*", ("hrtim", "v2", "HRTIM")),
// timer_v1 for STM32Gx/Hx/Ux/Wx (and Cx) serials
("STM32(C|G0|H7|WB|WL).*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")),
@@ -504,7 +520,7 @@ impl PeriMatcher {
("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")),
("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")),
("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")),
- ("STM32[CGHUW].*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")),
+ ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")),
("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")),
//
//// TIM mapping ends here ////
@@ -530,6 +546,14 @@ impl PeriMatcher {
("STM32F1.*:GPIO.*", ("gpio", "v1", "GPIO")),
(".*:GPIO.*", ("gpio", "v2", "GPIO")),
(".*:IPCC:v1_0", ("ipcc", "v1", "IPCC")),
+ ("STM32H7(4|5)(5|7).*:HSEM:.*", ("hsem", "v1", "HSEM")),
+ ("STM32WB55.*:HSEM:.*", ("hsem", "v1", "HSEM")),
+ ("STM32H735.*:HSEM:.*", ("hsem", "v2", "HSEM")),
+ ("STM32H7B3.*:HSEM:.*", ("hsem", "v2", "HSEM")),
+ ("STM32H753.*:HSEM:.*", ("hsem", "v2", "HSEM")),
+ ("STM32H743.*:HSEM:.*", ("hsem", "v2", "HSEM")),
+ ("STM32WL5.*:HSEM:.*", ("hsem", "v3", "HSEM")),
+ ("STM32WLE.*:HSEM:.*", ("hsem", "v4", "HSEM")),
(".*:DMAMUX.*", ("dmamux", "v1", "DMAMUX")),
(r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")),
(r".*:BDMA\d?:.*", ("bdma", "v1", "DMA")),
@@ -603,6 +627,7 @@ impl PeriMatcher {
("STM32F0x[128].*:TSC:.*", ("tsc", "v1", "TSC")),
("STM32F3[07][123].*:TSC:.*", ("tsc", "v1", "TSC")),
("STM32WB55.*:TSC:.*", ("tsc", "v2", "TSC")),
+ ("STM32WBA.*:TSC:.*", ("tsc", "v1", "TSC")),
("STM32L[045].*:TSC:.*", ("tsc", "v3", "TSC")),
("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")),
("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")),
@@ -760,11 +785,19 @@ pub fn parse_groups() -> Result<(HashMap, Vec), anyhow:
static NOPELIST: &[&str] = &[
// Not supported, not planned unless someone wants to do it.
"STM32MP",
+ // not supported yet, planned. Pull requests welcome!
+ "STM32H52",
+ "STM32H53",
+ "STM32H7R",
+ "STM32H7S",
+ "STM32U5F",
+ "STM32U5G",
+ "STM32WBA50",
+ "STM32WBA54",
+ "STM32WBA55",
// Does not exist in ST website. No datasheet, no RM.
"STM32GBK",
"STM32L485",
- "STM32U5F",
- "STM32U5G",
// STM32WxM modules. These are based on a chip that's supported on its own,
// not sure why we want a separate target for it.
"STM32WL5M",
@@ -889,7 +922,6 @@ fn process_group(
peripheral_to_clock: &rcc::ParsedRccs,
dma_channels: &dma::DmaChannels,
chips: &HashMap,
- memories: &memory::Memories,
docs: &docs::Docs,
) -> Result<(), anyhow::Error> {
let chip_name = group.chip_names[0].clone();
@@ -906,6 +938,7 @@ fn process_group(
let chip_af = &group.ips.values().find(|x| x.name == "GPIO").unwrap().version;
let chip_af = chip_af.strip_suffix("_gpio_v1_0").unwrap();
let chip_af = af.0.get(chip_af);
+
let cores: Vec<_> = group
.xml
.cores
@@ -927,7 +960,7 @@ fn process_group(
.collect();
for chip_name in &group.chip_names {
- process_chip(chips, chip_name, h, memories, docs, &group, &cores)?;
+ process_chip(chips, chip_name, h, docs, &group, &cores)?;
}
Ok(())
@@ -950,7 +983,6 @@ fn process_core(
let defines = h.get_defines(&core_name);
let mut peri_kinds = HashMap::new();
- peri_kinds.insert("UID".to_string(), "UID".to_string());
for ip in group.ips.values() {
let pname = ip.instance_name.clone();
let pkind = format!("{}:{}", ip.name, ip.version);
@@ -1041,6 +1073,8 @@ fn process_core(
"BKP",
"USBRAM",
"VREFINTCAL",
+ "UID",
+ "HSEM",
];
for pname in GHOST_PERIS {
if let Entry::Vacant(entry) = peri_kinds.entry(pname.to_string()) {
@@ -1322,160 +1356,21 @@ fn process_core(
fn process_chip(
chips: &HashMap,
chip_name: &str,
- h: &header::ParsedHeader,
- memories: &memory::Memories,
+ _h: &header::ParsedHeader,
docs: &docs::Docs,
group: &ChipGroup,
cores: &[stm32_data_serde::chip::Core],
) -> Result<(), anyhow::Error> {
let chip = chips.get(chip_name).unwrap();
- let flash_size = chip.flash * 1024;
- let ram_total = chip.ram * 1024;
- let memory = memories.get(group.die.as_ref().unwrap());
- let mut flash_remaining = flash_size;
- let mut memory_regions = Vec::new();
- let mut found = HashSet::<&str>::new();
- for each in [
- // We test FLASH_BANKx _before_ FLASH as we prefer their definition over the legacy one
- "FLASH_BANK1",
- "FLASH_BANK2",
- "FLASH",
- "FLASH_OTP",
- "D1_AXIFLASH",
- "D1_AXIICP",
- ] {
- if let Some(address) = h.defines.get("all").unwrap().0.get(&format!("{each}_BASE")) {
- let (key, banks) = match each {
- "FLASH" => (
- "BANK_1",
- Some([memory::FlashBank::Bank1, memory::FlashBank::Bank2].as_ref()),
- ),
- "FLASH_BANK1" => ("BANK_1", Some([memory::FlashBank::Bank1].as_ref())),
- "FLASH_BANK2" => ("BANK_2", Some([memory::FlashBank::Bank2].as_ref())),
- "FLASH_OTP" => ("OTP", Some([memory::FlashBank::Otp].as_ref())),
- each => (each, None),
- };
-
- if found.contains(key) {
- continue;
- }
- found.insert(key);
-
- if let Some(banks) = banks {
- for bank in banks {
- let bank_name = match bank {
- memory::FlashBank::Bank1 => "BANK_1",
- memory::FlashBank::Bank2 => "BANK_2",
- memory::FlashBank::Otp => "OTP",
- };
- let regions: Vec<_> = memory
- .flash_regions
- .iter()
- .filter(|region| region.bank == *bank)
- .enumerate()
- .map_while(|(index, region)| {
- let size = if *bank == memory::FlashBank::Bank1 || *bank == memory::FlashBank::Bank2 {
- // Truncate region to the total amount of remaining chip flash
- let size = std::cmp::min(region.bytes, flash_remaining);
- flash_remaining -= size;
- if size == 0 {
- // No more regions are present on this chip
- return None;
- }
- size
- } else {
- region.bytes
- };
-
- Some((index, region.address, size, region.settings.clone()))
- })
- .collect();
- let has_multiple_regions = regions.len() > 1;
- for (index, address, size, settings) in regions {
- let name = if has_multiple_regions {
- format!("{}_REGION_{}", bank_name, index + 1)
- } else {
- bank_name.to_string()
- };
-
- memory_regions.push(stm32_data_serde::chip::Memory {
- name,
- kind: stm32_data_serde::chip::memory::Kind::Flash,
- address,
- size,
- settings: Some(settings.clone()),
- });
- }
- }
- } else {
- memory_regions.push(stm32_data_serde::chip::Memory {
- name: key.to_string(),
- kind: stm32_data_serde::chip::memory::Kind::Flash,
- address: u32::try_from(*address).unwrap(),
- size: 0,
- settings: None,
- })
- }
- }
- }
- let mut found = HashSet::new();
- for each in [
- "SRAM",
- "SRAM1",
- "SRAM2",
- "D1_AXISRAM",
- "D1_ITCMRAM",
- "D1_DTCMRAM",
- "D1_AHBSRAM",
- "D2_AXISRAM",
- "D3_BKPSRAM",
- "D3_SRAM",
- ] {
- if let Some(address) = h.defines.get("all").unwrap().0.get(&format!("{each}_BASE")) {
- let key = match each {
- "D1_AXISRAM" => "SRAM",
- "SRAM1" => "SRAM",
- each => each,
- };
-
- if found.contains(key) {
- continue;
- }
- found.insert(key);
-
- let size = if key == "SRAM" {
- // if memory.ram.bytes != ram_total {
- // println!(
- // "SRAM mismatch for chip {} with die {}: Expected {} was {}",
- // chip_name,
- // group.die.as_ref().unwrap(),
- // ram_total,
- // memory.ram.bytes,
- // );
- // }
- std::cmp::min(memory.ram.bytes, ram_total)
- } else {
- 0
- };
-
- memory_regions.push(stm32_data_serde::chip::Memory {
- name: key.to_string(),
- kind: stm32_data_serde::chip::memory::Kind::Ram,
- address: u32::try_from(*address).unwrap(),
- size,
- settings: None,
- })
- }
- }
let docs = docs.documents_for(chip_name);
let chip = stm32_data_serde::Chip {
name: chip_name.to_string(),
family: group.family.clone().unwrap(),
line: group.line.clone().unwrap(),
die: group.die.clone().unwrap(),
- device_id: memory.device_id,
+ device_id: u16::from_str_radix(&group.die.as_ref().unwrap()[3..], 16).unwrap(),
packages: chip.packages.clone(),
- memory: memory_regions,
+ memory: memory::get(chip_name),
docs,
cores: cores.to_vec(),
};
@@ -1516,7 +1411,6 @@ pub fn dump_all_chips(
peripheral_to_clock: rcc::ParsedRccs,
dma_channels: dma::DmaChannels,
chips: std::collections::HashMap,
- memories: memory::Memories,
docs: docs::Docs,
) -> Result<(), anyhow::Error> {
std::fs::create_dir_all("build/data/chips")?;
@@ -1537,7 +1431,6 @@ pub fn dump_all_chips(
&peripheral_to_clock,
&dma_channels,
&chips,
- &memories,
&docs,
)
})
@@ -1556,7 +1449,6 @@ pub fn dump_all_chips(
&peripheral_to_clock,
&dma_channels,
&chips,
- &memories,
&docs,
)
})
diff --git a/stm32-data-gen/src/interrupts.rs b/stm32-data-gen/src/interrupts.rs
index 2c8aa47..cdbcd28 100644
--- a/stm32-data-gen/src/interrupts.rs
+++ b/stm32-data-gen/src/interrupts.rs
@@ -245,6 +245,14 @@ impl ChipInterrupts {
interrupt_signals.insert(("RCC".to_string(), "CRS".to_string()));
} else if name == "RCC" {
interrupt_signals.insert(("RCC".to_string(), "GLOBAL".to_string()));
+ } else if name == "RNG_CRYP" {
+ interrupt_signals.insert(("RNG".to_string(), "GLOBAL".to_string()));
+ interrupt_signals.insert(("CRYP".to_string(), "GLOBAL".to_string()));
+ } else if name == "WWDG_IWDG" {
+ interrupt_signals.insert(("WWDG".to_string(), "GLOBAL".to_string()));
+ interrupt_signals.insert(("IWDG".to_string(), "GLOBAL".to_string()));
+ } else if name == "RCC_AUDIOSYNC" {
+ // ignore
} else {
if parts[2].is_empty() {
trace!(" skipping because parts[2].is_empty()");
diff --git a/stm32-data-gen/src/main.rs b/stm32-data-gen/src/main.rs
index 677e31a..c687f42 100644
--- a/stm32-data-gen/src/main.rs
+++ b/stm32-data-gen/src/main.rs
@@ -69,9 +69,6 @@ fn main() -> anyhow::Result<()> {
let registers = registers::Registers::parse()?;
registers.write()?;
- // stopwatch.section("Parsing memories");
- let memories = memory::Memories::parse()?;
-
// stopwatch.section("Parsing interrupts");
let chip_interrupts = interrupts::ChipInterrupts::parse()?;
@@ -99,7 +96,6 @@ fn main() -> anyhow::Result<()> {
peripheral_to_clock,
dma_channels,
chips,
- memories,
docs,
)?;
diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs
index 817bea7..e92fb15 100644
--- a/stm32-data-gen/src/memory.rs
+++ b/stm32-data-gen/src/memory.rs
@@ -1,288 +1,359 @@
-use std::cmp::Ordering;
-use std::collections::HashMap;
-use std::fs;
+use regex::Regex;
+use stm32_data_serde::chip::memory::{self, Settings};
+use stm32_data_serde::chip::Memory;
-#[derive(Debug, PartialEq)]
-pub struct Memory {
- pub device_id: u16,
- pub ram: Ram,
- pub flash_size: u32,
- pub flash_regions: Vec,
+struct Mem {
+ name: &'static str,
+ address: u32,
+ size: u32,
}
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub struct Ram {
- pub address: u32,
- pub bytes: u32,
-}
-
-#[derive(Clone, Debug, PartialEq)]
-pub struct FlashRegion {
- pub bank: FlashBank,
- pub address: u32,
- pub bytes: u32,
- pub settings: stm32_data_serde::chip::memory::Settings,
-}
-
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum FlashBank {
- Bank1,
- Bank2,
- Otp,
-}
-
-mod xml {
- use serde::Deserialize;
-
- pub fn from_hex<'de, T, D>(deserializer: D) -> Result
- where
- D: serde::Deserializer<'de>,
- T: num::Num,
- T::FromStrRadixErr: std::fmt::Display,
- {
- use serde::de::Error;
- let s: &str = Deserialize::deserialize(deserializer)?;
- let s = s.trim();
- let (prefix, num) = s.split_at(2);
- if prefix != "0x" && prefix != "0X" {
- panic!("no hex prefix");
- }
- T::from_str_radix(num, 16).map_err(D::Error::custom)
- }
-
- pub fn opt_from_hex<'de, T, D>(deserializer: D) -> Result, D::Error>
- where
- D: serde::Deserializer<'de>,
- T: num::Num,
- T::FromStrRadixErr: std::fmt::Display,
- {
- Ok(Some(from_hex(deserializer)?))
- }
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Root {
- #[serde(rename = "Device")]
- pub device: root::Device,
- }
-
- mod root {
- use serde::Deserialize;
-
- use super::from_hex;
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Device {
- #[serde(rename = "DeviceID", deserialize_with = "from_hex")]
- pub device_id: u16,
- #[serde(rename = "Name")]
- pub name: String,
- #[serde(rename = "Peripherals")]
- pub peripherals: device::Peripherals,
- }
-
- mod device {
- use serde::Deserialize;
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Peripherals {
- #[serde(rename = "Peripheral")]
- pub peripharal: Vec,
- }
-
- mod peripherals {
- use serde::Deserialize;
-
- use super::super::super::opt_from_hex;
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Peripheral {
- #[serde(rename = "Name")]
- // pub name: peripheral::Name,
- pub name: String,
- #[serde(rename = "ErasedValue", deserialize_with = "opt_from_hex", default)]
- pub erased_value: Option,
- #[serde(rename = "Configuration", default)]
- pub configuration: Vec,
- }
-
- mod peripheral {
- use serde::Deserialize;
-
- use super::super::super::super::opt_from_hex;
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Configuration {
- #[serde(rename = "Parameters", default)]
- pub parameters: Option,
- #[serde(rename = "Organization", default)]
- pub organization: Option,
- #[serde(rename = "Allignement", deserialize_with = "opt_from_hex", default)]
- pub allignement: Option,
- #[serde(rename = "Bank")]
- pub bank: Vec,
- }
-
- mod configuration {
- use serde::Deserialize;
-
- use super::super::super::super::super::{from_hex, opt_from_hex};
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Parameters {
- #[serde(deserialize_with = "from_hex")]
- pub address: u32,
- #[serde(deserialize_with = "from_hex")]
- pub size: u32,
- #[serde(deserialize_with = "opt_from_hex", default)]
- pub occurence: Option,
- }
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Bank {
- #[serde(default)]
- pub name: Option,
- #[serde(rename = "Field", default)]
- pub field: Vec,
- }
-
- mod bank {
- use serde::Deserialize;
-
- #[derive(Debug, Deserialize, PartialEq)]
- pub struct Field {
- #[serde(rename = "Parameters")]
- pub parameters: super::Parameters,
- }
- }
- }
- }
- }
- }
- }
-}
-pub struct Memories(HashMap);
-
-impl Memories {
- pub fn parse() -> anyhow::Result {
- let mut paths: Vec<_> = glob::glob("sources/cubeprogdb/db/*.xml")
- .unwrap()
- .map(Result::unwrap)
- .collect();
- paths.sort();
-
- let mut memories = HashMap::new();
-
- for f in paths {
- // println!("Parsing {f:?}");
- let file = fs::read_to_string(f)?;
- let parsed: xml::Root = quick_xml::de::from_str(&file)?;
- // dbg!(&parsed);
-
- let device_id = parsed.device.device_id;
-
- let mut ram = None;
- let mut flash_size = None;
- let mut flash_regions = vec![];
-
- for mut peripheral in parsed.device.peripherals.peripharal {
- if peripheral.name == "Embedded SRAM" && ram.is_none() {
- let config = peripheral.configuration.first().unwrap();
- let parameters = config.parameters.as_ref().unwrap();
- ram = Some(Ram {
- address: parameters.address,
- bytes: parameters.size,
- });
- }
-
- enum BlockKind {
- Main,
- Otp,
- }
- let kind = match peripheral.name.as_str() {
- "Embedded Flash" => Some(BlockKind::Main),
- "OTP" => Some(BlockKind::Otp),
- _ => None,
- };
-
- if let Some(kind) = kind {
- peripheral.configuration.sort_by(|a, b| {
- // Prefer largest size
- let ordering = b
- .parameters
- .as_ref()
- .unwrap()
- .size
- .partial_cmp(&a.parameters.as_ref().unwrap().size)
- .unwrap();
-
- // ... then prefer single ordering over dual
- if ordering == Ordering::Equal {
- // Possible values are Single and Dual
- b.organization.partial_cmp(&a.organization).unwrap()
- } else {
- ordering
- }
- });
- let config = peripheral.configuration.first().unwrap();
-
- if flash_size.is_none() {
- let parameters = config.parameters.as_ref().unwrap();
-
- flash_size = Some(parameters.size);
- }
-
- for bank in config.bank.iter() {
- let flash_bank = match kind {
- BlockKind::Main => match bank.name.as_deref() {
- Some("Bank 1") => Some(FlashBank::Bank1),
- Some("Bank 2") => Some(FlashBank::Bank2),
- Some("EEPROM1") => None,
- Some("EEPROM2") => None,
- None => {
- assert_eq!(1, config.bank.len());
- Some(FlashBank::Bank1)
- }
- Some(other) => unimplemented!("Unsupported flash bank {}", other),
- },
- BlockKind::Otp => Some(FlashBank::Otp),
- };
-
- if let Some(flash_bank) = flash_bank {
- let erase_value = peripheral.erased_value.unwrap();
- let write_size = config.allignement.unwrap();
- flash_regions.extend(bank.field.iter().map(|field| FlashRegion {
- bank: flash_bank,
- address: field.parameters.address,
- bytes: field.parameters.occurence.unwrap() * field.parameters.size,
- settings: stm32_data_serde::chip::memory::Settings {
- erase_value,
- write_size,
- erase_size: field.parameters.size,
- },
- }));
- }
- }
- }
- }
-
- memories.insert(
- device_id,
- Memory {
- device_id,
- ram: ram.unwrap(),
- flash_size: flash_size.unwrap_or_default(),
- flash_regions,
+macro_rules! mem {
+ ($($name:ident $addr:literal $size:literal),*) => {
+ &[
+ $(
+ Mem {
+ name: stringify!($name),
+ address: $addr,
+ size: $size*1024,
},
- );
- }
+ )*
+ ]
+ };
+}
- Ok(Self(memories))
+#[rustfmt::skip]
+static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
+ // C0. TODO: check
+ ("STM32C01..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
+ ("STM32C01..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
+ ("STM32C03..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
+ ("STM32C03..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
+ // F0. TODO: check
+ ("STM32F0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
+ ("STM32F0[35]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
+ ("STM32F0[47]..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
+ ("STM32F03..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 4)),
+ ("STM32F03..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 4)),
+ ("STM32F04..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
+ ("STM32F05..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
+ ("STM32F05..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
+ ("STM32F07..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
+ ("STM32F07..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
+ ("STM32F09..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
+ // F1. TODO: check
+ ("STM32F1.[12].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
+ ("STM32F1.[12].8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
+ ("STM32F1.[12].B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
+ ("STM32F1.[57].B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64)),
+ ("STM32F1.[57].C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 64)),
+ ("STM32F1.0.6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 4)),
+ ("STM32F1.0.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
+ ("STM32F1.0.B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 8)),
+ ("STM32F1.0.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 24)),
+ ("STM32F1.0.D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 32)),
+ ("STM32F1.0.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 32)),
+ ("STM32F1.1.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
+ ("STM32F1.1.D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 48)),
+ ("STM32F1.1.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 48)),
+ ("STM32F1.1.F", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 256, SRAM 0x20000000 80)),
+ ("STM32F1.1.G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 80)),
+ ("STM32F1.3.6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 10)),
+ ("STM32F1.3.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20)),
+ ("STM32F1.3.B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20)),
+ ("STM32F1.3.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 48)),
+ ("STM32F1.3.D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
+ ("STM32F1.3.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
+ ("STM32F1.3.F", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 256, SRAM 0x20000000 96)),
+ ("STM32F1.3.G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 96)),
+ ("STM32F1.5.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 64)),
+ ("STM32F10[012].4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 4)),
+ ("STM32F103.4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
+ // F2. TODO: check
+ ("STM32F2...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64, SRAM2 0x2001c000 0)),
+ ("STM32F2...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ ("STM32F2...F", mem!(BANK_1 0x08000000 768, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ ("STM32F2...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ ("STM32F2.5.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x2001c000 0)),
+ ("STM32F2.7.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ // F3. TODO: check
+ ("STM32F3...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
+ ("STM32F3...D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
+ ("STM32F3...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
+ ("STM32F3.[12].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)),
+ ("STM32F3.[34].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
+ ("STM32F3([17]..8|0[12].8)", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
+ ("STM32F3([23]..8|03.8)", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12)),
+ ("STM32F3[05]..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 40)),
+ ("STM32F30..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
+ ("STM32F37..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 24)),
+ ("STM32F37..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
+ // F4. TODO: check
+ ("STM32F4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
+ ("STM32F4...D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
+ ("STM32F4...H", mem!(BANK_1 0x08000000 1536, SRAM 0x20000000 320, SRAM2 0x20040000 0)),
+ ("STM32F4.[567].E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ ("STM32F4.1.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 64)),
+ ("STM32F4.1.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
+ ("STM32F4.2.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 256)),
+ ("STM32F4.6.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ ("STM32F4(1[57].G|0..G)", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
+ ("STM32F4[23]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
+ ("STM32F4[23]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
+ ("STM32F4[67]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
+ ("STM32F4[67]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
+ ("STM32F40..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64)),
+ ("STM32F41..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
+ ("STM32F412.G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 256)),
+ ("STM32F413.G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 320, SRAM2 0x20040000 0)),
+ ("STM32F429.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
+ ("STM32F469.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
+ // F7. TODO: check
+ ("STM32F7...C", mem!(BANK_1 0x08000000 256, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
+ ("STM32F7...I", mem!(BANK_1 0x08000000 2048, SRAM 0x20020000 384, SRAM2 0x2007c000 0)),
+ ("STM32F7[23]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
+ ("STM32F7[45]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
+ ("STM32F73..8", mem!(BANK_1 0x08000000 64, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
+ ("STM32F74..E", mem!(BANK_1 0x08000000 512, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
+ ("STM32F75..8", mem!(BANK_1 0x08000000 64, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
+ ("STM32F76..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20020000 384, SRAM2 0x2007c000 0)),
+ // G0. TODO: check
+ ("STM32G0...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
+ ("STM32G0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
+ ("STM32G0...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 128)),
+ ("STM32G0[34]..[68]", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
+ ("STM32G0[56]..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)),
+ ("STM32G0[56]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
+ ("STM32G0[78]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
+ ("STM32G07..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 32)),
+ ("STM32G07..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
+ ("STM32G0B..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 128)),
+ // G4. TODO: check
+ ("STM32G4...6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
+ ("STM32G4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
+ ("STM32G4[34]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
+ ("STM32G4[78]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
+ ("STM32G4[9A]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 32, SRAM2 0x20014000 0)),
+ ("STM32G47..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
+ ("STM32G47..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
+ ("STM32G49..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32, SRAM2 0x20014000 0)),
+ // H5. TODO: check
+ ("STM32H5...B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM 0x20000000 32, SRAM2 0x20004000 0)),
+ ("STM32H5...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)),
+ ("STM32H5...I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)),
+ // H7. TODO: check
+ ("STM32H7...E", mem!(BANK_1 0x08000000 512, SRAM 0x24000000 128)),
+ ("STM32H7[23]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 128)),
+ ("STM32H7[45]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x24000000 512)),
+ ("STM32H7[AB]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x24000000 1024)),
+ ("STM32H73..B", mem!(BANK_1 0x08000000 128, SRAM 0x24000000 128)),
+ ("STM32H74..G", mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 512)),
+ ("STM32H75..B", mem!(BANK_1 0x08000000 128, SRAM 0x24000000 512)),
+ ("STM32H7A..G", mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 1024)),
+ ("STM32H7B..B", mem!(BANK_1 0x08000000 128, SRAM 0x24000000 1024)),
+ // L0. TODO: check
+ ("STM32L0...3", mem!(BANK_1 0x08000000 8, SRAM 0x20000000 2)),
+ ("STM32L0...6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
+ ("STM32L0...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20)),
+ ("STM32L0...Z", mem!(BANK_1 0x08000000 192, SRAM 0x20000000 20)),
+ ("STM32L0[12]..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 2)),
+ ("STM32L0[156]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
+ ("STM32L0[34]..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
+ ("STM32L0[78]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20)),
+ // L1. TODO: check
+ ("STM32L1...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 10)),
+ ("STM32L1...C..", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 64, SRAM 0x20000000 32)),
+ ("STM32L1...D..", mem!(BANK_1 0x08000000 128, BANK_2 0x08040000 256, SRAM 0x20000000 80)),
+ ("STM32L1...D", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 192, SRAM 0x20000000 48)),
+ ("STM32L1...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 80)),
+ ("STM32L1(6.[RV]C|5.[CRUV]C)", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
+ ("STM32L1[56].[QZ]C", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 64, SRAM 0x20000000 32)),
+ ("STM32L10..6..", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 10)),
+ ("STM32L10..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 4)),
+ ("STM32L10..8..", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
+ ("STM32L10..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
+ ("STM32L10..B..", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 10)),
+ ("STM32L10..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 16)),
+ ("STM32L15..6..", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)),
+ ("STM32L15..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 10)),
+ ("STM32L15..8..", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
+ ("STM32L15..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
+ ("STM32L15..B..", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
+ // L4. TODO: check
+ ("STM32L4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 40)),
+ ("STM32L4...I", mem!(BANK_1 0x08000000 2048, SRAM 0x20000000 192)),
+ ("STM32L4[12]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 40)),
+ ("STM32L4[34]..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 48)),
+ ("STM32L4[56]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128)),
+ ("STM32L4[78]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 96)),
+ ("STM32L4[9A]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 256)),
+ ("STM32L43..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 48)),
+ ("STM32L45..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
+ ("STM32L47..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96)),
+ ("STM32L47..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96)),
+ ("STM32L49..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 256)),
+ // L4+. TODO: check
+ ("STM32L4[PQR]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 192)),
+ ("STM32L4P..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192)),
+ // L5. TODO: check
+ ("STM32L5...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 256, SRAM2 0x20030000 0)),
+ ("STM32L5...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 256, SRAM2 0x20030000 0)),
+ // U0
+ ("STM32U031.4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
+ ("STM32U031.6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
+ ("STM32U031.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12)),
+ ("STM32U0[78]3.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 40)),
+ ("STM32U0[78]3.B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 40)),
+ ("STM32U0[78]3.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 40)),
+ // U5
+ ("STM32U5[34]..B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM 0x20000000 192, SRAM2 0x20030000 64)),
+ ("STM32U5[34]..C", mem!(BANK_1 0x08000000 128, BANK_2 0x08020000 128, SRAM 0x20000000 192, SRAM2 0x20030000 64)),
+ ("STM32U5[43]..E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 192, SRAM2 0x20030000 64)),
+ ("STM32U5[78]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 192, SRAM2 0x20030000 64, SRAM3 0x20040000 512)),
+ ("STM32U5[78]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 192, SRAM2 0x20030000 64, SRAM3 0x20040000 512)),
+ ("STM32U5[9A]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832)),
+ ("STM32U5[9A]..J", mem!(BANK_1 0x08000000 2048, BANK_2 0x08200000 2048, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832)),
+ ("STM32U5[FG]..J", mem!(BANK_1 0x08000000 2048, BANK_2 0x08200000 2048, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832, SRAM6 0x20270000 512)),
+ // WB. TODO: check
+ ("STM32WB...Y", mem!(BANK_1 0x08000000 640, SRAM 0x20000000 192)),
+ ("STM32WB.(0C|5V)G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128)),
+ ("STM32WB.(5C|5R)G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 192)),
+ ("STM32WB1..C", mem!(BANK_1 0x08000000 320, SRAM 0x20000000 12)),
+ ("STM32WB3..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96)),
+ ("STM32WB3..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96)),
+ ("STM32WB5..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
+ ("STM32WB5.[CR]E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192)),
+ ("STM32WB5.VE", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128)),
+ // WBA. TODO: check
+ ("STM32WBA...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96, SRAM2 0x20010000 0)),
+ ("STM32WBA...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x20010000 0)),
+ // WL. TODO: check
+ ("STM32WL...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
+ ("STM32WL...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
+ ("STM32WL...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
+]);
+
+struct FlashInfo {
+ write_size: u32,
+ erase_size: &'static [(u32, u32)],
+ erase_value: u8,
+}
+
+#[rustfmt::skip]
+static FLASH_INFO: RegexMap = RegexMap::new(&[
+ ("STM32C0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32F030.C", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }),
+ ("STM32F070.6", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 1*1024, 0)] }),
+ ("STM32F0[79].*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }),
+ ("STM32F0.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 1*1024, 0)] }),
+ ("STM32F10[0123].[468B]", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 1*1024, 0)] }),
+ ("STM32F1.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }),
+ ("STM32F2.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 16*1024, 4), (64*1024, 1), ( 128*1024, 0)] }),
+ ("STM32F3.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32F4.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 16*1024, 4), (64*1024, 1), ( 128*1024, 0)] }),
+ ("STM32F7[4567].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 32*1024, 4), (128*1024, 1), ( 256*1024, 0)] }),
+ ("STM32F7.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 16*1024, 4), (64*1024, 1), ( 128*1024, 0)] }),
+ ("STM32G0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32G4[78].*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
+ ("STM32G4.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32H5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
+ ("STM32H7[AB].*", FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[( 8*1024, 0)] }),
+ ("STM32H7.*", FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(128*1024, 0)] }),
+ ("STM32L4[PQRS].*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 8*1024, 0)] }),
+ ("STM32L4.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32L0.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 128, 0)] }),
+ ("STM32L1.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 256, 0)] }),
+ ("STM32L5.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
+ ("STM32U0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32U5[78].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
+ ("STM32U5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 16*1024, 0)] }),
+ ("STM32WBA.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
+ ("STM32WB1.*", FlashInfo{ erase_value: 0x00, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32WB.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
+ ("STM32WL.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+ ("STM32.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
+]);
+
+struct RegexMap {
+ map: &'static [(&'static str, T)],
+}
+
+impl RegexMap {
+ const fn new(map: &'static [(&'static str, T)]) -> Self {
+ Self { map }
}
- pub fn get(&self, die: &str) -> &Memory {
- assert!(die.starts_with("DIE"));
- let device_id = u16::from_str_radix(&die[3..], 16).unwrap();
-
- self.0.get(&device_id).unwrap()
+ fn get(&self, key: &str) -> Option<&T> {
+ for (k, v) in self.map {
+ if Regex::new(&format!("^{k}$")).unwrap().is_match(key) {
+ return Some(v);
+ }
+ }
+ None
}
}
+
+pub fn get(chip: &str) -> Vec {
+ let mems = *MEMS.get(chip).unwrap();
+ let flash = FLASH_INFO.get(chip).unwrap();
+
+ let mut res = Vec::new();
+
+ for mem in mems {
+ if mem.name.starts_with("BANK") {
+ if flash.erase_size.len() == 1 || mem.size <= flash.erase_size[0].0 * flash.erase_size[0].1 {
+ res.push(Memory {
+ name: mem.name.to_string(),
+ address: mem.address,
+ size: mem.size,
+ kind: memory::Kind::Flash,
+ settings: Some(Settings {
+ write_size: flash.write_size,
+ erase_size: flash.erase_size[0].0,
+ erase_value: flash.erase_value,
+ }),
+ });
+ } else {
+ let mut offs = 0;
+ for (i, &(erase_size, count)) in flash.erase_size.iter().enumerate() {
+ if offs >= mem.size {
+ break;
+ }
+ let left = mem.size - offs;
+ let mut size = left;
+ if i != flash.erase_size.len() - 1 {
+ size = size.min(erase_size * count);
+ }
+ res.push(Memory {
+ name: format!("{}_REGION_{}", mem.name, i + 1),
+ address: mem.address + offs,
+ size: size,
+ kind: memory::Kind::Flash,
+ settings: Some(Settings {
+ write_size: flash.write_size,
+ erase_size: erase_size,
+ erase_value: flash.erase_value,
+ }),
+ });
+ offs += size;
+ }
+ }
+ } else {
+ let mut kind = memory::Kind::Ram;
+ if mem.name.contains("FLASH") || mem.name.contains("AXIICP") {
+ kind = memory::Kind::Flash;
+ }
+ res.push(Memory {
+ name: mem.name.to_string(),
+ address: mem.address,
+ size: mem.size,
+ kind,
+ settings: None,
+ });
+ }
+ }
+
+ res.sort_by_key(|m| (m.address, m.name.clone()));
+
+ res
+}
diff --git a/stm32-metapac-gen/res/Cargo.toml b/stm32-metapac-gen/res/Cargo.toml
index 23361c7..b72d6e8 100644
--- a/stm32-metapac-gen/res/Cargo.toml
+++ b/stm32-metapac-gen/res/Cargo.toml
@@ -36,6 +36,7 @@ flavors = [
{ regex_feature = "stm32l1.*", target = "thumbv7m-none-eabi" },
{ regex_feature = "stm32l4.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32l5.*", target = "thumbv8m.main-none-eabihf" },
+ { regex_feature = "stm32u0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32u5.*", target = "thumbv8m.main-none-eabihf" },
{ regex_feature = "stm32wb.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32wl.*", target = "thumbv7em-none-eabi" },
diff --git a/transforms/LPTIM_v2a.yaml b/transforms/LPTIM_v2a.yaml
new file mode 100644
index 0000000..7a53546
--- /dev/null
+++ b/transforms/LPTIM_v2a.yaml
@@ -0,0 +1,8 @@
+transforms:
+
+ - !Rename
+ from: ^LPTIM1$
+ to: LPTIM
+
+ - !DeleteFieldsets
+ from: OR
diff --git a/transforms/LPTIM_v2b.yaml b/transforms/LPTIM_v2b.yaml
new file mode 100644
index 0000000..4a2bba1
--- /dev/null
+++ b/transforms/LPTIM_v2b.yaml
@@ -0,0 +1,57 @@
+transforms:
+
+ - !Rename
+ from: ^LPTIM1$
+ to: LPTIM_Adv
+
+ - !RenameRegisters
+ block: LPTIM_Adv
+ from: (.*)intput
+ to: ${1}input
+
+ - !Rename
+ from: (.*)intput
+ to: ${1}input
+
+ - !MakeBlock
+ blocks: ^LPTIM_Adv$
+ from: ^(.+)_output$
+ to_outer: Output
+ to_block: Output
+ to_inner: ${1}
+
+ - !MakeBlock
+ blocks: ^LPTIM_Adv$
+ from: ^(.+)_input$
+ to_outer: Input
+ to_block: Input
+ to_inner: ${1}
+
+ - !RenameFields
+ fieldset: CCR\d
+ from: CCR\d
+ to: CCR
+
+ - !MergeFieldsets
+ from: CCR\d
+ to: CCR
+
+ - !MakeRegisterArray
+ blocks: LPTIM_Adv
+ from: CCR\d
+ to: CCR
+
+ - !MakeFieldArray
+ fieldsets: CFGR2
+ from: (I[CN])\d(SEL)
+ to: $1$2
+
+ - !MakeFieldArray
+ fieldsets: CCMR\d
+ from: (.*)\d(.*)
+ to: $1$2
+
+ - !MakeFieldArray
+ fieldsets: (ISR|ICR|DIER).*
+ from: (.*)\d(.*)
+ to: $1$2