diff --git a/data/registers/syscfg_l0.yaml b/data/registers/syscfg_l0.yaml new file mode 100644 index 0000000..df80345 --- /dev/null +++ b/data/registers/syscfg_l0.yaml @@ -0,0 +1,118 @@ +--- +block/SYSCFG: + description: System configuration controller + items: + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: CFGR2 + byte_offset: 4 + fieldset: CFGR2 + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR3 + description: CFGR3 + byte_offset: 32 + fieldset: CFGR3 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + - name: UFB + description: User bank swapping + bit_offset: 3 + bit_size: 1 + - name: BOOT_MODE + description: Boot mode selected by the boot pins status bits + bit_offset: 8 + bit_size: 2 +fieldset/CFGR2: + description: CFGR2 + fields: + - name: FWDIS + description: Firewall disable bit + bit_offset: 0 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fm+ drive capability on PB6 enable bit + bit_offset: 8 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fm+ drive capability on PB7 enable bit + bit_offset: 9 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fm+ drive capability on PB8 enable bit + bit_offset: 10 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fm+ drive capability on PB9 enable bit + bit_offset: 11 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fm+ drive capability enable bit + bit_offset: 12 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fm+ drive capability enable bit + bit_offset: 13 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fm+ drive capability enable bit + bit_offset: 14 + bit_size: 1 +fieldset/CFGR3: + description: CFGR3 + fields: + - name: EN_VREFINT + description: VREFINT enable and scaler control for COMP2 enable bit + bit_offset: 0 + bit_size: 1 + - name: SEL_VREF_OUT + description: VREFINT_ADC connection bit + bit_offset: 4 + bit_size: 2 + - name: ENBUF_VREFINT_ADC + description: VREFINT reference for ADC enable bit + bit_offset: 8 + bit_size: 1 + - name: ENBUF_SENSOR_ADC + description: Temperature sensor reference for ADC enable bit + bit_offset: 9 + bit_size: 1 + - name: ENBUF_VREFINT_COMP2 + description: VREFINT reference for COMP2 scaler enable bit + bit_offset: 12 + bit_size: 1 + - name: ENREF_HSI48 + description: VREFINT reference for HSI48 oscillator enable bit + bit_offset: 13 + bit_size: 1 + - name: VREFINT_RDYF + description: VREFINT ready flag + bit_offset: 30 + bit_size: 1 + - name: REF_LOCK + description: SYSCFG_CFGR3 lock bit + bit_offset: 31 + bit_size: 1 +fieldset/EXTICR: + description: external interrupt configuration register 1-4 + fields: + - name: EXTI + description: EXTI configuration bits + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 diff --git a/parse.py b/parse.py index ffc3af3..40ac31c 100644 --- a/parse.py +++ b/parse.py @@ -233,6 +233,7 @@ perimap = [ ('.*:SPI:spi2s1_v3_3', 'spi_v2/SPI'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), + ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'), ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), ]