Ulf Lilleengen
GitHub
commit
a90f756dda
484
data/registers/spi_f1.yaml
Normal file
484
data/registers/spi_f1.yaml
Normal file
@ -0,0 +1,484 @@
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---
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block/SPI:
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description: Serial peripheral interface
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items:
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- byte_offset: 0
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description: control register 1
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fieldset: CR1
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name: CR1
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- byte_offset: 4
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description: control register 2
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fieldset: CR2
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name: CR2
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- byte_offset: 8
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description: status register
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fieldset: SR
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name: SR
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- byte_offset: 12
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description: data register
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fieldset: DR
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name: DR
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- byte_offset: 16
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description: CRC polynomial register
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fieldset: CRCPR
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name: CRCPR
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- access: Read
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byte_offset: 20
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description: RX CRC register
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fieldset: RXCRCR
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name: RXCRCR
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- access: Read
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byte_offset: 24
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description: TX CRC register
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fieldset: TXCRCR
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name: TXCRCR
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- byte_offset: 28
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description: I2S configuration register
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fieldset: I2SCFGR
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name: I2SCFGR
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- byte_offset: 32
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description: I2S prescaler register
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fieldset: I2SPR
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name: I2SPR
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enum/BIDIMODE:
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bit_size: 1
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variants:
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- description: 2-line unidirectional data mode selected
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name: Unidirectional
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value: 0
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- description: 1-line bidirectional data mode selected
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name: Bidirectional
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value: 1
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enum/BIDIOE:
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bit_size: 1
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variants:
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- description: Output disabled (receive-only mode)
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name: OutputDisabled
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value: 0
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- description: Output enabled (transmit-only mode)
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name: OutputEnabled
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value: 1
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enum/BR:
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bit_size: 3
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variants:
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- description: f_PCLK / 2
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name: Div2
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value: 0
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- description: f_PCLK / 4
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name: Div4
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value: 1
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- description: f_PCLK / 8
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name: Div8
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value: 2
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- description: f_PCLK / 16
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name: Div16
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value: 3
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- description: f_PCLK / 32
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name: Div32
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value: 4
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- description: f_PCLK / 64
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name: Div64
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value: 5
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- description: f_PCLK / 128
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name: Div128
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value: 6
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- description: f_PCLK / 256
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name: Div256
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value: 7
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enum/CHLEN:
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bit_size: 1
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variants:
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- description: 16-bit wide
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name: SixteenBit
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value: 0
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- description: 32-bit wide
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name: ThirtyTwoBit
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value: 1
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enum/CHSIDE:
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bit_size: 1
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variants:
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- description: Channel left has to be transmitted or has been received
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name: Left
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value: 0
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- description: Channel right has to be transmitted or has been received
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name: Right
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value: 1
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enum/CKPOL:
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bit_size: 1
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variants:
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- description: I2S clock inactive state is low level
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name: IdleLow
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value: 0
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- description: I2S clock inactive state is high level
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name: IdleHigh
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value: 1
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enum/CPHA:
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bit_size: 1
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variants:
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- description: The first clock transition is the first data capture edge
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name: FirstEdge
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value: 0
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- description: The second clock transition is the first data capture edge
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name: SecondEdge
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value: 1
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enum/CPOL:
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bit_size: 1
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variants:
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- description: CK to 0 when idle
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name: IdleLow
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value: 0
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- description: CK to 1 when idle
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name: IdleHigh
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value: 1
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enum/CRCNEXT:
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bit_size: 1
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variants:
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- description: Next transmit value is from Tx buffer
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name: TxBuffer
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value: 0
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- description: Next transmit value is from Tx CRC register
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name: CRC
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value: 1
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enum/DATLEN:
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bit_size: 2
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variants:
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- description: 16-bit data length
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name: SixteenBit
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value: 0
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- description: 24-bit data length
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name: TwentyFourBit
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value: 1
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- description: 32-bit data length
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name: ThirtyTwoBit
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value: 2
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enum/DFF:
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bit_size: 1
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variants:
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- description: 8-bit data frame format is selected for transmission/reception
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name: EightBit
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value: 0
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- description: 16-bit data frame format is selected for transmission/reception
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name: SixteenBit
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value: 1
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enum/ERRIE:
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bit_size: 1
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variants:
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- description: Error interrupt masked
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name: Masked
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value: 0
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- description: Error interrupt not masked
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name: NotMasked
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value: 1
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enum/ISCFG:
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bit_size: 2
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variants:
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- description: Slave - transmit
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name: SlaveTx
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value: 0
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- description: Slave - receive
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name: SlaveRx
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value: 1
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- description: Master - transmit
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name: MasterTx
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value: 2
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- description: Master - receive
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name: MasterRx
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value: 3
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enum/ISMOD:
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bit_size: 1
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variants:
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- description: SPI mode is selected
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name: SPIMode
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value: 0
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- description: I2S mode is selected
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name: I2SMode
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value: 1
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enum/ISSTD:
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bit_size: 2
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variants:
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- description: I2S Philips standard
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name: Philips
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value: 0
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- description: MSB justified standard
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name: MSB
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value: 1
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- description: LSB justified standard
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name: LSB
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value: 2
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- description: PCM standard
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name: PCM
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value: 3
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enum/LSBFIRST:
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bit_size: 1
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variants:
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- description: Data is transmitted/received with the MSB first
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name: MSBFirst
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value: 0
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- description: Data is transmitted/received with the LSB first
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name: LSBFirst
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value: 1
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enum/MSTR:
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bit_size: 1
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variants:
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- description: Slave configuration
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name: Slave
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value: 0
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- description: Master configuration
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name: Master
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value: 1
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enum/ODD:
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bit_size: 1
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variants:
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- description: Real divider value is I2SDIV * 2
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name: Even
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value: 0
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- description: Real divider value is (I2SDIV * 2) + 1
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name: Odd
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value: 1
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enum/OVRR:
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bit_size: 1
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variants:
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- description: No overrun occurred
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name: NoOverrun
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value: 0
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- description: Overrun occurred
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name: Overrun
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value: 1
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enum/PCMSYNC:
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bit_size: 1
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variants:
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- description: Short frame synchronisation
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name: Short
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value: 0
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- description: Long frame synchronisation
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name: Long
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value: 1
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enum/RXONLY:
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bit_size: 1
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variants:
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- description: Full duplex (Transmit and receive)
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name: FullDuplex
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value: 0
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- description: Output disabled (Receive-only mode)
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name: OutputDisabled
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value: 1
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fieldset/CR1:
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description: control register 1
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Clock phase
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enum: CPHA
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name: CPHA
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- bit_offset: 1
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bit_size: 1
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description: Clock polarity
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enum: CPOL
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name: CPOL
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- bit_offset: 2
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bit_size: 1
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description: Master selection
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enum: MSTR
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name: MSTR
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- bit_offset: 3
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bit_size: 3
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description: Baud rate control
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enum: BR
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name: BR
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- bit_offset: 6
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bit_size: 1
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description: SPI enable
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name: SPE
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- bit_offset: 7
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bit_size: 1
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description: Frame format
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enum: LSBFIRST
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name: LSBFIRST
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- bit_offset: 8
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bit_size: 1
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description: Internal slave select
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name: SSI
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- bit_offset: 9
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bit_size: 1
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description: Software slave management
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name: SSM
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- bit_offset: 10
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bit_size: 1
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description: Receive only
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enum: RXONLY
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name: RXONLY
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- bit_offset: 11
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bit_size: 1
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description: Data frame format
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enum: DFF
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name: DFF
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- bit_offset: 12
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bit_size: 1
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description: CRC transfer next
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enum: CRCNEXT
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name: CRCNEXT
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- bit_offset: 13
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bit_size: 1
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description: Hardware CRC calculation enable
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name: CRCEN
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- bit_offset: 14
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bit_size: 1
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description: Output enable in bidirectional mode
|
||||||
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enum: BIDIOE
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name: BIDIOE
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- bit_offset: 15
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bit_size: 1
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description: Bidirectional data mode enable
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||||||
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enum: BIDIMODE
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||||||
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name: BIDIMODE
|
||||||
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fieldset/CR2:
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||||||
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description: control register 2
|
||||||
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fields:
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- bit_offset: 0
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||||||
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bit_size: 1
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||||||
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description: Rx buffer DMA enable
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||||||
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name: RXDMAEN
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||||||
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- bit_offset: 1
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||||||
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bit_size: 1
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||||||
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description: Tx buffer DMA enable
|
||||||
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name: TXDMAEN
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||||||
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- bit_offset: 2
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||||||
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bit_size: 1
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||||||
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description: SS output enable
|
||||||
|
name: SSOE
|
||||||
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- bit_offset: 5
|
||||||
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bit_size: 1
|
||||||
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description: Error interrupt enable
|
||||||
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enum: ERRIE
|
||||||
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name: ERRIE
|
||||||
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- bit_offset: 6
|
||||||
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bit_size: 1
|
||||||
|
description: RX buffer not empty interrupt enable
|
||||||
|
name: RXNEIE
|
||||||
|
- bit_offset: 7
|
||||||
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bit_size: 1
|
||||||
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description: Tx buffer empty interrupt enable
|
||||||
|
name: TXEIE
|
||||||
|
fieldset/CRCPR:
|
||||||
|
description: CRC polynomial register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
description: CRC polynomial register
|
||||||
|
name: CRCPOLY
|
||||||
|
fieldset/DR:
|
||||||
|
description: data register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
description: Data register
|
||||||
|
name: DR
|
||||||
|
fieldset/I2SCFGR:
|
||||||
|
description: I2S configuration register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: Channel length (number of bits per audio channel)
|
||||||
|
enum: CHLEN
|
||||||
|
name: CHLEN
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 2
|
||||||
|
description: Data length to be transferred
|
||||||
|
enum: DATLEN
|
||||||
|
name: DATLEN
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: Steady state clock polarity
|
||||||
|
enum: CKPOL
|
||||||
|
name: CKPOL
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
description: I2S standard selection
|
||||||
|
enum: ISSTD
|
||||||
|
name: I2SSTD
|
||||||
|
- bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
description: PCM frame synchronization
|
||||||
|
enum: PCMSYNC
|
||||||
|
name: PCMSYNC
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 2
|
||||||
|
description: I2S configuration mode
|
||||||
|
enum: ISCFG
|
||||||
|
name: I2SCFG
|
||||||
|
- bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
description: I2S Enable
|
||||||
|
name: I2SE
|
||||||
|
- bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
description: I2S mode selection
|
||||||
|
enum: ISMOD
|
||||||
|
name: I2SMOD
|
||||||
|
fieldset/I2SPR:
|
||||||
|
description: I2S prescaler register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
description: I2S Linear prescaler
|
||||||
|
name: I2SDIV
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
description: Odd factor for the prescaler
|
||||||
|
enum: ODD
|
||||||
|
name: ODD
|
||||||
|
- bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
description: Master clock output enable
|
||||||
|
name: MCKOE
|
||||||
|
fieldset/RXCRCR:
|
||||||
|
description: RX CRC register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
description: Rx CRC register
|
||||||
|
name: RxCRC
|
||||||
|
fieldset/SR:
|
||||||
|
description: status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: Receive buffer not empty
|
||||||
|
name: RXNE
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: Transmit buffer empty
|
||||||
|
name: TXE
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: Channel side
|
||||||
|
enum: CHSIDE
|
||||||
|
name: CHSIDE
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: Underrun flag
|
||||||
|
name: UDR
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
description: CRC error flag
|
||||||
|
name: CRCERR
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: Mode fault
|
||||||
|
name: MODF
|
||||||
|
- bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
description: Overrun flag
|
||||||
|
enum_read: OVRR
|
||||||
|
name: OVR
|
||||||
|
- bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
description: Busy flag
|
||||||
|
name: BSY
|
||||||
|
fieldset/TXCRCR:
|
||||||
|
description: TX CRC register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
description: Tx CRC register
|
||||||
|
name: TxCRC
|
||||||
1
parse.py
1
parse.py
@ -327,6 +327,7 @@ perimap = [
|
|||||||
('.*:RNG:rng1_v2_0', 'rng_v1/RNG'),
|
('.*:RNG:rng1_v2_0', 'rng_v1/RNG'),
|
||||||
('.*:RNG:rng1_v2_1', 'rng_v1/RNG'),
|
('.*:RNG:rng1_v2_1', 'rng_v1/RNG'),
|
||||||
('.*:RNG:rng1_v3_1', 'rng_v1/RNG'),
|
('.*:RNG:rng1_v3_1', 'rng_v1/RNG'),
|
||||||
|
('.*:SPI:spi2_v1_4', 'spi_f1/SPI'),
|
||||||
('.*:SPI:spi2s1_v2_2', 'spi_v1/SPI'),
|
('.*:SPI:spi2s1_v2_2', 'spi_v1/SPI'),
|
||||||
('.*:SPI:spi2s1_v3_3', 'spi_v2/SPI'),
|
('.*:SPI:spi2s1_v3_3', 'spi_v2/SPI'),
|
||||||
('.*:SPI:spi2s1_v3_5', 'spi_v2/SPI'),
|
('.*:SPI:spi2s1_v3_5', 'spi_v2/SPI'),
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user