diff --git a/data/registers/adc_v1.yaml b/data/registers/adc_v1.yaml new file mode 100644 index 0000000..16f2352 --- /dev/null +++ b/data/registers/adc_v1.yaml @@ -0,0 +1,487 @@ +--- +block/ADC: + description: Analog-to-digital converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR1 + description: configuration register 1 + byte_offset: 12 + fieldset: CFGR1 + - name: CFGR2 + description: configuration register 2 + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR + description: sampling time register + byte_offset: 20 + fieldset: SMPR + - name: TR + description: watchdog threshold register + byte_offset: 32 + fieldset: TR + - name: CHSELR + description: channel selection register + byte_offset: 40 + fieldset: CHSELR + - name: DR + description: data register + byte_offset: 64 + access: Read + fieldset: DR + - name: CCR + description: common configuration register + byte_offset: 776 + fieldset: CCR +fieldset/CCR: + description: common configuration register + fields: + - name: VREFEN + description: Temperature sensor and VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: TSEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: DMAEN + description: Direct memory access enable + bit_offset: 0 + bit_size: 1 + - name: DMACFG + description: Direct memery access configuration + bit_offset: 1 + bit_size: 1 + enum: DMACFG + - name: SCANDIR + description: Scan sequence direction + bit_offset: 2 + bit_size: 1 + enum: SCANDIR + - name: RES + description: Data resolution + bit_offset: 3 + bit_size: 2 + enum: RES + - name: ALIGN + description: Data alignment + bit_offset: 5 + bit_size: 1 + enum: ALIGN + - name: EXTSEL + description: External trigger selection + bit_offset: 6 + bit_size: 3 + enum: EXTSEL + - name: EXTEN + description: External trigger enable and polarity selection + bit_offset: 10 + bit_size: 2 + enum: EXTEN + - name: OVRMOD + description: Overrun management mode + bit_offset: 12 + bit_size: 1 + enum: OVRMOD + - name: CONT + description: Single / continuous conversion mode + bit_offset: 13 + bit_size: 1 + - name: WAIT + description: Wait conversion mode + bit_offset: 14 + bit_size: 1 + - name: AUTOFF + description: Auto-off mode + bit_offset: 15 + bit_size: 1 + - name: DISCEN + description: Discontinuous mode + bit_offset: 16 + bit_size: 1 + - name: AWDSGL + description: Enable the watchdog on a single channel or on all channels + bit_offset: 22 + bit_size: 1 + enum: AWDSGL + - name: AWDEN + description: Analog watchdog enable + bit_offset: 23 + bit_size: 1 + - name: AWDCH + description: Analog watchdog channel selection + bit_offset: 26 + bit_size: 5 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: CKMODE + description: ADC clock mode + bit_offset: 30 + bit_size: 2 + enum: CKMODE +fieldset/CHSELR: + description: channel selection register + fields: + - name: CHSEL x + description: Channel-x selection + bit_offset: 0 + bit_size: 1 + array: + len: 19 + stride: 1 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: ADC enable command + bit_offset: 0 + bit_size: 1 + enum_read: ADENR + enum_write: ADENW + - name: ADDIS + description: ADC disable command + bit_offset: 1 + bit_size: 1 + enum_read: ADDISR + enum_write: ADDISW + - name: ADSTART + description: ADC start conversion command + bit_offset: 2 + bit_size: 1 + enum_read: ADSTARTR + enum_write: ADSTARTW + - name: ADSTP + description: ADC stop conversion command + bit_offset: 4 + bit_size: 1 + enum_read: ADSTPR + enum_write: ADSTPW + - name: ADCAL + description: ADC calibration + bit_offset: 31 + bit_size: 1 + enum_read: ADCALR + enum_write: ADCALW +fieldset/DR: + description: data register + fields: + - name: DATA + description: Converted data + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ADC ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: End of sampling flag interrupt enable + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: End of conversion interrupt enable + bit_offset: 2 + bit_size: 1 + - name: EOSEQIE + description: End of conversion sequence interrupt enable + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: Overrun interrupt enable + bit_offset: 4 + bit_size: 1 + - name: AWDIE + description: Analog watchdog interrupt enable + bit_offset: 7 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ADC ready + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: End of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: End of conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOSEQ + description: End of sequence flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: ADC overrun + bit_offset: 4 + bit_size: 1 + - name: AWD + description: Analog watchdog flag + bit_offset: 7 + bit_size: 1 +fieldset/SMPR: + description: sampling time register + fields: + - name: SMP + description: Sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SMP +fieldset/TR: + description: watchdog threshold register + fields: + - name: LT + description: Analog watchdog lower threshold + bit_offset: 0 + bit_size: 12 + - name: HT + description: Analog watchdog higher threshold + bit_offset: 16 + bit_size: 12 +enum/ADCALR: + bit_size: 1 + variants: + - name: NotCalibrating + description: ADC calibration either not yet performed or completed + value: 0 + - name: Calibrating + description: ADC calibration in progress + value: 1 +enum/ADCALW: + bit_size: 1 + variants: + - name: StartCalibration + description: Start the ADC calibration sequence + value: 1 +enum/ADDISR: + bit_size: 1 + variants: + - name: NotDisabling + description: No disable command active + value: 0 + - name: Disabling + description: ADC disabling + value: 1 +enum/ADDISW: + bit_size: 1 + variants: + - name: Disable + description: Disable the ADC + value: 1 +enum/ADENR: + bit_size: 1 + variants: + - name: Disabled + description: ADC disabled + value: 0 + - name: Enabled + description: ADC enabled + value: 1 +enum/ADENW: + bit_size: 1 + variants: + - name: Enabled + description: Enable the ADC + value: 1 +enum/ADSTARTR: + bit_size: 1 + variants: + - name: NotActive + description: No conversion ongoing + value: 0 + - name: Active + description: ADC operating and may be converting + value: 1 +enum/ADSTARTW: + bit_size: 1 + variants: + - name: StartConversion + description: Start the ADC conversion (may be delayed for hardware triggers) + value: 1 +enum/ADSTPR: + bit_size: 1 + variants: + - name: NotStopping + description: No stop command active + value: 0 + - name: Stopping + description: ADC stopping conversion + value: 1 +enum/ADSTPW: + bit_size: 1 + variants: + - name: StopConversion + description: Stop the active conversion + value: 1 +enum/ALIGN: + bit_size: 1 + variants: + - name: Right + description: Right alignment + value: 0 + - name: Left + description: Left alignment + value: 1 +enum/AWDSGL: + bit_size: 1 + variants: + - name: AllChannels + description: Analog watchdog enabled on all channels + value: 0 + - name: SingleChannel + description: Analog watchdog enabled on a single channel + value: 1 +enum/CKMODE: + bit_size: 2 + variants: + - name: ADCCLK + description: Asynchronous clock mode + value: 0 + - name: PCLK_Div2 + description: Synchronous clock mode (PCLK/2) + value: 1 + - name: PCLK_Div4 + description: Sychronous clock mode (PCLK/4) + value: 2 +enum/DMACFG: + bit_size: 1 + variants: + - name: OneShot + description: DMA one shot mode + value: 0 + - name: Circular + description: DMA circular mode + value: 1 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 3 + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO Event + value: 0 + - name: TIM1_CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 3 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 4 +enum/OVRMOD: + bit_size: 1 + variants: + - name: Preserved + description: ADC_DR register is preserved with the old data when an overrun is detected + value: 0 + - name: Overwritten + description: ADC_DR register is overwritten with the last conversion result when an overrun is detected + value: 1 +enum/RES: + bit_size: 2 + variants: + - name: TwelveBit + description: 12-bit (14 ADCCLK cycles) + value: 0 + - name: TenBit + description: 10-bit (13 ADCCLK cycles) + value: 1 + - name: EightBit + description: 8-bit (11 ADCCLK cycles) + value: 2 + - name: SixBit + description: 6-bit (9 ADCCLK cycles) + value: 3 +enum/SCANDIR: + bit_size: 1 + variants: + - name: Upward + description: Upward scan (from CHSEL0 to CHSEL18) + value: 0 + - name: Backward + description: Backward scan (from CHSEL18 to CHSEL0) + value: 1 +enum/SMP: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 cycles + value: 0 + - name: Cycles7_5 + description: 7.5 cycles + value: 1 + - name: Cycles13_5 + description: 13.5 cycles + value: 2 + - name: Cycles28_5 + description: 28.5 cycles + value: 3 + - name: Cycles41_5 + description: 41.5 cycles + value: 4 + - name: Cycles55_5 + description: 55.5 cycles + value: 5 + - name: Cycles71_5 + description: 71.5 cycles + value: 6 + - name: Cycles239_5 + description: 239.5 cycles + value: 7 +enum/TSEN: + bit_size: 1 + variants: + - name: Disabled + description: Temperature sensor disabled + value: 0 + - name: Enabled + description: Temperature sensor enabled + value: 1 +enum/VBATEN: + bit_size: 1 + variants: + - name: Disabled + description: V_BAT channel disabled + value: 0 + - name: Enabled + description: V_BAT channel enabled + value: 1 diff --git a/data/registers/adc_v4.yaml b/data/registers/adc_v4.yaml new file mode 100644 index 0000000..ceebe11 --- /dev/null +++ b/data/registers/adc_v4.yaml @@ -0,0 +1,968 @@ +--- +block/ADC: + description: Analog to Digital Converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR + description: configuration register 1 + byte_offset: 12 + fieldset: CFGR + - name: CFGR2 + description: configuration register 2 + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR + description: sampling time register 1-2 + byte_offset: 20 + array: + len: 2 + stride: 4 + fieldset: SMPR + - name: PCSEL + description: pre channel selection register + byte_offset: 28 + fieldset: PCSEL + - name: LTR1 + description: analog watchdog 1 threshold register + byte_offset: 32 + fieldset: LTR1 + - name: HTR1 + description: analog watchdog 2 threshold register + byte_offset: 36 + fieldset: HTR1 + - name: SQR1 + description: group regular sequencer ranks register 1 + byte_offset: 48 + fieldset: SQR1 + - name: SQR2 + description: group regular sequencer ranks register 2 + byte_offset: 52 + fieldset: SQR2 + - name: SQR3 + description: group regular sequencer ranks register 3 + byte_offset: 56 + fieldset: SQR3 + - name: SQR4 + description: group regular sequencer ranks register 4 + byte_offset: 60 + fieldset: SQR4 + - name: DR + description: group regular conversion data register + byte_offset: 64 + access: Read + fieldset: DR + - name: JSQR + description: group injected sequencer register + byte_offset: 76 + fieldset: JSQR + - name: OFR + description: offset number 1-4 register + byte_offset: 96 + array: + len: 4 + stride: 4 + fieldset: OFR + - name: JDR + description: group injected sequencer rank 1-4 register + byte_offset: 128 + array: + len: 4 + stride: 4 + access: Read + fieldset: JDR + - name: AWD2CR + description: analog watchdog 2 configuration register + byte_offset: 160 + fieldset: AWD2CR + - name: AWD3CR + description: analog watchdog 3 configuration register + byte_offset: 164 + fieldset: AWD3CR + - name: LTR2 + description: watchdog lower threshold register 2 + byte_offset: 176 + fieldset: LTR2 + - name: HTR2 + description: watchdog higher threshold register 2 + byte_offset: 180 + fieldset: HTR2 + - name: LTR3 + description: watchdog lower threshold register 3 + byte_offset: 184 + fieldset: LTR3 + - name: HTR3 + description: watchdog higher threshold register 3 + byte_offset: 188 + fieldset: HTR3 + - name: DIFSEL + description: channel differential or single-ended mode selection register + byte_offset: 192 + fieldset: DIFSEL + - name: CALFACT + description: calibration factors register + byte_offset: 196 + fieldset: CALFACT + - name: CALFACT2 + description: Calibration Factor register 2 + byte_offset: 200 + fieldset: CALFACT2 +fieldset/AWD2CR: + description: analog watchdog 2 configuration register + fields: + - name: AWD2CH + description: analog watchdog 2 monitored channel selection + bit_offset: 0 + bit_size: 1 + array: + len: 20 + stride: 1 +fieldset/AWD3CR: + description: analog watchdog 3 configuration register + fields: + - name: AWD3CH + description: analog watchdog 3 monitored channel selection + bit_offset: 1 + bit_size: 1 + array: + len: 20 + stride: 1 +fieldset/CALFACT: + description: calibration factors register + fields: + - name: CALFACT_S + description: calibration factor in single-ended mode + bit_offset: 0 + bit_size: 11 + - name: CALFACT_D + description: calibration factor in differential mode + bit_offset: 16 + bit_size: 11 +fieldset/CALFACT2: + description: Calibration Factor register 2 + fields: + - name: LINCALFACT + description: Linearity Calibration Factor + bit_offset: 0 + bit_size: 30 +fieldset/CFGR: + description: configuration register 1 + fields: + - name: DMNGT + description: DMA transfer enable + bit_offset: 0 + bit_size: 2 + enum: DMNGT + - name: RES + description: data resolution + bit_offset: 2 + bit_size: 3 + enum: RES + - name: EXTSEL + description: group regular external trigger source + bit_offset: 5 + bit_size: 5 + enum: EXTSEL + - name: EXTEN + description: group regular external trigger polarity + bit_offset: 10 + bit_size: 2 + enum: EXTEN + - name: OVRMOD + description: group regular overrun configuration + bit_offset: 12 + bit_size: 1 + enum: OVRMOD + - name: CONT + description: group regular continuous conversion mode + bit_offset: 13 + bit_size: 1 + - name: AUTDLY + description: low power auto wait + bit_offset: 14 + bit_size: 1 + - name: DISCEN + description: group regular sequencer discontinuous mode + bit_offset: 16 + bit_size: 1 + - name: DISCNUM + description: group regular sequencer discontinuous number of ranks + bit_offset: 17 + bit_size: 3 + - name: JDISCEN + description: group injected sequencer discontinuous mode + bit_offset: 20 + bit_size: 1 + - name: JQM + description: group injected contexts queue mode + bit_offset: 21 + bit_size: 1 + enum: JQM + - name: AWD1SGL + description: analog watchdog 1 monitoring a single channel or all channels + bit_offset: 22 + bit_size: 1 + enum: AWD1SGL + - name: AWD1EN + description: analog watchdog 1 enable on scope group regular + bit_offset: 23 + bit_size: 1 + - name: JAWD1EN + description: analog watchdog 1 enable on scope group injected + bit_offset: 24 + bit_size: 1 + - name: JAUTO + description: group injected automatic trigger mode + bit_offset: 25 + bit_size: 1 + - name: AWD1CH + description: analog watchdog 1 monitored channel selection + bit_offset: 26 + bit_size: 5 + - name: JQDIS + description: group injected contexts queue disable + bit_offset: 31 + bit_size: 1 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: ROVSE + description: oversampler enable on scope group regular + bit_offset: 0 + bit_size: 1 + - name: JOVSE + description: oversampler enable on scope group injected + bit_offset: 1 + bit_size: 1 + - name: OVSS + description: oversampling shift + bit_offset: 5 + bit_size: 4 + - name: TROVS + description: oversampling discontinuous mode (triggered mode) for group regular + bit_offset: 9 + bit_size: 1 + enum: TROVS + - name: ROVSM + description: Regular Oversampling mode + bit_offset: 10 + bit_size: 1 + enum: ROVSM + - name: RSHIFT1 + description: Right-shift data after Offset 1 correction + bit_offset: 11 + bit_size: 1 + - name: RSHIFT2 + description: Right-shift data after Offset 2 correction + bit_offset: 12 + bit_size: 1 + - name: RSHIFT3 + description: Right-shift data after Offset 3 correction + bit_offset: 13 + bit_size: 1 + - name: RSHIFT4 + description: Right-shift data after Offset 4 correction + bit_offset: 14 + bit_size: 1 + - name: OSVR + description: Oversampling ratio + bit_offset: 16 + bit_size: 10 + - name: LSHIFT + description: Left shift factor + bit_offset: 28 + bit_size: 4 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: enable + bit_offset: 0 + bit_size: 1 + enum_write: ADENW + - name: ADDIS + description: disable + bit_offset: 1 + bit_size: 1 + enum_write: ADDISW + - name: ADSTART + description: group regular conversion start + bit_offset: 2 + bit_size: 1 + - name: JADSTART + description: group injected conversion start + bit_offset: 3 + bit_size: 1 + - name: ADSTP + description: group regular conversion stop + bit_offset: 4 + bit_size: 1 + enum: ADSTP + - name: JADSTP + description: group injected conversion stop + bit_offset: 5 + bit_size: 1 + enum: ADSTP + - name: BOOST + description: Boost mode control + bit_offset: 8 + bit_size: 2 + enum: BOOST + - name: ADCALLIN + description: Linearity calibration + bit_offset: 16 + bit_size: 1 + - name: LINCALRDYW1 + description: Linearity calibration ready Word 1 + bit_offset: 22 + bit_size: 1 + - name: LINCALRDYW2 + description: Linearity calibration ready Word 2 + bit_offset: 23 + bit_size: 1 + - name: LINCALRDYW3 + description: Linearity calibration ready Word 3 + bit_offset: 24 + bit_size: 1 + - name: LINCALRDYW4 + description: Linearity calibration ready Word 4 + bit_offset: 25 + bit_size: 1 + - name: LINCALRDYW5 + description: Linearity calibration ready Word 5 + bit_offset: 26 + bit_size: 1 + - name: LINCALRDYW6 + description: Linearity calibration ready Word 6 + bit_offset: 27 + bit_size: 1 + - name: ADVREGEN + description: voltage regulator enable + bit_offset: 28 + bit_size: 1 + - name: DEEPPWD + description: deep power down enable + bit_offset: 29 + bit_size: 1 + - name: ADCALDIF + description: differential mode for calibration + bit_offset: 30 + bit_size: 1 + enum: ADCALDIF + - name: ADCAL + description: calibration + bit_offset: 31 + bit_size: 1 +fieldset/DIFSEL: + description: channel differential or single-ended mode selection register + fields: + - name: DIFSEL + description: channel differential or single-ended mode for channel + bit_offset: 0 + bit_size: 1 + array: + len: 20 + stride: 1 + enum: DIFSEL +fieldset/DR: + description: group regular conversion data register + fields: + - name: RDATA + description: group regular conversion data + bit_offset: 0 + bit_size: 16 +fieldset/HTR1: + description: analog watchdog 2 threshold register + fields: + - name: HTR1 + description: analog watchdog 2 threshold low + bit_offset: 0 + bit_size: 26 +fieldset/HTR2: + description: watchdog higher threshold register 2 + fields: + - name: HTR2 + description: Analog watchdog 2 higher threshold + bit_offset: 0 + bit_size: 26 +fieldset/HTR3: + description: watchdog higher threshold register 3 + fields: + - name: HTR3 + description: Analog watchdog 3 higher threshold + bit_offset: 0 + bit_size: 26 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ready interrupt + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: group regular end of sampling interrupt + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: group regular end of unitary conversion interrupt + bit_offset: 2 + bit_size: 1 + - name: EOSIE + description: group regular end of sequence conversions interrupt + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: group regular overrun interrupt + bit_offset: 4 + bit_size: 1 + - name: JEOCIE + description: group injected end of unitary conversion interrupt + bit_offset: 5 + bit_size: 1 + - name: JEOSIE + description: group injected end of sequence conversions interrupt + bit_offset: 6 + bit_size: 1 + - name: AWD1IE + description: analog watchdog 1 interrupt + bit_offset: 7 + bit_size: 1 + - name: AWD2IE + description: analog watchdog 2 interrupt + bit_offset: 8 + bit_size: 1 + - name: AWD3IE + description: analog watchdog 3 interrupt + bit_offset: 9 + bit_size: 1 + - name: JQOVFIE + description: group injected contexts queue overflow interrupt + bit_offset: 10 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ready flag + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: group regular end of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: group regular end of unitary conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOS + description: group regular end of sequence conversions flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: group regular overrun flag + bit_offset: 4 + bit_size: 1 + - name: JEOC + description: group injected end of unitary conversion flag + bit_offset: 5 + bit_size: 1 + - name: JEOS + description: group injected end of sequence conversions flag + bit_offset: 6 + bit_size: 1 + - name: AWD1 + description: analog watchdog 1 flag + bit_offset: 7 + bit_size: 1 + - name: AWD2 + description: analog watchdog 2 flag + bit_offset: 8 + bit_size: 1 + - name: AWD3 + description: analog watchdog 3 flag + bit_offset: 9 + bit_size: 1 + - name: JQOVF + description: group injected contexts queue overflow flag + bit_offset: 10 + bit_size: 1 + - name: LDORDY + description: ADC LDO output voltage ready (not always available) + bit_offset: 12 + bit_size: 1 +fieldset/JDR: + description: group injected sequencer rank 1 register + fields: + - name: JDATA + description: group injected sequencer rank 1 conversion data + bit_offset: 0 + bit_size: 32 +fieldset/JSQR: + description: group injected sequencer register + fields: + - name: JL + description: group injected sequencer scan length + bit_offset: 0 + bit_size: 2 + - name: JEXTSEL + description: group injected external trigger source + bit_offset: 2 + bit_size: 5 + enum: JEXTSEL + - name: JEXTEN + description: group injected external trigger polarity + bit_offset: 7 + bit_size: 2 + enum: JEXTEN + - name: JSQ1 + description: group injected sequencer rank 1-4 + bit_offset: 9 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/LTR1: + description: analog watchdog 1 threshold register + fields: + - name: LTR1 + description: analog watchdog 1 threshold low + bit_offset: 0 + bit_size: 26 +fieldset/LTR2: + description: watchdog lower threshold register 2 + fields: + - name: LTR2 + description: Analog watchdog 2 lower threshold + bit_offset: 0 + bit_size: 26 +fieldset/LTR3: + description: watchdog lower threshold register 3 + fields: + - name: LTR3 + description: Analog watchdog 3 lower threshold + bit_offset: 0 + bit_size: 26 +fieldset/OFR: + description: offset number x register + fields: + - name: OFFSET1 + description: offset number x offset level + bit_offset: 0 + bit_size: 26 + - name: OFFSET1_CH + description: offset number x channel selection + bit_offset: 26 + bit_size: 5 + - name: SSATE + description: Signed saturation enable + bit_offset: 31 + bit_size: 1 +fieldset/PCSEL: + description: channel preselection register + fields: + - name: PCSEL + description: "Channel x (VINP[i]) pre selection" + bit_offset: 0 + bit_size: 1 + array: + len: 20 + stride: 1 + enum: PCSEL +fieldset/SMPR: + description: sampling time register n + fields: + - name: SMP + description: channel n * 10 + x sampling time + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SMP +fieldset/SQR1: + description: group regular sequencer ranks register 1 + fields: + - name: L + description: L3 + bit_offset: 0 + bit_size: 4 + - name: SQ + description: group regular sequencer rank 1-4 + bit_offset: 6 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/SQR2: + description: group regular sequencer ranks register 2 + fields: + - name: SQ + description: group regular sequencer rank 5-9 + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR3: + description: group regular sequencer ranks register 3 + fields: + - name: SQ + description: group regular sequencer rank 10-14 + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR4: + description: group regular sequencer ranks register 4 + fields: + - name: SQ + description: group regular sequencer rank 15-16 + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 6 +enum/ADCALDIF: + bit_size: 1 + variants: + - name: SingleEnded + description: Calibration for single-ended mode + value: 0 + - name: Differential + description: Calibration for differential mode + value: 1 +enum/ADDISW: + bit_size: 1 + variants: + - name: Disable + description: Disable conversion and go to power down mode + value: 0 +enum/ADENW: + bit_size: 1 + variants: + - name: Enable + description: Enable ADC + value: 1 +enum/ADSTP: + bit_size: 1 + variants: + - name: Stop + description: Stop conversion of channel + value: 1 +enum/AWD1SGL: + bit_size: 1 + variants: + - name: All + description: Analog watchdog 1 enabled on all channels + value: 0 + - name: Single + description: Analog watchdog 1 enabled on single channel selected in AWD1CH + value: 1 +enum/BOOST: + bit_size: 2 + variants: + - name: LT6_25 + description: Boost mode used when clock ≤ 6.25 MHz + value: 0 + - name: LT12_5 + description: Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz + value: 1 + - name: LT25 + description: Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz + value: 2 + - name: LT50 + description: Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz + value: 3 +enum/DIFSEL: + bit_size: 1 + variants: + - name: SingleEnded + description: Input channel is configured in single-ended mode + value: 0 + - name: Differential + description: Input channel is configured in differential mode + value: 1 +enum/DMNGT: + bit_size: 2 + variants: + - name: DR + description: Store output data in DR only + value: 0 + - name: DMA_OneShot + description: DMA One Shot Mode selected + value: 1 + - name: DFSDM + description: DFSDM mode selected + value: 2 + - name: DMA_Circular + description: DMA Circular Mode selected + value: 3 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 5 + variants: + - name: TIM1_CC1 + description: Timer 1 CC1 event + value: 0 + - name: TIM1_CC2 + description: Timer 1 CC2 event + value: 1 + - name: TIM1_CC3 + description: Timer 1 CC3 event + value: 2 + - name: TIM2_CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 4 + - name: TIM4_CC4 + description: Timer 4 CC4 event + value: 5 + - name: EXTI11 + description: EXTI line 11 + value: 6 + - name: TIM8_TRGO + description: Timer 8 TRGO event + value: 7 + - name: TIM8_TRGO2 + description: Timer 8 TRGO2 event + value: 8 + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 9 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 10 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 11 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 12 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 13 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 14 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 15 + - name: HRTIM1_ADCTRG1 + description: HRTIM1_ADCTRG1 event + value: 16 + - name: HRTIM1_ADCTRG3 + description: HRTIM1_ADCTRG3 event + value: 17 + - name: LPTIM1_OUT + description: LPTIM1_OUT event + value: 18 + - name: LPTIM2_OUT + description: LPTIM2_OUT event + value: 19 + - name: LPTIM3_OUT + description: LPTIM3_OUT event + value: 20 +enum/JEXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/JEXTSEL: + bit_size: 5 + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 0 + - name: TIM1_CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2_CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 4 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 5 + - name: EXTI15 + description: EXTI line 15 + value: 6 + - name: TIM8_CC4 + description: Timer 8 CC4 event + value: 7 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 8 + - name: TIM8_TRGO + description: Timer 8 TRGO event + value: 9 + - name: TIM8_TRGO2 + description: Timer 8 TRGO2 event + value: 10 + - name: TIM3_CC3 + description: Timer 3 CC3 event + value: 11 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 12 + - name: TIM3_CC1 + description: Timer 3 CC1 event + value: 13 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 14 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 15 + - name: HRTIM1_ADCTRG2 + description: HRTIM1_ADCTRG2 event + value: 16 + - name: HRTIM1_ADCTRG4 + description: HRTIM1_ADCTRG4 event + value: 17 + - name: LPTIM1_OUT + description: LPTIM1_OUT event + value: 18 + - name: LPTIM2_OUT + description: LPTIM2_OUT event + value: 19 + - name: LPTIM3_OUT + description: LPTIM3_OUT event + value: 20 +enum/JQM: + bit_size: 1 + variants: + - name: Mode0 + description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR" + value: 0 + - name: Mode1 + description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence" + value: 1 +enum/OVRMOD: + bit_size: 1 + variants: + - name: Preserve + description: Preserve DR register when an overrun is detected + value: 0 + - name: Overwrite + description: Overwrite DR register when an overrun is detected + value: 1 +enum/PCSEL: + bit_size: 20 + variants: + - name: NotPreselected + description: Input channel x is not pre-selected + value: 0 + - name: Preselected + description: Pre-select input channel x + value: 1 +enum/RES: + bit_size: 3 + variants: + - name: SixteenBit + description: 16-bit resolution + value: 0 + - name: FourteenBit + description: 14-bit resolution in legacy mode (not optimized power consumption) + value: 1 + - name: TwelveBit + description: 12-bit resolution in legacy mode (not optimized power consumption) + value: 2 + - name: TenBit + description: 10-bit resolution + value: 3 + - name: FourteenBitV + description: 14-bit resolution + value: 5 + - name: TwelveBitV + description: 12-bit resolution + value: 6 + - name: EightBit + description: 8-bit resolution + value: 7 +enum/ROVSM: + bit_size: 1 + variants: + - name: Continued + description: Oversampling is temporary stopped and continued after injection sequence + value: 0 + - name: Resumed + description: Oversampling is aborted and resumed from start after injection sequence + value: 1 +enum/SMP: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 clock cycles + value: 0 + - name: Cycles2_5 + description: 2.5 clock cycles + value: 1 + - name: Cycles8_5 + description: 8.5 clock cycles + value: 2 + - name: Cycles16_5 + description: 16.5 clock cycles + value: 3 + - name: Cycles32_5 + description: 32.5 clock cycles + value: 4 + - name: Cycles64_5 + description: 64.5 clock cycles + value: 5 + - name: Cycles387_5 + description: 387.5 clock cycles + value: 6 + - name: Cycles810_5 + description: 810.5 clock cycles + value: 7 +enum/TROVS: + bit_size: 1 + variants: + - name: Automatic + description: All oversampled conversions for a channel are run following a trigger + value: 0 + - name: Triggered + description: Each oversampled conversion for a channel needs a new trigger + value: 1 diff --git a/data/registers/adccommon_v4.yaml b/data/registers/adccommon_v4.yaml new file mode 100644 index 0000000..1c50f5f --- /dev/null +++ b/data/registers/adccommon_v4.yaml @@ -0,0 +1,367 @@ +--- +block/ADC_COMMON: + description: Analog-to-Digital Converter + items: + - name: CSR + description: ADC Common status register + byte_offset: 0 + access: Read + fieldset: CSR + - name: CCR + description: ADC common control register + byte_offset: 8 + fieldset: CCR + - name: CDR + description: ADC common regular data register for dual and triple modes + byte_offset: 12 + access: Read + fieldset: CDR + - name: CDR2 + description: ADC x common regular data register for 32-bit dual mode + byte_offset: 16 + access: Read + fieldset: CDR2 +fieldset/CCR: + description: ADC common control register + fields: + - name: DUAL + description: Dual ADC mode selection + bit_offset: 0 + bit_size: 5 + enum: DUAL + - name: DELAY + description: Delay between 2 sampling phases + bit_offset: 8 + bit_size: 4 + - name: DAMDF + description: Dual ADC Mode Data Format + bit_offset: 14 + bit_size: 2 + enum: DAMDF + - name: CKMODE + description: ADC clock mode + bit_offset: 16 + bit_size: 2 + enum: CKMODE + - name: PRESC + description: ADC prescaler + bit_offset: 18 + bit_size: 4 + enum: PRESC + - name: VREFEN + description: VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: VSENSEEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 +fieldset/CDR: + description: ADC common regular data register for dual and triple modes + fields: + - name: RDATA_MST + description: Regular data of the master ADC + bit_offset: 0 + bit_size: 16 + - name: RDATA_SLV + description: Regular data of the slave ADC + bit_offset: 16 + bit_size: 16 +fieldset/CDR2: + description: ADC x common regular data register for 32-bit dual mode + fields: + - name: RDATA_ALT + description: Regular data of the master/slave alternated ADCs + bit_offset: 0 + bit_size: 32 +fieldset/CSR: + description: ADC Common status register + fields: + - name: ADRDY_MST + description: Master ADC ready + bit_offset: 0 + bit_size: 1 + enum: ADRDY_MST + - name: EOSMP_MST + description: End of Sampling phase flag of the master ADC + bit_offset: 1 + bit_size: 1 + enum: EOSMP_MST + - name: EOC_MST + description: End of regular conversion of the master ADC + bit_offset: 2 + bit_size: 1 + enum: EOC_MST + - name: EOS_MST + description: End of regular sequence flag of the master ADC + bit_offset: 3 + bit_size: 1 + enum: EOS_MST + - name: OVR_MST + description: Overrun flag of the master ADC + bit_offset: 4 + bit_size: 1 + enum: OVR_MST + - name: JEOC_MST + description: End of injected conversion flag of the master ADC + bit_offset: 5 + bit_size: 1 + enum: JEOC_MST + - name: JEOS_MST + description: End of injected sequence flag of the master ADC + bit_offset: 6 + bit_size: 1 + enum: JEOS_MST + - name: AWD1_MST + description: Analog watchdog 1 flag of the master ADC + bit_offset: 7 + bit_size: 1 + enum: AWD1_MST + - name: AWD2_MST + description: Analog watchdog 2 flag of the master ADC + bit_offset: 8 + bit_size: 1 + enum: AWD1_MST + - name: AWD3_MST + description: Analog watchdog 3 flag of the master ADC + bit_offset: 9 + bit_size: 1 + enum: AWD1_MST + - name: JQOVF_MST + description: Injected Context Queue Overflow flag of the master ADC + bit_offset: 10 + bit_size: 1 + enum: JQOVF_MST + - name: ADRDY_SLV + description: Slave ADC ready + bit_offset: 16 + bit_size: 1 + enum: ADRDY_MST + - name: EOSMP_SLV + description: End of Sampling phase flag of the slave ADC + bit_offset: 17 + bit_size: 1 + enum: EOSMP_MST + - name: EOC_SLV + description: End of regular conversion of the slave ADC + bit_offset: 18 + bit_size: 1 + enum: EOC_MST + - name: EOS_SLV + description: End of regular sequence flag of the slave ADC + bit_offset: 19 + bit_size: 1 + enum: EOS_MST + - name: OVR_SLV + description: Overrun flag of the slave ADC + bit_offset: 20 + bit_size: 1 + enum: OVR_MST + - name: JEOC_SLV + description: End of injected conversion flag of the slave ADC + bit_offset: 21 + bit_size: 1 + enum: JEOC_MST + - name: JEOS_SLV + description: End of injected sequence flag of the slave ADC + bit_offset: 22 + bit_size: 1 + enum: JEOS_MST + - name: AWD1_SLV + description: Analog watchdog 1 flag of the slave ADC + bit_offset: 23 + bit_size: 1 + enum: AWD1_MST + - name: AWD2_SLV + description: Analog watchdog 2 flag of the slave ADC + bit_offset: 24 + bit_size: 1 + enum: AWD1_MST + - name: AWD3_SLV + description: Analog watchdog 3 flag of the slave ADC + bit_offset: 25 + bit_size: 1 + enum: AWD1_MST + - name: JQOVF_SLV + description: Injected Context Queue Overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 + enum: JQOVF_MST +enum/ADRDY_MST: + bit_size: 1 + variants: + - name: NotReady + description: ADC is not ready to start conversion + value: 0 + - name: Ready + description: ADC is ready to start conversion + value: 1 +enum/AWD1_MST: + bit_size: 1 + variants: + - name: NoEvent + description: No analog watchdog event occurred + value: 0 + - name: Event + description: Analog watchdog event occurred + value: 1 +enum/CKMODE: + bit_size: 2 + variants: + - name: Asynchronous + description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock + value: 0 + - name: SyncDiv1 + description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck + value: 1 + - name: SyncDiv2 + description: Use AHB clock rcc_hclk3 divided by 2 + value: 2 + - name: SyncDiv4 + description: Use AHB clock rcc_hclk3 divided by 4 + value: 3 +enum/DAMDF: + bit_size: 2 + variants: + - name: NoPack + description: "Without data packing, CDR/CDR2 not used" + value: 0 + - name: Format32to10 + description: CDR formatted for 32-bit down to 10-bit resolution + value: 2 + - name: Format8 + description: CDR formatted for 8-bit resolution + value: 3 +enum/DUAL: + bit_size: 5 + variants: + - name: Independent + description: Independent mode + value: 0 + - name: DualRJ + description: "Dual, combined regular simultaneous + injected simultaneous mode" + value: 1 + - name: DualRA + description: "Dual, combined regular simultaneous + alternate trigger mode" + value: 2 + - name: DualIJ + description: "Dual, combined interleaved mode + injected simultaneous mode" + value: 3 + - name: DualJ + description: "Dual, injected simultaneous mode only" + value: 5 + - name: DualR + description: "Dual, regular simultaneous mode only" + value: 6 + - name: DualI + description: "Dual, interleaved mode only" + value: 7 + - name: DualA + description: "Dual, alternate trigger mode only" + value: 9 +enum/EOC_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Regular conversion is not complete + value: 0 + - name: Complete + description: Regular conversion complete + value: 1 +enum/EOSMP_MST: + bit_size: 1 + variants: + - name: NotEnded + description: End of sampling phase no yet reached + value: 0 + - name: Ended + description: End of sampling phase reached + value: 1 +enum/EOS_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Regular sequence is not complete + value: 0 + - name: Complete + description: Regular sequence complete + value: 1 +enum/JEOC_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Injected conversion is not complete + value: 0 + - name: Complete + description: Injected conversion complete + value: 1 +enum/JEOS_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Injected sequence is not complete + value: 0 + - name: Complete + description: Injected sequence complete + value: 1 +enum/JQOVF_MST: + bit_size: 1 + variants: + - name: NoOverflow + description: No injected context queue overflow has occurred + value: 0 + - name: Overflow + description: Injected context queue overflow has occurred + value: 1 +enum/OVR_MST: + bit_size: 1 + variants: + - name: NoOverrun + description: No overrun occurred + value: 0 + - name: Overrun + description: Overrun occurred + value: 1 +enum/PRESC: + bit_size: 4 + variants: + - name: Div1 + description: adc_ker_ck_input not divided + value: 0 + - name: Div2 + description: adc_ker_ck_input divided by 2 + value: 1 + - name: Div4 + description: adc_ker_ck_input divided by 4 + value: 2 + - name: Div6 + description: adc_ker_ck_input divided by 6 + value: 3 + - name: Div8 + description: adc_ker_ck_input divided by 8 + value: 4 + - name: Div10 + description: adc_ker_ck_input divided by 10 + value: 5 + - name: Div12 + description: adc_ker_ck_input divided by 12 + value: 6 + - name: Div16 + description: adc_ker_ck_input divided by 16 + value: 7 + - name: Div32 + description: adc_ker_ck_input divided by 32 + value: 8 + - name: Div64 + description: adc_ker_ck_input divided by 64 + value: 9 + - name: Div128 + description: adc_ker_ck_input divided by 128 + value: 10 + - name: Div256 + description: adc_ker_ck_input divided by 256 + value: 11 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 57d19eb..972052b 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -119,17 +119,23 @@ perimap = [ ('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1U5', ('i2c', 'v2', 'I2C')), + ('.*:DAC:dacif_v1_1', ('dac', 'v1', 'DAC')), ('.*:DAC:dacif_v2_0', ('dac', 'v2', 'DAC')), ('.*:DAC:dacif_v3_0', ('dac', 'v2', 'DAC')), + ('.*:ADC:aditf_v2_5F1', ('adc', 'f1', 'ADC')), + ('.*:ADC:aditf4_v1_1', ('adc', 'v1', 'ADC')), ('.*:ADC:aditf2_v1_1', ('adc', 'v2', 'ADC')), ('.*:ADC:aditf5_v2_0', ('adc', 'v3', 'ADC')), + ('.*:ADC:aditf5_v3_0', ('adc', 'v4', 'ADC')), ('STM32G0.*:ADC:.*', ('adc', 'g0', 'ADC')), ('STM32G0.*:ADC_COMMON:.*', ('adccommon', 'v3', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf2_v1_1', ('adccommon', 'v2', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf5_v2_0', ('adccommon', 'v3', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf4_v3_0_WL', ('adccommon', 'v3', 'ADC_COMMON')), + ('STM32H7.*:ADC_COMMON:.*', ('adccommon', 'v4', 'ADC_COMMON')), + ('.*:DCMI:.*', ('dcmi', 'v1', 'DCMI')), ('STM32F0.*:SYSCFG:.*', ('syscfg', 'f0', 'SYSCFG')), ('STM32F2.*:SYSCFG:.*', ('syscfg', 'f2', 'SYSCFG')),