From 697ff5ff6e660416593d6c9ed4766cad0b85c033 Mon Sep 17 00:00:00 2001 From: Daehyeok Mun Date: Sat, 19 Aug 2023 18:41:38 -0700 Subject: [PATCH] Support STM32G4 ADC peripheral --- data/registers/rcc_g4.yaml | 14 ++++++++++++++ stm32-data-gen/src/chips.rs | 2 ++ 2 files changed, 16 insertions(+) diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index a254fdc..f649702 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1027,9 +1027,11 @@ fieldset/CCIPR: description: ADCs clock source selection bit_offset: 28 bit_size: 2 + enum: ADCSEL - name: ADC345SEL description: ADC3/4/5 clock source selection bit_offset: 30 + enum: ADCSEL bit_size: 2 fieldset/CCIPR2: description: Peripherals independent clock configuration register @@ -1333,6 +1335,18 @@ fieldset/PLLCFGR: description: Main PLL division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 +enum/ADCSEL: + bit_size: 2 + variants: + - name: NOCLK + description: No clock selected + value: 0 + - name: PLLP + description: PLL 'P' clock selected as ADC clock + value: 1 + - name: SYSCLK + description: System clock selected as ADC clock + value: 2 enum/CLK48SEL: bit_size: 2 variants: diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 9c8795c..07fa785 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -180,6 +180,8 @@ impl PeriMatcher { (".*:ADC:aditf5_v3_1", ("adc", "v4", "ADC")), ("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), + ("STM32G4.*:ADC:.*", ("adc", "v4", "ADC")), + ("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), (".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")),