From 68fa1b173aa0dc0277e773a92fa8fc0f7151da40 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 16:45:53 +0800 Subject: [PATCH 1/8] extract --- data/registers/fmc_v4.yaml | 986 +++++++++++++++++++++++++++++++++++++ 1 file changed, 986 insertions(+) create mode 100644 data/registers/fmc_v4.yaml diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml new file mode 100644 index 0000000..c511af0 --- /dev/null +++ b/data/registers/fmc_v4.yaml @@ -0,0 +1,986 @@ +block/FMC: + description: Flexible memory controller. + items: + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register for bank 1. + byte_offset: 0 + fieldset: BCR1 + - name: BTR1 + description: SRAM/NOR-Flash chip-select timing register for bank 1. + byte_offset: 4 + fieldset: BTR1 + - name: BCR2 + description: SRAM/NOR-Flash chip-select control register for bank 2. + byte_offset: 8 + fieldset: BCR2 + - name: BTR2 + description: SRAM/NOR-Flash chip-select timing register for bank 2. + byte_offset: 12 + fieldset: BTR2 + - name: BCR3 + description: SRAM/NOR-Flash chip-select control register for bank 3. + byte_offset: 16 + fieldset: BCR3 + - name: BTR3 + description: SRAM/NOR-Flash chip-select timing register for bank 3. + byte_offset: 20 + fieldset: BTR3 + - name: BCR4 + description: SRAM/NOR-Flash chip-select control register for bank 4. + byte_offset: 24 + fieldset: BCR4 + - name: BTR4 + description: SRAM/NOR-Flash chip-select timing register for bank 4. + byte_offset: 28 + fieldset: BTR4 + - name: PCSCNTR + description: PSRAM chip select counter register. + byte_offset: 32 + fieldset: PCSCNTR + - name: PCR + description: NAND Flash control registers. + byte_offset: 128 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register. + byte_offset: 132 + fieldset: SR + - name: PMEM + description: Common memory space timing register. + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register. + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: ECC result registers. + byte_offset: 148 + fieldset: ECCR + - name: BWTR1 + description: SRAM/NOR-Flash write timing registers 1. + byte_offset: 260 + fieldset: BWTR1 + - name: BWTR2 + description: SRAM/NOR-Flash write timing registers 2. + byte_offset: 268 + fieldset: BWTR2 + - name: BWTR3 + description: SRAM/NOR-Flash write timing registers 3. + byte_offset: 276 + fieldset: BWTR3 + - name: BWTR4 + description: SRAM/NOR-Flash write timing registers 4. + byte_offset: 284 + fieldset: BWTR4 + - name: SDCR1 + description: SDRAM control registers 1. + byte_offset: 320 + fieldset: SDCR1 + - name: SDCR2 + description: SDRAM control registers 2. + byte_offset: 324 + fieldset: SDCR2 + - name: SDTR1 + description: SDRAM timing registers 1. + byte_offset: 328 + fieldset: SDTR1 + - name: SDTR2 + description: SDRAM timing registers 2. + byte_offset: 332 + fieldset: SDTR2 + - name: SDCMR + description: SDRAM Command Mode register. + byte_offset: 336 + fieldset: SDCMR + - name: SDRTR + description: SDRAM refresh timer register. + byte_offset: 340 + fieldset: SDRTR + - name: SDSR + description: SDRAM status register. + byte_offset: 344 + fieldset: SDSR +fieldset/BCR1: + description: SRAM/NOR-Flash chip-select control register for bank 1. + fields: + - name: MBKEN + description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type Defines the type of external memory attached to the corresponding memory bank. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width Defines the external memory device width, valid for all type of memories. + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable Enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + bit_offset: 11 + bit_size: 1 + - name: WREN + description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 31 + bit_size: 1 +fieldset/BCR2: + description: SRAM/NOR-Flash chip-select control register for bank 2. + fields: + - name: MBKEN + description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type Defines the type of external memory attached to the corresponding memory bank. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width Defines the external memory device width, valid for all type of memories. + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable Enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + bit_offset: 11 + bit_size: 1 + - name: WREN + description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 31 + bit_size: 1 +fieldset/BCR3: + description: SRAM/NOR-Flash chip-select control register for bank 3. + fields: + - name: MBKEN + description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type Defines the type of external memory attached to the corresponding memory bank. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width Defines the external memory device width, valid for all type of memories. + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable Enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + bit_offset: 11 + bit_size: 1 + - name: WREN + description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 31 + bit_size: 1 +fieldset/BCR4: + description: SRAM/NOR-Flash chip-select control register for bank 4. + fields: + - name: MBKEN + description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type Defines the type of external memory attached to the corresponding memory bank. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width Defines the external memory device width, valid for all type of memories. + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable Enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + bit_offset: 11 + bit_size: 1 + - name: WREN + description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 31 + bit_size: 1 +fieldset/BTR1: + description: SRAM/NOR-Flash chip-select timing register for bank 1. + fields: + - name: ADDSET + description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' + bit_offset: 30 + bit_size: 2 +fieldset/BTR2: + description: SRAM/NOR-Flash chip-select timing register for bank 2. + fields: + - name: ADDSET + description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' + bit_offset: 30 + bit_size: 2 +fieldset/BTR3: + description: SRAM/NOR-Flash chip-select timing register for bank 3. + fields: + - name: ADDSET + description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' + bit_offset: 30 + bit_size: 2 +fieldset/BTR4: + description: SRAM/NOR-Flash chip-select timing register for bank 4. + fields: + - name: ADDSET + description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' + bit_offset: 30 + bit_size: 2 +fieldset/BWTR1: + description: SRAM/NOR-Flash write timing registers 1. + fields: + - name: ADDSET + description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. + bit_offset: 30 + bit_size: 2 +fieldset/BWTR2: + description: SRAM/NOR-Flash write timing registers 2. + fields: + - name: ADDSET + description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. + bit_offset: 30 + bit_size: 2 +fieldset/BWTR3: + description: SRAM/NOR-Flash write timing registers 3. + fields: + - name: ADDSET + description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. + bit_offset: 30 + bit_size: 2 +fieldset/BWTR4: + description: SRAM/NOR-Flash write timing registers 4. + fields: + - name: ADDSET + description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 + - name: DATAHLD + description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. + bit_offset: 30 + bit_size: 2 +fieldset/ECCR: + description: ECC result registers. + fields: + - name: ECC + description: ECC result This field contains the value computed by the ECC computation logic. Table 99 describes the contents of these bitfields. + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register. + fields: + - name: ATTSET + description: Attribute memory setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:. + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:. + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:. + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:. + bit_offset: 24 + bit_size: 8 +fieldset/PCR: + description: NAND Flash control registers. + fields: + - name: PWAITEN + description: Wait feature enable bit Enables the Wait feature for the NAND Flash memory bank:. + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type Defines the type of device attached to the corresponding memory bank:. + bit_offset: 3 + bit_size: 1 + - name: PWID + description: Data bus width Defines the external memory device width. + bit_offset: 4 + bit_size: 2 + - name: ECCEN + description: ECC computation logic enable bit. + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: 'CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.' + bit_offset: 9 + bit_size: 4 + - name: TAR + description: 'ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.' + bit_offset: 13 + bit_size: 3 + - name: TAR3 + description: 'ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.' + bit_offset: 16 + bit_size: 1 + - name: ECCPS + description: ECC page size Defines the page size for the extended ECC:. + bit_offset: 17 + bit_size: 3 +fieldset/PCSCNTR: + description: PSRAM chip select counter register. + fields: + - name: CSCOUNT + description: Chip select counter. These bits are written by software to define the maximum chip select low pulse duration. It is expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses. The counter is disabled if the programmed value is 0. + bit_offset: 0 + bit_size: 16 + - name: CNTB1EN + description: Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. + bit_offset: 16 + bit_size: 1 + - name: CNTB2EN + description: Counter Bank 2 enable This bit enables the chip select counter for PSRAM/NOR Bank 2. + bit_offset: 17 + bit_size: 1 + - name: CNTB3EN + description: Counter Bank 3 enable This bit enables the chip select counter for PSRAM/NOR Bank 3. + bit_offset: 18 + bit_size: 1 + - name: CNTB4EN + description: Counter Bank 4 enable This bit enables the chip select counter for PSRAM/NOR Bank 4. + bit_offset: 19 + bit_size: 1 +fieldset/PMEM: + description: Common memory space timing register. + fields: + - name: MEMSET + description: Common memory x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:. + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:. + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:. + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions:. + bit_offset: 24 + bit_size: 8 +fieldset/SDCMR: + description: SDRAM Command Mode register. + fields: + - name: MODE + description: 'Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the the unused bank must be kept to 0.' + bit_offset: 0 + bit_size: 3 + - name: CTB2 + description: Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. .... + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. + bit_offset: 9 + bit_size: 13 +fieldset/SDCR1: + description: SDRAM control registers 1. + fields: + - name: NC + description: Number of column address bits These bits define the number of bits of a column address. + bit_offset: 0 + bit_size: 2 + - name: NR + description: Number of row address bits These bits define the number of bits of a row address. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width. These bits define the memory device width. + bit_offset: 4 + bit_size: 2 + - name: NB + description: Number of internal banks This bit sets the number of internal banks. + bit_offset: 6 + bit_size: 1 + - name: CAS + description: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles. + bit_offset: 7 + bit_size: 2 + - name: WP + description: Write protection This bit enables write mode access to the SDRAM bank. + bit_offset: 9 + bit_size: 1 + - name: SDCLK + description: 'SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.' + bit_offset: 10 + bit_size: 2 + - name: RBURST + description: 'Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.' + bit_offset: 12 + bit_size: 1 + - name: RPIPE + description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.' + bit_offset: 13 + bit_size: 2 +fieldset/SDCR2: + description: SDRAM control registers 2. + fields: + - name: NC + description: Number of column address bits These bits define the number of bits of a column address. + bit_offset: 0 + bit_size: 2 + - name: NR + description: Number of row address bits These bits define the number of bits of a row address. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width. These bits define the memory device width. + bit_offset: 4 + bit_size: 2 + - name: NB + description: Number of internal banks This bit sets the number of internal banks. + bit_offset: 6 + bit_size: 1 + - name: CAS + description: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles. + bit_offset: 7 + bit_size: 2 + - name: WP + description: Write protection This bit enables write mode access to the SDRAM bank. + bit_offset: 9 + bit_size: 1 + - name: SDCLK + description: 'SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.' + bit_offset: 10 + bit_size: 2 + - name: RBURST + description: 'Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.' + bit_offset: 12 + bit_size: 1 + - name: RPIPE + description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.' + bit_offset: 13 + bit_size: 2 +fieldset/SDRTR: + description: SDRAM refresh timer register. + fields: + - name: CRE + description: Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. + bit_offset: 0 + bit_size: 1 + - name: COUNT + description: Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20. + bit_offset: 1 + bit_size: 13 + - name: REIE + description: RES Interrupt Enable. + bit_offset: 14 + bit_size: 1 +fieldset/SDSR: + description: SDRAM status register. + fields: + - name: RE + description: Refresh error flag An interrupt is generated if REIE = 1 and RE = 1. + bit_offset: 0 + bit_size: 1 + - name: MODES1 + description: Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. + bit_offset: 1 + bit_size: 2 + - name: MODES2 + description: Status Mode for Bank 2 This bit defines the Status Mode of SDRAM Bank 2. + bit_offset: 3 + bit_size: 2 + - name: BUSY + description: Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request. + bit_offset: 5 + bit_size: 1 +fieldset/SDTR1: + description: SDRAM timing registers 1. + fields: + - name: TMRD + description: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: 'Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.' + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... + bit_offset: 8 + bit_size: 4 + - name: TRC + description: 'Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.' + bit_offset: 12 + bit_size: 4 + - name: TWR + description: 'Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.' + bit_offset: 16 + bit_size: 4 + - name: TRP + description: 'Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are don’t care.' + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... + bit_offset: 24 + bit_size: 4 +fieldset/SDTR2: + description: SDRAM timing registers 2. + fields: + - name: TMRD + description: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: 'Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.' + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... + bit_offset: 8 + bit_size: 4 + - name: TRC + description: 'Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.' + bit_offset: 12 + bit_size: 4 + - name: TWR + description: 'Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.' + bit_offset: 16 + bit_size: 4 + - name: TRP + description: 'Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are don’t care.' + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... + bit_offset: 24 + bit_size: 4 +fieldset/SR: + description: FIFO status and interrupt register. + fields: + - name: IRS + description: 'Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set.' + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status The flag is set by hardware and reset by software. + bit_offset: 1 + bit_size: 1 + - name: IFS + description: 'Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set.' + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit. + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit. + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit. + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty Read-only bit that provides the status of the FIFO. + bit_offset: 6 + bit_size: 1 From 45f5429068c43610b03f98d8566bb78a65fba2a1 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 16:46:36 +0800 Subject: [PATCH 2/8] apply transform --- data/registers/fmc_v4.yaml | 647 ++++++------------------------------- transforms/FMC.yaml | 21 ++ 2 files changed, 125 insertions(+), 543 deletions(-) create mode 100644 transforms/FMC.yaml diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml index c511af0..991fe7c 100644 --- a/data/registers/fmc_v4.yaml +++ b/data/registers/fmc_v4.yaml @@ -5,34 +5,20 @@ block/FMC: description: SRAM/NOR-Flash chip-select control register for bank 1. byte_offset: 0 fieldset: BCR1 - - name: BTR1 + - name: BTR description: SRAM/NOR-Flash chip-select timing register for bank 1. + array: + len: 4 + stride: 8 byte_offset: 4 - fieldset: BTR1 - - name: BCR2 + fieldset: BTR + - name: BCR description: SRAM/NOR-Flash chip-select control register for bank 2. + array: + len: 3 + stride: 8 byte_offset: 8 - fieldset: BCR2 - - name: BTR2 - description: SRAM/NOR-Flash chip-select timing register for bank 2. - byte_offset: 12 - fieldset: BTR2 - - name: BCR3 - description: SRAM/NOR-Flash chip-select control register for bank 3. - byte_offset: 16 - fieldset: BCR3 - - name: BTR3 - description: SRAM/NOR-Flash chip-select timing register for bank 3. - byte_offset: 20 - fieldset: BTR3 - - name: BCR4 - description: SRAM/NOR-Flash chip-select control register for bank 4. - byte_offset: 24 - fieldset: BCR4 - - name: BTR4 - description: SRAM/NOR-Flash chip-select timing register for bank 4. - byte_offset: 28 - fieldset: BTR4 + fieldset: BCR - name: PCSCNTR description: PSRAM chip select counter register. byte_offset: 32 @@ -56,39 +42,27 @@ block/FMC: - name: ECCR description: ECC result registers. byte_offset: 148 - fieldset: ECCR - - name: BWTR1 + - name: BWTR description: SRAM/NOR-Flash write timing registers 1. + array: + len: 4 + stride: 8 byte_offset: 260 - fieldset: BWTR1 - - name: BWTR2 - description: SRAM/NOR-Flash write timing registers 2. - byte_offset: 268 - fieldset: BWTR2 - - name: BWTR3 - description: SRAM/NOR-Flash write timing registers 3. - byte_offset: 276 - fieldset: BWTR3 - - name: BWTR4 - description: SRAM/NOR-Flash write timing registers 4. - byte_offset: 284 - fieldset: BWTR4 - - name: SDCR1 + fieldset: BWTR + - name: SDCR description: SDRAM control registers 1. + array: + len: 2 + stride: 4 byte_offset: 320 - fieldset: SDCR1 - - name: SDCR2 - description: SDRAM control registers 2. - byte_offset: 324 - fieldset: SDCR2 - - name: SDTR1 + fieldset: SDCR + - name: SDTR description: SDRAM timing registers 1. + array: + len: 2 + stride: 4 byte_offset: 328 - fieldset: SDTR1 - - name: SDTR2 - description: SDRAM timing registers 2. - byte_offset: 332 - fieldset: SDTR2 + fieldset: SDTR - name: SDCMR description: SDRAM Command Mode register. byte_offset: 336 @@ -101,6 +75,81 @@ block/FMC: description: SDRAM status register. byte_offset: 344 fieldset: SDSR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register for bank 4. + fields: + - name: MBKEN + description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type Defines the type of external memory attached to the corresponding memory bank. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width Defines the external memory device width, valid for all type of memories. + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable Enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + bit_offset: 11 + bit_size: 1 + - name: WREN + description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 31 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register for bank 1. fields: @@ -176,232 +225,7 @@ fieldset/BCR1: description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' bit_offset: 31 bit_size: 1 -fieldset/BCR2: - description: SRAM/NOR-Flash chip-select control register for bank 2. - fields: - - name: MBKEN - description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type Defines the type of external memory attached to the corresponding memory bank. - bit_offset: 2 - bit_size: 2 - - name: MWID - description: Memory data bus width Defines the external memory device width, valid for all type of memories. - bit_offset: 4 - bit_size: 2 - - name: FACCEN - description: Flash access enable Enables NOR Flash memory access operations. - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. - bit_offset: 9 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. - bit_offset: 11 - bit_size: 1 - - name: WREN - description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' - bit_offset: 16 - bit_size: 3 - - name: CBURSTRW - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 21 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 31 - bit_size: 1 -fieldset/BCR3: - description: SRAM/NOR-Flash chip-select control register for bank 3. - fields: - - name: MBKEN - description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type Defines the type of external memory attached to the corresponding memory bank. - bit_offset: 2 - bit_size: 2 - - name: MWID - description: Memory data bus width Defines the external memory device width, valid for all type of memories. - bit_offset: 4 - bit_size: 2 - - name: FACCEN - description: Flash access enable Enables NOR Flash memory access operations. - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. - bit_offset: 9 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. - bit_offset: 11 - bit_size: 1 - - name: WREN - description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' - bit_offset: 16 - bit_size: 3 - - name: CBURSTRW - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 21 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 31 - bit_size: 1 -fieldset/BCR4: - description: SRAM/NOR-Flash chip-select control register for bank 4. - fields: - - name: MBKEN - description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type Defines the type of external memory attached to the corresponding memory bank. - bit_offset: 2 - bit_size: 2 - - name: MWID - description: Memory data bus width Defines the external memory device width, valid for all type of memories. - bit_offset: 4 - bit_size: 2 - - name: FACCEN - description: Flash access enable Enables NOR Flash memory access operations. - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. - bit_offset: 9 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. - bit_offset: 11 - bit_size: 1 - - name: WREN - description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' - bit_offset: 16 - bit_size: 3 - - name: CBURSTRW - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 21 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 31 - bit_size: 1 -fieldset/BTR1: +fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register for bank 1. fields: - name: ADDSET @@ -436,112 +260,7 @@ fieldset/BTR1: description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' bit_offset: 30 bit_size: 2 -fieldset/BTR2: - description: SRAM/NOR-Flash chip-select timing register for bank 2. - fields: - - name: ADDSET - description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' - bit_offset: 30 - bit_size: 2 -fieldset/BTR3: - description: SRAM/NOR-Flash chip-select timing register for bank 3. - fields: - - name: ADDSET - description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' - bit_offset: 30 - bit_size: 2 -fieldset/BTR4: - description: SRAM/NOR-Flash chip-select timing register for bank 4. - fields: - - name: ADDSET - description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' - bit_offset: 30 - bit_size: 2 -fieldset/BWTR1: +fieldset/BWTR: description: SRAM/NOR-Flash write timing registers 1. fields: - name: ADDSET @@ -568,94 +287,6 @@ fieldset/BWTR1: description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. bit_offset: 30 bit_size: 2 -fieldset/BWTR2: - description: SRAM/NOR-Flash write timing registers 2. - fields: - - name: ADDSET - description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. - bit_offset: 30 - bit_size: 2 -fieldset/BWTR3: - description: SRAM/NOR-Flash write timing registers 3. - fields: - - name: ADDSET - description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. - bit_offset: 30 - bit_size: 2 -fieldset/BWTR4: - description: SRAM/NOR-Flash write timing registers 4. - fields: - - name: ADDSET - description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. - bit_offset: 30 - bit_size: 2 -fieldset/ECCR: - description: ECC result registers. - fields: - - name: ECC - description: ECC result This field contains the value computed by the ECC computation logic. Table 99 describes the contents of these bitfields. - bit_offset: 0 - bit_size: 32 fieldset/PATT: description: Attribute memory space timing register. fields: @@ -779,7 +410,7 @@ fieldset/SDCMR: description: Mode Register definition This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. bit_offset: 9 bit_size: 13 -fieldset/SDCR1: +fieldset/SDCR: description: SDRAM control registers 1. fields: - name: NC @@ -818,45 +449,6 @@ fieldset/SDCR1: description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.' bit_offset: 13 bit_size: 2 -fieldset/SDCR2: - description: SDRAM control registers 2. - fields: - - name: NC - description: Number of column address bits These bits define the number of bits of a column address. - bit_offset: 0 - bit_size: 2 - - name: NR - description: Number of row address bits These bits define the number of bits of a row address. - bit_offset: 2 - bit_size: 2 - - name: MWID - description: Memory data bus width. These bits define the memory device width. - bit_offset: 4 - bit_size: 2 - - name: NB - description: Number of internal banks This bit sets the number of internal banks. - bit_offset: 6 - bit_size: 1 - - name: CAS - description: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles. - bit_offset: 7 - bit_size: 2 - - name: WP - description: Write protection This bit enables write mode access to the SDRAM bank. - bit_offset: 9 - bit_size: 1 - - name: SDCLK - description: 'SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.' - bit_offset: 10 - bit_size: 2 - - name: RBURST - description: 'Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.' - bit_offset: 12 - bit_size: 1 - - name: RPIPE - description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.' - bit_offset: 13 - bit_size: 2 fieldset/SDRTR: description: SDRAM refresh timer register. fields: @@ -891,7 +483,7 @@ fieldset/SDSR: description: Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request. bit_offset: 5 bit_size: 1 -fieldset/SDTR1: +fieldset/SDTR: description: SDRAM timing registers 1. fields: - name: TMRD @@ -922,37 +514,6 @@ fieldset/SDTR1: description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... bit_offset: 24 bit_size: 4 -fieldset/SDTR2: - description: SDRAM timing registers 2. - fields: - - name: TMRD - description: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: 'Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.' - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... - bit_offset: 8 - bit_size: 4 - - name: TRC - description: 'Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.' - bit_offset: 12 - bit_size: 4 - - name: TWR - description: 'Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.' - bit_offset: 16 - bit_size: 4 - - name: TRP - description: 'Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are don’t care.' - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... - bit_offset: 24 - bit_size: 4 fieldset/SR: description: FIFO status and interrupt register. fields: diff --git a/transforms/FMC.yaml b/transforms/FMC.yaml new file mode 100644 index 0000000..bc8f5da --- /dev/null +++ b/transforms/FMC.yaml @@ -0,0 +1,21 @@ +transforms: + - !DeleteFieldsets + from: ^ECCR$ + + - !MergeFieldsets + from: ^(BCR)[2-4]$ + to: $1 + + - !MergeFieldsets + from: ^(BTR|BWTR|SDCR|SDTR)\d+$ + to: $1 + + - !MakeRegisterArray + blocks: FMC + from: ^(BCR)[2-4]$ + to: $1 + + - !MakeRegisterArray + blocks: FMC + from: ^(BTR|BWTR|SDCR|SDTR)\d+$ + to: $1 From de08d9fe066c4526248019cb459d6fce87346de6 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 16:54:06 +0800 Subject: [PATCH 3/8] use extends --- data/registers/fmc_v4.yaml | 82 +------------------------------------- 1 file changed, 2 insertions(+), 80 deletions(-) diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml index 991fe7c..93fbf98 100644 --- a/data/registers/fmc_v4.yaml +++ b/data/registers/fmc_v4.yaml @@ -151,64 +151,9 @@ fieldset/BCR: bit_offset: 31 bit_size: 1 fieldset/BCR1: + extends: BCR description: SRAM/NOR-Flash chip-select control register for bank 1. fields: - - name: MBKEN - description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type Defines the type of external memory attached to the corresponding memory bank. - bit_offset: 2 - bit_size: 2 - - name: MWID - description: Memory data bus width Defines the external memory device width, valid for all type of memories. - bit_offset: 4 - bit_size: 2 - - name: FACCEN - description: Flash access enable Enables NOR Flash memory access operations. - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. - bit_offset: 9 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. - bit_offset: 11 - bit_size: 1 - - name: WREN - description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).' - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' - bit_offset: 16 - bit_size: 3 - - name: CBURSTRW - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - bit_offset: 19 - bit_size: 1 - name: CCLKEN description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' bit_offset: 20 @@ -217,33 +162,10 @@ fieldset/BCR1: description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' bit_offset: 21 bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.' - bit_offset: 31 - bit_size: 1 fieldset/BTR: + extends: BWTR description: SRAM/NOR-Flash chip-select timing register for bank 1. fields: - - name: ADDSET - description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.' - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.' - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.' - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - bit_offset: 16 - bit_size: 4 - name: CLKDIV description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).' bit_offset: 20 From ac3b6c20545b88e7b65c63f6e4a6d919c6d224c5 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 17:05:04 +0800 Subject: [PATCH 4/8] split `FMC` into `NOR_PSRAM`, `NAND` and `SDRAM` --- data/registers/fmc_v4.yaml | 63 +++++++++++++++++++++++--------------- transforms/FMC.yaml | 21 +++++++++++++ 2 files changed, 60 insertions(+), 24 deletions(-) diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml index 93fbf98..d22ce49 100644 --- a/data/registers/fmc_v4.yaml +++ b/data/registers/fmc_v4.yaml @@ -1,5 +1,37 @@ block/FMC: description: Flexible memory controller. + items: + - name: NOR_PSRAM + byte_offset: 0 + block: NOR_PSRAM + - name: NAND + byte_offset: 128 + block: NAND + - name: SDRAM + byte_offset: 320 + block: SDRAM +block/NAND: + items: + - name: PCR + description: NAND Flash control registers. + byte_offset: 0 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register. + byte_offset: 4 + fieldset: SR + - name: PMEM + description: Common memory space timing register. + byte_offset: 8 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register. + byte_offset: 12 + fieldset: PATT + - name: ECCR + description: ECC result registers. + byte_offset: 20 +block/NOR_PSRAM: items: - name: BCR1 description: SRAM/NOR-Flash chip-select control register for bank 1. @@ -23,25 +55,6 @@ block/FMC: description: PSRAM chip select counter register. byte_offset: 32 fieldset: PCSCNTR - - name: PCR - description: NAND Flash control registers. - byte_offset: 128 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register. - byte_offset: 132 - fieldset: SR - - name: PMEM - description: Common memory space timing register. - byte_offset: 136 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register. - byte_offset: 140 - fieldset: PATT - - name: ECCR - description: ECC result registers. - byte_offset: 148 - name: BWTR description: SRAM/NOR-Flash write timing registers 1. array: @@ -49,31 +62,33 @@ block/FMC: stride: 8 byte_offset: 260 fieldset: BWTR +block/SDRAM: + items: - name: SDCR description: SDRAM control registers 1. array: len: 2 stride: 4 - byte_offset: 320 + byte_offset: 0 fieldset: SDCR - name: SDTR description: SDRAM timing registers 1. array: len: 2 stride: 4 - byte_offset: 328 + byte_offset: 8 fieldset: SDTR - name: SDCMR description: SDRAM Command Mode register. - byte_offset: 336 + byte_offset: 16 fieldset: SDCMR - name: SDRTR description: SDRAM refresh timer register. - byte_offset: 340 + byte_offset: 20 fieldset: SDRTR - name: SDSR description: SDRAM status register. - byte_offset: 344 + byte_offset: 24 fieldset: SDSR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register for bank 4. diff --git a/transforms/FMC.yaml b/transforms/FMC.yaml index bc8f5da..23f71d7 100644 --- a/transforms/FMC.yaml +++ b/transforms/FMC.yaml @@ -19,3 +19,24 @@ transforms: blocks: FMC from: ^(BTR|BWTR|SDCR|SDTR)\d+$ to: $1 + + - !MakeBlock + blocks: FMC + from: ^(BCR\d*|BW?TR\d*|PCSCNTR)$ + to_outer: NOR_PSRAM + to_block: NOR_PSRAM + to_inner: $1 + + - !MakeBlock + blocks: FMC + from: ^(PCR|SR|PMEM|PATT|ECCR)$ + to_outer: NAND + to_block: NAND + to_inner: $1 + + - !MakeBlock + blocks: FMC + from: ^(SDCR\d*|SDTR\d*|SDCMR|SDRTR|SDSR)$ + to_outer: SDRAM + to_block: SDRAM + to_inner: $1 From 72aa630cf0c5e124640372137a9106eb0c3c8519 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 18:54:30 +0800 Subject: [PATCH 5/8] add enum for `NOR_PSRAM` block --- data/registers/fmc_v4.yaml | 255 ++++++++++++++++++++++++++++++++++--- transforms/FMC.yaml | 5 + 2 files changed, 239 insertions(+), 21 deletions(-) diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml index d22ce49..cf57c2d 100644 --- a/data/registers/fmc_v4.yaml +++ b/data/registers/fmc_v4.yaml @@ -105,10 +105,12 @@ fieldset/BCR: description: Memory type Defines the type of external memory attached to the corresponding memory bank. bit_offset: 2 bit_size: 2 + enum: MTYP - name: MWID description: Memory data bus width Defines the external memory device width, valid for all type of memories. bit_offset: 4 bit_size: 2 + enum: MWID - name: FACCEN description: Flash access enable Enables NOR Flash memory access operations. bit_offset: 6 @@ -121,10 +123,12 @@ fieldset/BCR: description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. bit_offset: 9 bit_size: 1 + enum: WAITPOL - name: WAITCFG description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. bit_offset: 11 bit_size: 1 + enum: WAITCFG - name: WREN description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. bit_offset: 12 @@ -145,10 +149,12 @@ fieldset/BCR: description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.' bit_offset: 16 bit_size: 3 + enum: CPSIZE - name: CBURSTRW description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. bit_offset: 19 bit_size: 1 + enum: CBURSTRW - name: CCLKEN description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).' bit_offset: 20 @@ -189,14 +195,6 @@ fieldset/BTR: description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.' bit_offset: 24 bit_size: 4 - - name: ACCMOD - description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - bit_offset: 28 - bit_size: 2 - - name: DATAHLD - description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.' - bit_offset: 30 - bit_size: 2 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers 1. fields: @@ -220,6 +218,7 @@ fieldset/BWTR: description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. bit_offset: 28 bit_size: 2 + enum: ACCMOD - name: DATAHLD description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. bit_offset: 30 @@ -289,22 +288,13 @@ fieldset/PCSCNTR: description: Chip select counter. These bits are written by software to define the maximum chip select low pulse duration. It is expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses. The counter is disabled if the programmed value is 0. bit_offset: 0 bit_size: 16 - - name: CNTB1EN + - name: CNTBEN description: Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. bit_offset: 16 bit_size: 1 - - name: CNTB2EN - description: Counter Bank 2 enable This bit enables the chip select counter for PSRAM/NOR Bank 2. - bit_offset: 17 - bit_size: 1 - - name: CNTB3EN - description: Counter Bank 3 enable This bit enables the chip select counter for PSRAM/NOR Bank 3. - bit_offset: 18 - bit_size: 1 - - name: CNTB4EN - description: Counter Bank 4 enable This bit enables the chip select counter for PSRAM/NOR Bank 4. - bit_offset: 19 - bit_size: 1 + array: + len: 4 + stride: 1 fieldset/PMEM: description: Common memory space timing register. fields: @@ -386,6 +376,7 @@ fieldset/SDCR: description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.' bit_offset: 13 bit_size: 2 + enum: RPIPE fieldset/SDRTR: description: SDRAM refresh timer register. fields: @@ -482,3 +473,225 @@ fieldset/SR: description: FIFO empty Read-only bit that provides the status of the FIFO. bit_offset: 6 bit_size: 1 +enum/ACCMOD: + bit_size: 2 + variants: + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 +enum/CAS: + bit_size: 2 + variants: + - name: Clocks1 + description: 1 cycle + value: 1 + - name: Clocks2 + description: 2 cycles + value: 2 + - name: Clocks3 + description: 3 cycles + value: 3 +enum/CBURSTRW: + bit_size: 1 + variants: + - name: Asynchronous + description: Write operations are always performed in Asynchronous mode. + value: 0 + - name: Synchronous + description: Write operations are performed in Synchronous mode. + value: 1 +enum/CPSIZE: + bit_size: 3 + variants: + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 +enum/ECCPS: + bit_size: 3 + variants: + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 +enum/MODE: + bit_size: 3 + variants: + - name: Normal + description: Normal Mode + value: 0 + - name: ClockConfigurationEnable + description: Clock Configuration Enable + value: 1 + - name: PALL + description: PALL (All Bank Precharge) command + value: 2 + - name: AutoRefreshCommand + description: Auto-refresh command + value: 3 + - name: LoadModeRegister + description: Load Mode Resgier + value: 4 + - name: SelfRefreshCommand + description: Self-refresh command + value: 5 + - name: PowerDownCommand + description: Power-down command + value: 6 +enum/MODES: + bit_size: 2 + variants: + - name: Normal + description: Normal Mode + value: 0 + - name: SelfRefresh + description: Self-refresh mode + value: 1 + - name: PowerDown + description: Power-down mode + value: 2 +enum/MTYP: + bit_size: 2 + variants: + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 +enum/MWID: + bit_size: 2 + variants: + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 +enum/NB: + bit_size: 1 + variants: + - name: NB2 + description: Two internal Banks + value: 0 + - name: NB4 + description: Four internal Banks + value: 1 +enum/NC: + bit_size: 2 + variants: + - name: Bits8 + description: 8 bits + value: 0 + - name: Bits9 + description: 9 bits + value: 1 + - name: Bits10 + description: 10 bits + value: 2 + - name: Bits11 + description: 11 bits + value: 3 +enum/NR: + bit_size: 2 + variants: + - name: Bits11 + description: 11 bits + value: 0 + - name: Bits12 + description: 12 bits + value: 1 + - name: Bits13 + description: 13 bits + value: 2 +enum/PWID: + bit_size: 2 + variants: + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 +enum/RPIPE: + bit_size: 2 + variants: + - name: NoDelay + description: No clock cycle delay + value: 0 + - name: Clocks1 + description: One clock cycle delay + value: 1 + - name: Clocks2 + description: Two clock cycles delay + value: 2 +enum/SDCLK: + bit_size: 2 + variants: + - name: Disabled + description: SDCLK clock disabled + value: 0 + - name: Div2 + description: SDCLK period = 2 x HCLK period + value: 2 + - name: Div3 + description: SDCLK period = 3 x HCLK period + value: 3 +enum/WAITCFG: + bit_size: 1 + variants: + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 +enum/WAITPOL: + bit_size: 1 + variants: + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/transforms/FMC.yaml b/transforms/FMC.yaml index 23f71d7..a618be0 100644 --- a/transforms/FMC.yaml +++ b/transforms/FMC.yaml @@ -40,3 +40,8 @@ transforms: to_outer: SDRAM to_block: SDRAM to_inner: $1 + + - !MakeFieldArray + fieldsets: ^PCSCNTR$ + from: CNTB\dEN + to: CNTBEN From e857c9cb94604fc1d34036b08fb44fa843e88410 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 19:18:09 +0800 Subject: [PATCH 6/8] add enum for `NAND` block --- data/registers/fmc_v4.yaml | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml index cf57c2d..4a74e4f 100644 --- a/data/registers/fmc_v4.yaml +++ b/data/registers/fmc_v4.yaml @@ -257,10 +257,12 @@ fieldset/PCR: description: Memory type Defines the type of device attached to the corresponding memory bank:. bit_offset: 3 bit_size: 1 + enum: PTYP - name: PWID description: Data bus width Defines the external memory device width. bit_offset: 4 bit_size: 2 + enum: PWID - name: ECCEN description: ECC computation logic enable bit. bit_offset: 6 @@ -272,15 +274,12 @@ fieldset/PCR: - name: TAR description: 'ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.' bit_offset: 13 - bit_size: 3 - - name: TAR3 - description: 'ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.' - bit_offset: 16 - bit_size: 1 + bit_size: 4 - name: ECCPS description: ECC page size Defines the page size for the extended ECC:. bit_offset: 17 bit_size: 3 + enum: ECCPS fieldset/PCSCNTR: description: PSRAM chip select counter register. fields: @@ -644,6 +643,12 @@ enum/NR: - name: Bits13 description: 13 bits value: 2 +enum/PTYP: + bit_size: 1 + variants: + - name: NAND + description: NAND flash + value: 1 enum/PWID: bit_size: 2 variants: From 05f52fcc7e66c6a9026dbe36eefbe972283d9ef3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 19:29:06 +0800 Subject: [PATCH 7/8] add enum for `SDRAM` block --- data/registers/fmc_v4.yaml | 26 ++++++++++++++++---------- transforms/FMC.yaml | 10 ++++++++++ 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml index 4a74e4f..088a548 100644 --- a/data/registers/fmc_v4.yaml +++ b/data/registers/fmc_v4.yaml @@ -320,14 +320,14 @@ fieldset/SDCMR: description: 'Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the the unused bank must be kept to 0.' bit_offset: 0 bit_size: 3 - - name: CTB2 + enum: MODE + - name: CTB description: Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. bit_offset: 3 bit_size: 1 - - name: CTB1 - description: Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. - bit_offset: 4 - bit_size: 1 + array: + len: 2 + stride: 1 - name: NRFS description: Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. .... bit_offset: 5 @@ -343,22 +343,27 @@ fieldset/SDCR: description: Number of column address bits These bits define the number of bits of a column address. bit_offset: 0 bit_size: 2 + enum: NC - name: NR description: Number of row address bits These bits define the number of bits of a row address. bit_offset: 2 bit_size: 2 + enum: NR - name: MWID description: Memory data bus width. These bits define the memory device width. bit_offset: 4 bit_size: 2 + enum: MWID - name: NB description: Number of internal banks This bit sets the number of internal banks. bit_offset: 6 bit_size: 1 + enum: NB - name: CAS description: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles. bit_offset: 7 bit_size: 2 + enum: CAS - name: WP description: Write protection This bit enables write mode access to the SDRAM bank. bit_offset: 9 @@ -367,6 +372,7 @@ fieldset/SDCR: description: 'SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.' bit_offset: 10 bit_size: 2 + enum: SDCLK - name: RBURST description: 'Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.' bit_offset: 12 @@ -398,14 +404,14 @@ fieldset/SDSR: description: Refresh error flag An interrupt is generated if REIE = 1 and RE = 1. bit_offset: 0 bit_size: 1 - - name: MODES1 + - name: MODES description: Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. bit_offset: 1 bit_size: 2 - - name: MODES2 - description: Status Mode for Bank 2 This bit defines the Status Mode of SDRAM Bank 2. - bit_offset: 3 - bit_size: 2 + array: + len: 2 + stride: 2 + enum: MODES - name: BUSY description: Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request. bit_offset: 5 diff --git a/transforms/FMC.yaml b/transforms/FMC.yaml index a618be0..0b5bb9d 100644 --- a/transforms/FMC.yaml +++ b/transforms/FMC.yaml @@ -45,3 +45,13 @@ transforms: fieldsets: ^PCSCNTR$ from: CNTB\dEN to: CNTBEN + + - !MakeFieldArray + fieldsets: ^SDCMR$ + from: CTB\d + to: CTB + + - !MakeFieldArray + fieldsets: ^SDSR$ + from: MODES\d + to: MODES From af02de81fd7ab39d4101497219ffb62ea2135b95 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 19:52:23 +0800 Subject: [PATCH 8/8] add to chips.rs --- stm32-data-gen/src/chips.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e6de9f0..258bacd 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -423,6 +423,7 @@ impl PeriMatcher { ("STM32F469.*:FMC:.*", ("fmc", "v2x1", "FMC")), ("STM32F7.*:FMC:.*", ("fmc", "v2x1", "FMC")), ("STM32H7.*:FMC:.*", ("fmc", "v3x1", "FMC")), + ("STM32H5.*:FMC:.*", ("fmc", "v4", "FMC")), ("STM32F100.*:FSMC:.*", ("fsmc", "v1x0", "FSMC")), ("STM32F10[12357].*:FSMC:.*", ("fsmc", "v1x3", "FSMC")), ("STM32F2.*:FSMC:.*", ("fsmc", "v1x3", "FSMC")),