adv, gp16, gp32 merged
This commit is contained in:
eZio Pan
parent
6eba236ede
commit
a3e7e74535
@ -1,3 +1,91 @@
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block/TIM_GP32:
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extends: TIM_GP16
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description: General purpose 32-bit timers
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items:
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- name: CNT
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description: counter (Dither mode disabled)
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byte_offset: 36
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fieldset: CNT_GP32
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- name: CNT_DITHER
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description: counter (Dither mode enbled)
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byte_offset: 36
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fieldset: CNT_DITHER_GP32
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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byte_offset: 44
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fieldset: ARR_GP32
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_GP32
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- name: CCR
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description: capture/compare register x (x=1-4) (Dither mode disabled)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_GP32
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- name: CCR_DITHER
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description: capture/compare register x (x=1-4) (Dither mode enabled)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_GP32
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fieldset/CNT_GP32:
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description: counter (Dither mode disabled)
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 32
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fieldset/CNT_DITHER_GP32:
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description: counter (Dither mode enabled)
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 31
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- name: UIFCPY
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description: UIF copy
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bit_offset: 31
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bit_size: 1
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fieldset/ARR_GP32:
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description: auto-reload register (Dither mode disabled)
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fields:
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- name: ARR
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description: Auto-reload value
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bit_offset: 0
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bit_size: 32
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fieldset/ARR_DITHER_GP32:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 28
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fieldset/CCR_DITHER_GP32:
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description: capture/compare register x (x=1-4,6) (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: CCR
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description: capture/compare x (x=1-4,6) value
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bit_offset: 4
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bit_size: 28
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fieldset/CCR_GP32:
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description: capture/compare register x (x=1-4,6) (Dither mode disabled)
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fields:
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- name: CCR
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description: capture/compare x (x=1-4,6) value
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bit_offset: 0
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bit_size: 32
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block/TIM_ADV:
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extends: TIM_GP16
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description: Advanced Control timers
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@ -1,909 +0,0 @@
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block/TIM_GP32:
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description: General purpose 32-bit timers
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1_GP32
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- name: CR2
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description: control register 2
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byte_offset: 4
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fieldset: CR2_GP32
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- name: SMCR
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description: slave mode control register
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byte_offset: 8
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fieldset: SMCR_GP32
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- name: DIER
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description: DMA/Interrupt enable register
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byte_offset: 12
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fieldset: DIER_GP32
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- name: SR
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description: status register
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byte_offset: 16
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fieldset: SR_GP32
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- name: EGR
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description: event generation register
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byte_offset: 20
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access: Write
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fieldset: EGR_GP32
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- name: CCMR_Input
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description: capture/compare mode register 1-2 (input mode)
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array:
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len: 2
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Input_GP32
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- name: CCMR_Output
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description: capture/compare mode register 1-2 (output mode)
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array:
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len: 2
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Output_GP32
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- name: CCER
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description: capture/compare enable register
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byte_offset: 32
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fieldset: CCER_GP32
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- name: CNT
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description: counter (Dither mode disabled)
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byte_offset: 36
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fieldset: CNT_GP32
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- name: CNT_DITHER
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description: counter (Dither mode enbled)
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byte_offset: 36
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fieldset: CNT_DITHER_GP32
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- name: PSC
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description: prescaler
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byte_offset: 40
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fieldset: PSC_GP32
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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byte_offset: 44
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fieldset: ARR_GP32
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_GP32
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- name: RCR
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description: repetition counter register
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byte_offset: 48
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fieldset: RCR_GP32
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- name: CCR
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description: capture/compare register x (x=1-4) (Dither mode disabled)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_GP32
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- name: CCR_DITHER
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description: capture/compare register x (x=1-4) (Dither mode enabled)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_GP32
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- name: ECR
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description: encoder control register
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byte_offset: 88
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fieldset: ECR_GP32
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- name: TISEL
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description: input selection register
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byte_offset: 92
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fieldset: TISEL_GP32
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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fieldset: AF1_GP32
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_GP32
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_GP32
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_GP32
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fieldset/AF1_GP32:
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description: alternate function register 1
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fields:
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- name: ETRSEL
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description: etr_in source selection
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bit_offset: 14
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bit_size: 4
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fieldset/AF2_GP32:
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description: alternate function register 2
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fields:
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- name: OCRSEL
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description: ocref_clr source selection
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bit_offset: 16
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bit_size: 3
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fieldset/ARR_GP32:
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description: auto-reload register (Dither mode disabled)
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fields:
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- name: ARR
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description: Auto-reload value
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bit_offset: 0
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bit_size: 32
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fieldset/ARR_DITHER_GP32:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 28
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fieldset/CCER_GP32:
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description: capture/compare enable register
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fields:
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- name: CCE
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description: Capture/Compare x (x=1-6) output enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 4
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- name: CCP
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description: Capture/Compare x (x=1-6) output Polarity
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bit_offset: 1
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bit_size: 1
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array:
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len: 6
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stride: 4
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- name: CCNP
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description: Capture/Compare x (x=1-4) output Polarity
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bit_offset: 3
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bit_size: 1
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array:
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len: 4
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stride: 4
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fieldset/CCMR_Input_GP32:
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description: capture/compare mode register x (x=1-2) (input mode)
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fields:
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- name: CCS
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description: Capture/Compare y selection
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bit_offset: 0
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bit_size: 2
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array:
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len: 2
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stride: 8
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enum: CCMR_Input_CCS
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- name: ICPSC
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description: Input capture y prescaler
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bit_offset: 2
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bit_size: 2
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array:
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len: 2
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stride: 8
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- name: ICF
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description: Input capture y filter
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bit_offset: 4
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bit_size: 4
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array:
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len: 2
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stride: 8
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enum: FilterValue
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fieldset/CCMR_Output_GP32:
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description: capture/compare mode register x (x=1-3) (output mode)
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fields:
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- name: CCS
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description: Capture/Compare y selection
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bit_offset: 0
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bit_size: 2
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array:
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len: 2
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stride: 8
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enum: CCMR_Output_CCS
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- name: OCFE
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description: Output compare y fast enable
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bit_offset: 2
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bit_size: 1
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array:
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len: 2
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stride: 8
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- name: OCPE
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description: Output compare y preload enable
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bit_offset: 3
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bit_size: 1
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array:
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len: 2
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stride: 8
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- name: OCM
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description: Output compare y mode
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bit_offset: 4
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bit_size: 3
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array:
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len: 2
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stride: 8
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enum: OCM
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- name: OCCE
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description: Output compare y clear enable
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bit_offset: 7
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bit_size: 1
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array:
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len: 2
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stride: 8
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fieldset/CCR_GP32:
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description: capture/compare register x (x=1-4,6) (Dither mode disabled)
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fields:
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- name: CCR
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description: capture/compare x (x=1-4,6) value
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bit_offset: 0
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bit_size: 32
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fieldset/CCR_DITHER_GP32:
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description: capture/compare register x (x=1-4,6) (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: CCR
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description: capture/compare x (x=1-4,6) value
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bit_offset: 4
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bit_size: 28
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fieldset/CNT_GP32:
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description: counter (Dither mode disabled)
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 32
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fieldset/CNT_DITHER_GP32:
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description: counter (Dither mode enabled)
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 31
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- name: UIFCPY
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description: UIF copy
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bit_offset: 31
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bit_size: 1
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fieldset/CR1_GP32:
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description: control register 1
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fields:
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- name: CEN
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description: Counter enable
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bit_offset: 0
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bit_size: 1
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- name: UDIS
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description: Update disable
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bit_offset: 1
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bit_size: 1
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- name: URS
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description: Update request source
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bit_offset: 2
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bit_size: 1
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enum: URS
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- name: OPM
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description: One-pulse mode enbaled
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bit_offset: 3
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bit_size: 1
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- name: DIR
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description: Direction
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bit_offset: 4
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bit_size: 1
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enum: DIR
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- name: CMS
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description: Center-aligned mode selection
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bit_offset: 5
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bit_size: 2
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enum: CMS
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- name: ARPE
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description: Auto-reload preload enable
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bit_offset: 7
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bit_size: 1
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- name: CKD
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description: Clock division
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bit_offset: 8
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bit_size: 2
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enum: CKD
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- name: UIFREMAP
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description: UIF status bit remapping enable
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bit_offset: 11
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bit_size: 1
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- name: DITHEN
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description: Dithering enable
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bit_offset: 12
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bit_size: 1
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fieldset/CR2_GP32:
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description: control register 2
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fields:
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- name: CCDS
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description: Capture/compare DMA selection
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bit_offset: 3
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bit_size: 1
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enum: CCDS
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- name: MMS
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description: Master mode selection
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bit_offset: 4
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bit_size: 3
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enum: MMS
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- name: TI1S
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description: TI1 selection
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bit_offset: 7
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bit_size: 1
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enum: TI1S
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fieldset/DCR_GP32:
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description: DMA control register
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fields:
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- name: DBA
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description: DMA base address
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bit_offset: 0
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bit_size: 5
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- name: DBL
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description: DMA burst length
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bit_offset: 8
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bit_size: 5
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- name: DBSS
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description: DMA burst source selection
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bit_offset: 16
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bit_size: 4
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enum: DBSS
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fieldset/DIER_GP32:
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description: DMA/Interrupt enable register
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fields:
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- name: UIE
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description: Update interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: CCIE
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description: Capture/Compare x (x=1-4) interrupt enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 4
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stride: 1
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- name: TIE
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description: Trigger interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: BIE
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description: Break interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: UDE
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description: Update DMA request enable
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bit_offset: 8
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bit_size: 1
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- name: CCDE
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description: Capture/Compare x (x=1-4) DMA request enable
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bit_offset: 9
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bit_size: 1
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array:
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len: 4
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stride: 1
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- name: TDE
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description: Trigger DMA request enable
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bit_offset: 14
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bit_size: 1
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- name: IDXIE
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description: Index interrupt enable
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bit_offset: 20
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bit_size: 1
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- name: DIRIE
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description: Direction change interrupt enable
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bit_offset: 21
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bit_size: 1
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- name: IERRIE
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description: Index error interrupt enable
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bit_offset: 22
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bit_size: 1
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- name: TERRIE
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description: Transition error interrupt enable
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bit_offset: 23
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bit_size: 1
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fieldset/DMAR_GP32:
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description: DMA address for full transfer
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fields:
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- name: DMAB
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description: DMA register for burst accesses
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bit_offset: 0
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bit_size: 32
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fieldset/ECR_GP32:
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description: encoder control register
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fields:
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- name: IE
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description: Index enable
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bit_offset: 0
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bit_size: 1
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- name: IDIR
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description: Index direction
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bit_offset: 1
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bit_size: 2
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enum: IDIR
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- name: IBLK
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description: Index blanking
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bit_offset: 3
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bit_size: 2
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enum: IBLK
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- name: FIDX
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description: First index
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bit_offset: 5
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bit_size: 1
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enum: FIDX
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- name: IPOS
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description: Index positioning
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bit_offset: 6
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bit_size: 2
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- name: PW
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description: Pulse width
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bit_offset: 16
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bit_size: 8
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- name: PWPRSC
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description: Pulse width prescaler
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bit_offset: 24
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bit_size: 2
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fieldset/EGR_GP32:
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description: event generation register
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fields:
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- name: UG
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description: Update generation
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bit_offset: 0
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bit_size: 1
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- name: CCG
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description: Capture/compare x (x=1-4) generation
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bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: TG
|
||||
description: Trigger generation
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/PSC_GP32:
|
||||
description: prescaler
|
||||
fields:
|
||||
- name: PSC
|
||||
description: Prescaler value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/RCR_GP32:
|
||||
description: repetition counter register
|
||||
fields:
|
||||
- name: REP
|
||||
description: Repetition counter value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/SMCR_GP32:
|
||||
description: slave mode control register
|
||||
fields:
|
||||
- name: SMS
|
||||
description: Slave mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SMS
|
||||
- name: TS
|
||||
description: Trigger selection
|
||||
bit_offset: 4
|
||||
bit_size: 3
|
||||
enum: TS
|
||||
- name: MSM
|
||||
description: Master/Slave mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: MSM
|
||||
- name: ETF
|
||||
description: External trigger filter
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
enum: FilterValue
|
||||
- name: ETPS
|
||||
description: External trigger prescaler
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: ETPS
|
||||
- name: ECE
|
||||
description: External clock mode 2 enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ETP
|
||||
description: External trigger polarity
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: ETP
|
||||
- name: SMSPE
|
||||
description: SMS preload enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SMSPS
|
||||
description: SMS preload source
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: SMSPS
|
||||
fieldset/SR_GP32:
|
||||
description: status register
|
||||
fields:
|
||||
- name: UIF
|
||||
description: Update interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CCIF
|
||||
description: Capture/compare x (x=1-4) interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: TIF
|
||||
description: Trigger interrupt flag
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CCOF
|
||||
description: Capture/Compare x (x=1-4) overcapture flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: IDXIF
|
||||
description: Index interrupt flag
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DIRIF
|
||||
description: Direction change interrupt flag
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: IERRIF
|
||||
description: Index error interrupt flag
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TERRIF
|
||||
description: Transition error interrupt flag
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/TISEL_GP32:
|
||||
description: input selection register
|
||||
fields:
|
||||
- name: TISEL
|
||||
description: Selects TIM_TIx (x=1-4) input
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
enum/CCDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OnCompare
|
||||
description: CCx DMA request sent when CCx event occurs
|
||||
value: 0
|
||||
- name: OnUpdate
|
||||
description: CCx DMA request sent when update event occurs
|
||||
value: 1
|
||||
enum/CCMR_Input_CCS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TI4
|
||||
description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx'
|
||||
value: 1
|
||||
- name: TI3
|
||||
description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)
|
||||
value: 2
|
||||
- name: TRC
|
||||
description: CCx channel is configured as input, ICx is mapped on TRC
|
||||
value: 3
|
||||
enum/CCMR_Output_CCS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Output
|
||||
description: CCx channel is configured as output
|
||||
value: 0
|
||||
enum/CKD:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Div1
|
||||
description: t_DTS = t_CK_INT
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: t_DTS = 2 × t_CK_INT
|
||||
value: 1
|
||||
- name: Div4
|
||||
description: t_DTS = 4 × t_CK_INT
|
||||
value: 2
|
||||
enum/CMS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: EdgeAligned
|
||||
description: The counter counts up or down depending on the direction bit
|
||||
value: 0
|
||||
- name: CenterAligned1
|
||||
description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
|
||||
value: 1
|
||||
- name: CenterAligned2
|
||||
description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
|
||||
value: 2
|
||||
- name: CenterAligned3
|
||||
description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
|
||||
value: 3
|
||||
enum/DBSS:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Update
|
||||
description: Update
|
||||
value: 1
|
||||
- name: CC1
|
||||
description: CC1
|
||||
value: 2
|
||||
- name: CC2
|
||||
description: CC2
|
||||
value: 3
|
||||
- name: CC3
|
||||
description: CC3
|
||||
value: 4
|
||||
- name: CC4
|
||||
description: CC4
|
||||
value: 5
|
||||
- name: COM
|
||||
description: COM
|
||||
value: 6
|
||||
- name: Trigger
|
||||
description: Trigger
|
||||
value: 7
|
||||
enum/DIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Up
|
||||
description: Counter used as upcounter
|
||||
value: 0
|
||||
- name: Down
|
||||
description: Counter used as downcounter
|
||||
value: 1
|
||||
enum/ETP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotInverted
|
||||
description: ETR is noninverted, active at high level or rising edge
|
||||
value: 0
|
||||
- name: Inverted
|
||||
description: ETR is inverted, active at low level or falling edge
|
||||
value: 1
|
||||
enum/ETPS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Div1
|
||||
description: Prescaler OFF
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: ETRP frequency divided by 2
|
||||
value: 1
|
||||
- name: Div4
|
||||
description: ETRP frequency divided by 4
|
||||
value: 2
|
||||
- name: Div8
|
||||
description: ETRP frequency divided by 8
|
||||
value: 3
|
||||
enum/FIDX:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AlwaysActive
|
||||
description: Index is always active
|
||||
value: 0
|
||||
- name: FirstOnly
|
||||
description: the first Index only resets the counter
|
||||
value: 1
|
||||
enum/FilterValue:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: NoFilter
|
||||
description: No filter, sampling is done at fDTS
|
||||
value: 0
|
||||
- name: FCK_INT_N2
|
||||
description: fSAMPLING=fCK_INT, N=2
|
||||
value: 1
|
||||
- name: FCK_INT_N4
|
||||
description: fSAMPLING=fCK_INT, N=4
|
||||
value: 2
|
||||
- name: FCK_INT_N8
|
||||
description: fSAMPLING=fCK_INT, N=8
|
||||
value: 3
|
||||
- name: FDTS_Div2_N6
|
||||
description: fSAMPLING=fDTS/2, N=6
|
||||
value: 4
|
||||
- name: FDTS_Div2_N8
|
||||
description: fSAMPLING=fDTS/2, N=8
|
||||
value: 5
|
||||
- name: FDTS_Div4_N6
|
||||
description: fSAMPLING=fDTS/4, N=6
|
||||
value: 6
|
||||
- name: FDTS_Div4_N8
|
||||
description: fSAMPLING=fDTS/4, N=8
|
||||
value: 7
|
||||
- name: FDTS_Div8_N6
|
||||
description: fSAMPLING=fDTS/8, N=6
|
||||
value: 8
|
||||
- name: FDTS_Div8_N8
|
||||
description: fSAMPLING=fDTS/8, N=8
|
||||
value: 9
|
||||
- name: FDTS_Div16_N5
|
||||
description: fSAMPLING=fDTS/16, N=5
|
||||
value: 10
|
||||
- name: FDTS_Div16_N6
|
||||
description: fSAMPLING=fDTS/16, N=6
|
||||
value: 11
|
||||
- name: FDTS_Div16_N8
|
||||
description: fSAMPLING=fDTS/16, N=8
|
||||
value: 12
|
||||
- name: FDTS_Div32_N5
|
||||
description: fSAMPLING=fDTS/32, N=5
|
||||
value: 13
|
||||
- name: FDTS_Div32_N6
|
||||
description: fSAMPLING=fDTS/32, N=6
|
||||
value: 14
|
||||
- name: FDTS_Div32_N8
|
||||
description: fSAMPLING=fDTS/32, N=8
|
||||
value: 15
|
||||
enum/IBLK:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: AlwaysActive
|
||||
description: Index always active
|
||||
value: 0
|
||||
- name: CC3P
|
||||
description: Index disabled when tim_ti3 input is active, as per CC3P bitfield
|
||||
value: 1
|
||||
- name: CC4P
|
||||
description: Index disabled when tim_ti4 input is active, as per CC4P bitfield
|
||||
value: 2
|
||||
enum/IDIR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Both
|
||||
description: Index resets the counter whatever the direction
|
||||
value: 0
|
||||
- name: Up
|
||||
description: Index resets the counter when up-counting only
|
||||
value: 1
|
||||
- name: Down
|
||||
description: Index resets the counter when down-counting only
|
||||
value: 2
|
||||
enum/MMS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Reset
|
||||
description: The UG bit from the TIMx_EGR register is used as trigger output
|
||||
value: 0
|
||||
- name: Enable
|
||||
description: The counter enable signal, CNT_EN, is used as trigger output
|
||||
value: 1
|
||||
- name: Update
|
||||
description: The update event is selected as trigger output
|
||||
value: 2
|
||||
- name: ComparePulse
|
||||
description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
|
||||
value: 3
|
||||
- name: CompareOC1
|
||||
description: OC1REF signal is used as trigger output
|
||||
value: 4
|
||||
- name: CompareOC2
|
||||
description: OC2REF signal is used as trigger output
|
||||
value: 5
|
||||
- name: CompareOC3
|
||||
description: OC3REF signal is used as trigger output
|
||||
value: 6
|
||||
- name: CompareOC4
|
||||
description: OC4REF signal is used as trigger output
|
||||
value: 7
|
||||
enum/MSM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoSync
|
||||
description: No action
|
||||
value: 0
|
||||
- name: Sync
|
||||
description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
|
||||
value: 1
|
||||
enum/OCM:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Frozen
|
||||
description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
|
||||
value: 0
|
||||
- name: ActiveOnMatch
|
||||
description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
|
||||
value: 1
|
||||
- name: InactiveOnMatch
|
||||
description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
|
||||
value: 2
|
||||
- name: Toggle
|
||||
description: OCyREF toggles when TIMx_CNT=TIMx_CCRy
|
||||
value: 3
|
||||
- name: ForceInactive
|
||||
description: OCyREF is forced low
|
||||
value: 4
|
||||
- name: ForceActive
|
||||
description: OCyREF is forced high
|
||||
value: 5
|
||||
- name: PwmMode1
|
||||
description: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
|
||||
value: 6
|
||||
- name: PwmMode2
|
||||
description: Inversely to PwmMode1
|
||||
value: 7
|
||||
enum/SMS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
|
||||
value: 0
|
||||
- name: Encoder_Mode_1
|
||||
description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
|
||||
value: 1
|
||||
- name: Encoder_Mode_2
|
||||
description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
|
||||
value: 2
|
||||
- name: Encoder_Mode_3
|
||||
description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
|
||||
value: 3
|
||||
- name: Reset_Mode
|
||||
description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
|
||||
value: 4
|
||||
- name: Gated_Mode
|
||||
description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
|
||||
value: 5
|
||||
- name: Trigger_Mode
|
||||
description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
|
||||
value: 6
|
||||
- name: Ext_Clock_Mode
|
||||
description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
|
||||
value: 7
|
||||
enum/SMSPS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Update
|
||||
description: The transfer is triggered by the Timer’s Update event
|
||||
value: 0
|
||||
- name: Index
|
||||
description: The transfer is triggered by the Index event
|
||||
value: 1
|
||||
enum/TI1S:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Normal
|
||||
description: The TIMx_CH1 pin is connected to TI1 input
|
||||
value: 0
|
||||
- name: XOR
|
||||
description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
|
||||
value: 1
|
||||
enum/TS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: ITR0
|
||||
description: Internal Trigger 0 (ITR0)
|
||||
value: 0
|
||||
- name: ITR1
|
||||
description: Internal Trigger 1 (ITR1)
|
||||
value: 1
|
||||
- name: ITR2
|
||||
description: Internal Trigger 2 (ITR2)
|
||||
value: 2
|
||||
- name: ITR3
|
||||
description: Internal Trigger 3 (ITR3)
|
||||
value: 3
|
||||
- name: TI1F_ED
|
||||
description: TI1 Edge Detector (TI1F_ED)
|
||||
value: 4
|
||||
- name: TI1FP1
|
||||
description: Filtered Timer Input 1 (TI1FP1)
|
||||
value: 5
|
||||
- name: TI2FP2
|
||||
description: Filtered Timer Input 2 (TI2FP2)
|
||||
value: 6
|
||||
- name: ETRF
|
||||
description: External Trigger input (ETRF)
|
||||
value: 7
|
||||
enum/URS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AnyEvent
|
||||
description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
|
||||
value: 0
|
||||
- name: CounterOnly
|
||||
description: Only counter overflow/underflow generates an update interrupt or DMA request
|
||||
value: 1
|
||||
Loading…
x
Reference in New Issue
Block a user