diff --git a/data/registers/dbgmcu_wl5x.yaml b/data/registers/dbgmcu_wl5x.yaml new file mode 100644 index 0000000..7f54639 --- /dev/null +++ b/data/registers/dbgmcu_wl5x.yaml @@ -0,0 +1,181 @@ +--- +block/DBGMCU: + description: Microcontroller Debug Unit + items: + - name: IDCODER + description: DBGMCU Identity Code Register + byte_offset: 0 + access: Read + fieldset: IDCODER + - name: CR + description: DBGMCU Configuration Register + byte_offset: 4 + fieldset: CR + - name: APB1FZR1 + description: DBGMCU CPU1 APB1 Peripheral Freeze Register 1 + byte_offset: 60 + fieldset: APB1FZR1 + - name: C2APB1FZR1 + description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device" + byte_offset: 64 + fieldset: C2APB1FZR1 + - name: APB1FZR2 + description: DBGMCU CPU1 APB1 Peripheral Freeze Register 2 + byte_offset: 68 + fieldset: APB1FZR2 + - name: C2APB1FZR2 + description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device" + byte_offset: 72 + fieldset: C2APB1FZR2 + - name: APB2FZR + description: DBGMCU CPU1 APB2 Peripheral Freeze Register + byte_offset: 76 + fieldset: APB2FZR + - name: C2APB2FZR + description: "DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device" + byte_offset: 80 + fieldset: C2APB2FZR +fieldset/APB1FZR1: + description: DBGMCU CPU1 APB1 Peripheral Freeze Register 1 + fields: + - name: DBG_TIM2_STOP + description: TIM2 stop in CPU1 debug + bit_offset: 0 + bit_size: 1 + - name: DBG_RTC_STOP + description: RTC stop in CPU1 debug + bit_offset: 10 + bit_size: 1 + - name: DBG_WWDG_STOP + description: WWDG stop in CPU1 debug + bit_offset: 11 + bit_size: 1 + - name: DBG_IWDG_STOP + description: IWDG stop in CPU1 debug + bit_offset: 12 + bit_size: 1 + - name: DBG_I2C1_STOP + description: I2C1 SMBUS timeout stop in CPU1 debug + bit_offset: 21 + bit_size: 1 + - name: DBG_I2C2_STOP + description: I2C2 SMBUS timeout stop in CPU1 debug + bit_offset: 22 + bit_size: 1 + - name: DBG_I2C3_STOP + description: I2C3 SMBUS timeout stop in CPU1 debug + bit_offset: 23 + bit_size: 1 + - name: DBG_LPTIM1_STOP + description: LPTIM1 stop in CPU1 debug + bit_offset: 31 + bit_size: 1 +fieldset/APB1FZR2: + description: DBGMCU CPU1 APB1 Peripheral Freeze Register 2 + fields: + - name: DBG_LPTIM2_STOP + description: DBG_LPTIM2_STOP + bit_offset: 5 + bit_size: 1 + - name: DBG_LPTIM3_STOP + description: DBG_LPTIM3_STOP + bit_offset: 6 + bit_size: 1 +fieldset/APB2FZR: + description: DBGMCU CPU1 APB2 Peripheral Freeze Register + fields: + - name: DBG_TIM1_STOP + description: DBG_TIM1_STOP + bit_offset: 11 + bit_size: 1 + - name: DBG_TIM16_STOP + description: DBG_TIM16_STOP + bit_offset: 17 + bit_size: 1 + - name: DBG_TIM17_STOP + description: DBG_TIM17_STOP + bit_offset: 18 + bit_size: 1 +fieldset/C2APB1FZR1: + description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device" + fields: + - name: DBG_TIM2_STOP + description: DBG_TIM2_STOP + bit_offset: 0 + bit_size: 1 + - name: DBG_RTC_STOP + description: DBG_RTC_STOP + bit_offset: 10 + bit_size: 1 + - name: DBG_IWDG_STOP + description: DBG_IWDG_STOP + bit_offset: 12 + bit_size: 1 + - name: DBG_I2C1_STOP + description: DBG_I2C1_STOP + bit_offset: 21 + bit_size: 1 + - name: DBG_I2C2_STOP + description: DBG_I2C2_STOP + bit_offset: 22 + bit_size: 1 + - name: DBG_I2C3_STOP + description: DBG_I2C3_STOP + bit_offset: 23 + bit_size: 1 + - name: DBG_LPTIM1_STOP + description: DBG_LPTIM1_STOP + bit_offset: 31 + bit_size: 1 +fieldset/C2APB1FZR2: + description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device" + fields: + - name: DBG_LPTIM2_STOP + description: DBG_LPTIM2_STOP + bit_offset: 5 + bit_size: 1 + - name: DBG_LPTIM3_STOP + description: DBG_LPTIM3_STOP + bit_offset: 6 + bit_size: 1 +fieldset/C2APB2FZR: + description: "DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device" + fields: + - name: DBG_TIM1_STOP + description: DBG_TIM1_STOP + bit_offset: 11 + bit_size: 1 + - name: DBG_TIM16_STOP + description: DBG_TIM16_STOP + bit_offset: 17 + bit_size: 1 + - name: DBG_TIM17_STOP + description: DBG_TIM17_STOP + bit_offset: 18 + bit_size: 1 +fieldset/CR: + description: DBGMCU Configuration Register + fields: + - name: DBG_SLEEP + description: Allow debug in SLEEP mode + bit_offset: 0 + bit_size: 1 + - name: DBG_STOP + description: Allow debug in STOP mode + bit_offset: 1 + bit_size: 1 + - name: DBG_STANDBY + description: Allow debug in STANDBY mode + bit_offset: 2 + bit_size: 1 +fieldset/IDCODER: + description: DBGMCU Identity Code Register + fields: + - name: DEV_ID + description: Device ID + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: Revision + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/rcc_wl5x.yaml b/data/registers/rcc_wl5x.yaml new file mode 100644 index 0000000..8537225 --- /dev/null +++ b/data/registers/rcc_wl5x.yaml @@ -0,0 +1,1424 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: APB3RSTR + description: APB3 peripheral reset register + byte_offset: 68 + fieldset: APB3RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1 peripheral clock enable register 1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 96 + fieldset: APB2ENR + - name: APB3ENR + description: APB3 peripheral clock enable register + byte_offset: 100 + fieldset: APB3ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1 peripheral clocks enable in Sleep mode register 1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep mode register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2 peripheral clocks enable in Sleep mode register + byte_offset: 128 + fieldset: APB2SMENR + - name: APB3SMENR + description: APB3 peripheral clock enable in Sleep mode register + byte_offset: 132 + fieldset: APB3SMENR + - name: CCIPR + description: Peripherals independent clock configuration register + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: Backup domain control register + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: Control/status register + byte_offset: 148 + fieldset: CSR + - name: EXTCFGR + description: Extended clock recovery register + byte_offset: 264 + fieldset: EXTCFGR + - name: C2AHB1ENR + description: CPU2 AHB1 peripheral clock enable register + byte_offset: 328 + fieldset: C2AHB1ENR + - name: C2AHB2ENR + description: CPU2 AHB2 peripheral clock enable register + byte_offset: 332 + fieldset: C2AHB2ENR + - name: C2AHB3ENR + description: "CPU2 AHB3 peripheral clock enable register [dual core device only]" + byte_offset: 336 + fieldset: C2AHB3ENR + - name: C2APB1ENR1 + description: "CPU2 APB1 peripheral clock enable register 1 [dual core device only]" + byte_offset: 344 + fieldset: C2APB1ENR1 + - name: C2APB1ENR2 + description: "CPU2 APB1 peripheral clock enable register 2 [dual core device only]" + byte_offset: 348 + fieldset: C2APB1ENR2 + - name: C2APB2ENR + description: "CPU2 APB2 peripheral clock enable register [dual core device only]" + byte_offset: 352 + fieldset: C2APB2ENR + - name: C2APB3ENR + description: "CPU2 APB3 peripheral clock enable register [dual core device only]" + byte_offset: 356 + fieldset: C2APB3ENR + - name: C2AHB1SMENR + description: "CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]" + byte_offset: 360 + fieldset: C2AHB1SMENR + - name: C2AHB2SMENR + description: "CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]" + byte_offset: 364 + fieldset: C2AHB2SMENR + - name: C2AHB3SMENR + description: "CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]" + byte_offset: 368 + fieldset: C2AHB3SMENR + - name: C2APB1SMENR1 + description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]" + byte_offset: 376 + fieldset: C2APB1SMENR1 + - name: C2APB1SMENR2 + description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]" + byte_offset: 380 + fieldset: C2APB1SMENR2 + - name: C2APB2SMENR + description: "CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]" + byte_offset: 384 + fieldset: C2APB2SMENR + - name: C2APB3SMENR + description: "CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]" + byte_offset: 388 + fieldset: C2APB3SMENR +fieldset/AHB1ENR: + description: AHB1 peripheral clock enable register + fields: + - name: DMA1EN + description: CPU1 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU1 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU1 DMAMUX1 clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU1 CRC clock enable + bit_offset: 12 + bit_size: 1 +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1 reset + bit_offset: 2 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 +fieldset/AHB1SMENR: + description: AHB1 peripheral clocks enable in Sleep modes register + fields: + - name: DMA1SMEN + description: DMA1 clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during CPU1 CSleep mode + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX1 clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - name: GPIOAEN + description: CPU1 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU1 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU1 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: CPU1 IO port H clock enable + bit_offset: 7 + bit_size: 1 +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 +fieldset/AHB2SMENR: + description: AHB2 peripheral clocks enable in Sleep modes register + fields: + - name: GPIOASMEN + description: IO port A clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clock enable during CPU1 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clock enable during CPU1 CSleep mode. + bit_offset: 7 + bit_size: 1 +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - name: PKAEN + description: PKAEN + bit_offset: 16 + bit_size: 1 + - name: AESEN + description: AESEN + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: RNGEN + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: HSEMEN + bit_offset: 19 + bit_size: 1 + - name: IPCCEN + description: IPCCEN + bit_offset: 20 + bit_size: 1 + - name: FLASHEN + description: CPU1 Flash interface clock enable + bit_offset: 25 + bit_size: 1 +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - name: PKARST + description: PKARST + bit_offset: 16 + bit_size: 1 + - name: AESRST + description: AESRST + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: RNGRST + bit_offset: 18 + bit_size: 1 + - name: HSEMRST + description: HSEMRST + bit_offset: 19 + bit_size: 1 + - name: IPCCRST + description: IPCCRST + bit_offset: 20 + bit_size: 1 + - name: FLASHRST + description: Flash interface reset + bit_offset: 25 + bit_size: 1 +fieldset/AHB3SMENR: + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: PKASMEN + description: PKA accelerator clock enable during CPU1 CSleep mode. + bit_offset: 16 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clocks enable during CPU1 Csleep and CStop modes + bit_offset: 18 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU1 CSleep mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 memory interface clock enable during CPU1 CSleep mode + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clock enable during CPU1 CSleep mode. + bit_offset: 25 + bit_size: 1 +fieldset/APB1ENR1: + description: APB1 peripheral clock enable register 1 + fields: + - name: TIM2EN + description: CPU1 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: RTCAPBEN + description: CPU1 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: CPU1 Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2S2EN + description: CPU1 SPI2S2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: CPU1 USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: CPU1 I2C1 clocks enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: CPU1 I2C2 clocks enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: CPU1 I2C3 clocks enable + bit_offset: 23 + bit_size: 1 + - name: DAC1EN + description: CPU1 DAC1 clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: CPU1 Low power timer 1 clocks enable + bit_offset: 31 + bit_size: 1 +fieldset/APB1ENR2: + description: APB1 peripheral clock enable register 2 + fields: + - name: LPUART1EN + description: CPU1 Low power UART 1 clocks enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU1 Low power timer 2 clocks enable + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: CPU1 Low power timer 3 clocks enable + bit_offset: 6 + bit_size: 1 +fieldset/APB1RSTR1: + description: APB1 peripheral reset register 1 + fields: + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: SPI2S2RST + description: SPI2S2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: DACRST + description: DAC1 reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 +fieldset/APB1RSTR2: + description: APB1 peripheral reset register 2 + fields: + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 + - name: LPTIM3RST + description: Low-power timer 3 reset + bit_offset: 6 + bit_size: 1 +fieldset/APB1SMENR1: + description: APB1 peripheral clocks enable in Sleep mode register 1 + fields: + - name: TIM2SMEN + description: TIM2 timer clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC bus clock enable during CPU1 CSleep mode. + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI2S2SMEN + description: SPI2S2 clock enable during CPU1 CSleep mode. + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during CPU1 Csleep and CStop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 23 + bit_size: 1 + - name: DACSMEN + description: DAC1 clock enable during CPU1 CSleep mode. + bit_offset: 29 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode + bit_offset: 31 + bit_size: 1 +fieldset/APB1SMENR2: + description: APB1 peripheral clocks enable in Sleep mode register 2 + fields: + - name: LPUART1SMEN + description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 6 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - name: ADCEN + description: CPU1 ADC clocks enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: CPU1 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU1 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU1 USART1clocks enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU1 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU1 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - name: ADCRST + description: ADC reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 +fieldset/APB2SMENR: + description: APB2 peripheral clocks enable in Sleep mode register + fields: + - name: ADCSMEN + description: ADC clocks enable during CPU1 Csleep and CStop modes + bit_offset: 9 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clock enable during CPU1 CSleep mode. + bit_offset: 18 + bit_size: 1 +fieldset/APB3ENR: + description: APB3 peripheral clock enable register + fields: + - name: SUBGHZSPIEN + description: sub-GHz radio SPI clock enable + bit_offset: 0 + bit_size: 1 +fieldset/APB3RSTR: + description: APB3 peripheral reset register + fields: + - name: SUBGHZSPIRST + description: Sub-GHz radio SPI reset + bit_offset: 0 + bit_size: 1 +fieldset/APB3SMENR: + description: APB3 peripheral clock enable in Sleep mode register + fields: + - name: SUBGHZSPISMEN + description: Sub-GHz radio SPI clock enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register + fields: + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: LSE system clock enable + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + - name: LSESYSRDY + description: LSE system clock ready + bit_offset: 11 + bit_size: 1 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 +fieldset/C2AHB1ENR: + description: CPU2 AHB1 peripheral clock enable register + fields: + - name: DMA1EN + description: CPU2 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU2 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU2 DMAMUX1 clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU2 CRC clock enable + bit_offset: 12 + bit_size: 1 +fieldset/C2AHB1SMENR: + description: "CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]" + fields: + - name: DMA1SMEN + description: DMA1 clock enable during CPU2 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during CPU2 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX1 clock enable during CPU2 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during CPU2 CSleep mode. + bit_offset: 12 + bit_size: 1 +fieldset/C2AHB2ENR: + description: CPU2 AHB2 peripheral clock enable register + fields: + - name: GPIOAEN + description: CPU2 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU2 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU2 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: CPU2 IO port H clock enable + bit_offset: 7 + bit_size: 1 +fieldset/C2AHB2SMENR: + description: "CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]" + fields: + - name: GPIOASMEN + description: IO port A clock enable during CPU2 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clock enable during CPU2 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clock enable during CPU2 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clock enable during CPU2 CSleep mode. + bit_offset: 7 + bit_size: 1 +fieldset/C2AHB3ENR: + description: "CPU2 AHB3 peripheral clock enable register [dual core device only]" + fields: + - name: PKAEN + description: CPU2 PKA accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: AESEN + description: CPU2 AES accelerator clock enable + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: CPU2 True RNG clocks enable + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: CPU2 HSEM clock enable + bit_offset: 19 + bit_size: 1 + - name: IPCCEN + description: CPU2 IPCC interface clock enable + bit_offset: 20 + bit_size: 1 + - name: FLASHEN + description: CPU2 Flash interface clock enable + bit_offset: 25 + bit_size: 1 +fieldset/C2AHB3SMENR: + description: "CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]" + fields: + - name: PKASMEN + description: PKA accelerator clock enable during CPU2 CSleep mode. + bit_offset: 16 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clock enable during CPU2 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clock enable during CPU2 CSleep and CStop mode. + bit_offset: 18 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU2 CSleep mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 memory interface clock enable during CPU2 CSleep mode. + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clock enable during CPU2 CSleep mode. + bit_offset: 25 + bit_size: 1 +fieldset/C2APB1ENR1: + description: "CPU2 APB1 peripheral clock enable register 1 [dual core device only]" + fields: + - name: TIM2EN + description: CPU2 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: RTCAPBEN + description: CPU2 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: SPI2S2EN + description: CPU2 SPI2S2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: CPU2 USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: CPU2 I2C1 clocks enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: CPU2 I2C2 clocks enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: CPU2 I2C3 clocks enable + bit_offset: 23 + bit_size: 1 + - name: DAC1EN + description: CPU2 DAC1 clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: CPU2 Low power timer 1 clocks enable + bit_offset: 31 + bit_size: 1 +fieldset/C2APB1ENR2: + description: "CPU2 APB1 peripheral clock enable register 2 [dual core device only]" + fields: + - name: LPUART1EN + description: CPU2 Low power UART 1 clocks enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU2 Low power timer 2 clocks enable + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: CPU2 Low power timer 3 clocks enable + bit_offset: 6 + bit_size: 1 +fieldset/C2APB1SMENR1: + description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]" + fields: + - name: TIM2SMEN + description: TIM2 timer clock enable during CPU2 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC bus clock enable during CPU2 CSleep mode. + bit_offset: 10 + bit_size: 1 + - name: SPI2S2SMEN + description: SPI2S2 clock enable during CPU2 CSleep mode. + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during CPU2 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during CPU2 CSleep and CStop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during CPU2 CSleep and CStop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during CPU2 CSleep and CStop modes + bit_offset: 23 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 clock enable during CPU2 CSleep mode. + bit_offset: 29 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clock enable during CPU2 CSleep and CStop mode + bit_offset: 31 + bit_size: 1 +fieldset/C2APB1SMENR2: + description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]" + fields: + - name: LPUART1SMEN + description: Low power UART 1 clock enable during CPU2 CSleep and CStop mode + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. + bit_offset: 6 + bit_size: 1 +fieldset/C2APB2ENR: + description: "CPU2 APB2 peripheral clock enable register [dual core device only]" + fields: + - name: ADCEN + description: ADC clocks enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: CPU2 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU2 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU2 USART1clocks enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU2 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU2 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 +fieldset/C2APB2SMENR: + description: "CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]" + fields: + - name: ADCSMEN + description: ADC clocks enable during CPU2 Csleep and CStop modes + bit_offset: 9 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during CPU2 CSleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during CPU2 CSleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1clock enable during CPU2 CSleep and CStop mode + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during CPU2 CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clock enable during CPU2 CSleep mode + bit_offset: 18 + bit_size: 1 +fieldset/C2APB3ENR: + description: "CPU2 APB3 peripheral clock enable register [dual core device only]" + fields: + - name: SUBGHZSPIEN + description: CPU2 sub-GHz radio SPI clock enable + bit_offset: 0 + bit_size: 1 +fieldset/C2APB3SMENR: + description: "CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]" + fields: + - name: SUBGHZSPISMEN + description: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes + bit_offset: 0 + bit_size: 1 +fieldset/CCIPR: + description: Peripherals independent clock configuration register + fields: + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: SPI2S2SEL + description: SPI2S2 I2S clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: LPTIM3SEL + description: Low power timer 3 clock source selection + bit_offset: 22 + bit_size: 2 + - name: ADCSEL + description: ADC clock source selection + bit_offset: 28 + bit_size: 2 + - name: RNGSEL + description: RNG clock source selection + bit_offset: 30 + bit_size: 2 +fieldset/CFGR: + description: Clock configuration register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)" + bit_offset: 4 + bit_size: 4 + - name: PPRE1 + description: PCLK1 low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + - name: PPRE2 + description: PCLK2 high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + - name: HPREF + description: "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)" + bit_offset: 16 + bit_size: 1 + - name: PPRE1F + description: PCLK1 prescaler flag (APB1) + bit_offset: 17 + bit_size: 1 + - name: PPRE2F + description: PCLK2 prescaler flag (APB2) + bit_offset: 18 + bit_size: 1 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 +fieldset/CICR: + description: Clock interrupt clear register + fields: + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI16 ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE32 ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: HSE32 Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 +fieldset/CIER: + description: Clock interrupt enable register + fields: + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI16 ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE32 ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI16 ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE32 ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: HSE32 Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI range control selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + - name: HSION + description: HSI16 clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI16 always enable for peripheral kernel clocks. + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI16 automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSIKERDY + description: HSI16 kernel clock ready flag for peripherals requests. + bit_offset: 12 + bit_size: 1 + - name: HSEON + description: HSE32 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE32 clock ready flag + bit_offset: 17 + bit_size: 1 + - name: CSSON + description: HSE32 Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: HSE32 sysclk prescaler + bit_offset: 20 + bit_size: 1 + - name: HSEBYPPWR + description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. + bit_offset: 21 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register + fields: + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSIPRE + description: LSI frequency prescaler + bit_offset: 4 + bit_size: 1 + - name: MSISRANGE + description: MSI clock ranges + bit_offset: 8 + bit_size: 4 + - name: RFRSTF + description: Radio in reset status flag + bit_offset: 14 + bit_size: 1 + - name: RFRST + description: Radio reset + bit_offset: 15 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: RFILARSTF + description: Radio illegal access flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +fieldset/EXTCFGR: + description: Extended clock recovery register + fields: + - name: SHDHPRE + description: "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)" + bit_offset: 0 + bit_size: 4 + - name: C2HPRE + description: "[dual core device only] HCLK2 prescaler (CPU2)" + bit_offset: 4 + bit_size: 4 + - name: SHDHPREF + description: "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)" + bit_offset: 16 + bit_size: 1 + - name: C2HPREF + description: CLK2 prescaler flag (CPU2) + bit_offset: 17 + bit_size: 1 +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 24 + bit_size: 7 +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - name: PLLSRC + description: Main PLL entry clock source + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor for the main PLL input clock + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLPCLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLPCLK. + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: Main PLL PLLQCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLQCLK + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: Main PLL PLLRCLK output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLRCLK + bit_offset: 29 + bit_size: 3 diff --git a/data/registers/syscfg_wl5x.yaml b/data/registers/syscfg_wl5x.yaml new file mode 100644 index 0000000..a104742 --- /dev/null +++ b/data/registers/syscfg_wl5x.yaml @@ -0,0 +1,418 @@ +--- +block/SYSCFG: + description: System configuration controller + items: + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: CFGR2 + description: CFGR2 + byte_offset: 28 + fieldset: CFGR2 + - name: SWPR + description: SWPR + byte_offset: 32 + fieldset: SWPR + - name: SKR + description: SKR + byte_offset: 36 + access: Write + fieldset: SKR + - name: IMR1 + description: SYSCFG CPU1 interrupt mask register 1 + byte_offset: 256 + fieldset: IMR1 + - name: IMR2 + description: SYSCFG CPU1 interrupt mask register 2 + byte_offset: 260 + fieldset: IMR2 + - name: C2IMR1 + description: SYSCFG CPU2 interrupt mask register 1 + byte_offset: 264 + fieldset: C2IMR1 + - name: C2IMR2 + description: SYSCFG CPU2 interrupt mask register 2 + byte_offset: 268 + fieldset: C2IMR2 + - name: RFDCR + description: radio debug control register + byte_offset: 520 + fieldset: RFDCR +fieldset/C2IMR1: + description: SYSCFG CPU2 interrupt mask register 1 + fields: + - name: RTCSTAMPTAMPLSECSSIM + description: RTCSTAMPTAMPLSECSSIM + bit_offset: 0 + bit_size: 1 + - name: RTCALARMIM + description: RTCALARMIM + bit_offset: 1 + bit_size: 1 + - name: RTCSSRUIM + description: RTCSSRUIM + bit_offset: 2 + bit_size: 1 + - name: RTCWKUPIM + description: RTCWKUPIM + bit_offset: 3 + bit_size: 1 + - name: RCCIM + description: RCCIM + bit_offset: 5 + bit_size: 1 + - name: FLASHIM + description: FLASHIM + bit_offset: 6 + bit_size: 1 + - name: PKAIM + description: PKAIM + bit_offset: 8 + bit_size: 1 + - name: AESIM + description: AESIM + bit_offset: 10 + bit_size: 1 + - name: COMPIM + description: COMPIM + bit_offset: 11 + bit_size: 1 + - name: ADCIM + description: ADCIM + bit_offset: 12 + bit_size: 1 + - name: DACIM + description: DACIM + bit_offset: 13 + bit_size: 1 + - name: EXTI0IM + description: EXTI0IM + bit_offset: 16 + bit_size: 1 + - name: EXTI1IM + description: EXTI1IM + bit_offset: 17 + bit_size: 1 + - name: EXTI2IM + description: EXTI2IM + bit_offset: 18 + bit_size: 1 + - name: EXTI3IM + description: EXTI3IM + bit_offset: 19 + bit_size: 1 + - name: EXTI4IM + description: EXTI4IM + bit_offset: 20 + bit_size: 1 + - name: EXTI5IM + description: EXTI5IM + bit_offset: 21 + bit_size: 1 + - name: EXTI6IM + description: EXTI6IM + bit_offset: 22 + bit_size: 1 + - name: EXTI7IM + description: EXTI7IM + bit_offset: 23 + bit_size: 1 + - name: EXTI8IM + description: EXTI8IM + bit_offset: 24 + bit_size: 1 + - name: EXTI9IM + description: EXTI9IM + bit_offset: 25 + bit_size: 1 + - name: EXTI10IM + description: EXTI10IM + bit_offset: 26 + bit_size: 1 + - name: EXTI11IM + description: EXTI11IM + bit_offset: 27 + bit_size: 1 + - name: EXTI12IM + description: EXTI12IM + bit_offset: 28 + bit_size: 1 + - name: EXTI13IM + description: EXTI13IM + bit_offset: 29 + bit_size: 1 + - name: EXTI14IM + description: EXTI14IM + bit_offset: 30 + bit_size: 1 + - name: EXTI15IM + description: EXTI15IM + bit_offset: 31 + bit_size: 1 +fieldset/C2IMR2: + description: SYSCFG CPU2 interrupt mask register 2 + fields: + - name: DMA1CH1IM + description: DMA1CH1IM + bit_offset: 0 + bit_size: 1 + - name: DMA1CH2IM + description: DMA1CH2IM + bit_offset: 1 + bit_size: 1 + - name: DMA1CH3IM + description: DMA1CH3IM + bit_offset: 2 + bit_size: 1 + - name: DMA1CH4IM + description: DMA1CH4IM + bit_offset: 3 + bit_size: 1 + - name: DMA1CH5IM + description: DMA1CH5IM + bit_offset: 4 + bit_size: 1 + - name: DMA1CH6IM + description: DMA1CH6IM + bit_offset: 5 + bit_size: 1 + - name: DMA1CH7IM + description: DMA1CH7IM + bit_offset: 6 + bit_size: 1 + - name: DMA2CH1IM + description: DMA2CH1IM + bit_offset: 8 + bit_size: 1 + - name: DMA2CH2IM + description: DMA2CH2IM + bit_offset: 9 + bit_size: 1 + - name: DMA2CH3IM + description: DMA2CH3IM + bit_offset: 10 + bit_size: 1 + - name: DMA2CH4IM + description: DMA2CH4IM + bit_offset: 11 + bit_size: 1 + - name: DMA2CH5IM + description: DMA2CH5IM + bit_offset: 12 + bit_size: 1 + - name: DMA2CH6IM + description: DMA2CH6IM + bit_offset: 13 + bit_size: 1 + - name: DMA2CH7IM + description: DMA2CH7IM + bit_offset: 14 + bit_size: 1 + - name: DMAMUX1IM + description: DMAMUX1IM + bit_offset: 15 + bit_size: 1 + - name: PVM3IM + description: PVM3IM + bit_offset: 18 + bit_size: 1 + - name: PVDIM + description: PVDIM + bit_offset: 20 + bit_size: 1 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fast-mode Plus driving capability activation + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 +fieldset/CFGR2: + description: CFGR2 + fields: + - name: CLL + description: CPU1 LOCKUP (Hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 +fieldset/EXTICR: + description: external interrupt configuration register 4 + fields: + - name: EXTI + description: EXTI12 configuration bits + bit_offset: 0 + bit_size: 3 + array: + len: 4 + stride: 4 +fieldset/IMR1: + description: SYSCFG CPU1 interrupt mask register 1 + fields: + - name: RTCSTAMPTAMPLSECSSIM + description: RTCSTAMPTAMPLSECSSIM + bit_offset: 0 + bit_size: 1 + - name: RTCSSRUIM + description: RTCSSRUIM + bit_offset: 2 + bit_size: 1 + - name: EXTI5IM + description: EXTI5IM + bit_offset: 21 + bit_size: 1 + - name: EXTI6IM + description: EXTI6IM + bit_offset: 22 + bit_size: 1 + - name: EXTI7IM + description: EXTI7IM + bit_offset: 23 + bit_size: 1 + - name: EXTI8IM + description: EXTI8IM + bit_offset: 24 + bit_size: 1 + - name: EXTI9IM + description: EXTI9IM + bit_offset: 25 + bit_size: 1 + - name: EXTI10IM + description: EXTI10IM + bit_offset: 26 + bit_size: 1 + - name: EXTI11IM + description: EXTI11IM + bit_offset: 27 + bit_size: 1 + - name: EXTI12IM + description: EXTI12IM + bit_offset: 28 + bit_size: 1 + - name: EXTI13IM + description: EXTI13IM + bit_offset: 29 + bit_size: 1 + - name: EXTI14IM + description: EXTI14IM + bit_offset: 30 + bit_size: 1 + - name: EXTI15IM + description: EXTI15IM + bit_offset: 31 + bit_size: 1 +fieldset/IMR2: + description: SYSCFG CPU1 interrupt mask register 2 + fields: + - name: PVM3IM + description: PVM3IM + bit_offset: 18 + bit_size: 1 + - name: PVDIM + description: PVDIM + bit_offset: 20 + bit_size: 1 +fieldset/MEMRMP: + description: memory remap register + fields: + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 +fieldset/RFDCR: + description: radio debug control register + fields: + - name: RFTBSEL + description: radio debug test bus selection + bit_offset: 0 + bit_size: 1 +fieldset/SCSR: + description: SCSR + fields: + - name: SRAM2ER + description: SRAM2 erase + bit_offset: 0 + bit_size: 1 + - name: SRAMBSY + description: "SRAM1, SRAM2 and PKA SRAM busy by erase operation" + bit_offset: 1 + bit_size: 1 + - name: PKASRAMBSY + description: PKA SRAM busy by erase operation + bit_offset: 8 + bit_size: 1 +fieldset/SKR: + description: SKR + fields: + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 +fieldset/SWPR: + description: SWPR + fields: + - name: PWP + description: SRAM2 1Kbyte page 0 write protection + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/parse.py b/parse.py index 7a80770..5391a46 100644 --- a/parse.py +++ b/parse.py @@ -13,6 +13,12 @@ def removeprefix(value: str, prefix: str, /) -> str: else: return value[:] +def corename(d): + if m := re.match('.*Cortex-M(\d+)(\+?)', d): + name = "cm" + str(m.group(1)) + if m.group(2) == "+": + name += "p" + return name def removesuffix(value: str, suffix: str, /) -> str: if value.endswith(suffix): @@ -134,6 +140,8 @@ def parse_value(val, defines): def parse_header(f): irqs = {} defines = {} + cores = [] + cur_core = 'all' accum = '' for l in open(f, 'r', encoding='utf-8', errors='ignore'): @@ -144,11 +152,54 @@ def parse_header(f): continue accum = '' + # Scoped by a single core + if m:= re.match('.*if defined.*CORE_CM(\\d+)(PLUS)?.*', l): + cur_core = "cm" + str(m.group(1)) + if m.group(2) != None: + cur_core += "p" + #print("Cur core is ", cur_core, "matched", l) + found = False + for core in cores: + if core == cur_core: + found = True + if not found: + cores.append(cur_core) + #print("Switching to core", cur_core, "for", f) + elif m:= re.match('.*else.*', l): + cur_core = "all" + if m:= re.match('.*else.*CORE_CM(\\d+)(PLUS)?.*', l): + cur_core = "cm" + str(m.group(1)) + if m.group(2) != None: + cur_core += "p" + #print("Cur core is ", cur_core, "matched", l) + elif len(cores) > 1: + # Pick the second core assuming we've already parsed one + cur_core = cores[1] + + found = False + for core in cores: + if core == cur_core: + found = True + if not found: + cores.append(cur_core) + #print("Switching to core", cur_core, "for", f) + elif m:= re.match('.*endif.*', l): + #print("Switching to common core for", f) + cur_core = "all" + + + if cur_core not in irqs: + #print("Registering new core", cur_core) + irqs[cur_core] = {} + if cur_core not in defines: + defines[cur_core] = {} + if m := re.match('([a-zA-Z0-9_]+)_IRQn += (\\d+),? +/\\*!< (.*) \\*/', l): - irqs[m.group(1)] = int(m.group(2)) + #print("Found irq for", cur_core) + irqs[cur_core][m.group(1)] = int(m.group(2)) if m := re.match('#define +([0-9A-Za-z_]+)\\(', l): - defines[m.group(1)] = -1 + defines[cur_core][m.group(1)] = -1 if m := re.match('#define +([0-9A-Za-z_]+) +(.*)', l): name = m.group(1) val = m.group(2) @@ -156,10 +207,23 @@ def parse_header(f): if name == 'FLASH_SIZE': continue val = val.split('/*')[0].strip() - val = parse_value(val, defines) - defines[name] = val + val = parse_value(val, defines[cur_core]) + #print("Found define for", cur_core) + defines[cur_core][name] = val + + #print("Found", len(cores), "cores for", f) + #print("Found", len(irqs['all']), "shared interrupts for", f) + + if len(cores) == 0: + cores.append("all") + + for core in cores: + if core != "all": + irqs[core].update(irqs['all']) + defines[core].update(defines['all']) return { + 'cores': cores, 'interrupts': irqs, 'defines': defines, } @@ -240,19 +304,23 @@ perimap = [ ('.*:DAC:dacif_v3_0', 'dac_v2/DAC'), ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'), ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'), + ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'), ('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'), + ('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'), ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), + ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'), ('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'), ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'), ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'), + ('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl5x/DBGMCU'), ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), @@ -266,10 +334,10 @@ rng_clock_map = [ ('STM32L4.*:RNG:.*', 'AHB2'), ('STM32F4.*:RNG:.*', 'AHB2'), ('STM32H7.*:RNG:.*', 'AHB2'), - ('STM32WB55.*:RNG:.*', 'AHB3') + ('STM32WB55.*:RNG:.*', 'AHB3'), + ('STM32WL5.*:RNG:.*', 'AHB3') ] - def match_peri(peri): for r, block in perimap: if re.match(r, peri): @@ -368,16 +436,28 @@ def parse_chips(): core = r['Core'] family = r['@Family'] - # multicores have a list here. Just keep the first, to not break the schema. + cores = [] if isinstance(core, list): - core = core[0] + for core in core: + cores.append(OrderedDict( + { + 'name': corename(core), + 'peripherals': {}, + })) + else: + cores.append(OrderedDict( + { + 'name': corename(core), + 'peripherals': {}, + })) + if chip_name not in chips: chips[chip_name] = OrderedDict({ 'name': chip_name, 'family': family, 'line': r['@Line'], - 'core': core, + 'cores': cores, 'flash': flash, 'ram': ram, 'gpio_af': gpio_af, @@ -411,7 +491,6 @@ def parse_chips(): continue if pname.startswith('ADC'): if not 'ADC_COMMON' in peris: - print(f'adding ADC_COMMON') peris['ADC_COMMON'] = 'ADC_COMMON:'+removesuffix(ip['@Version'], '_Cube') peris[pname] = pkind pins[pname] = [] @@ -458,122 +537,138 @@ def parse_chips(): raise Exception("missing header for {}".format(chip_name)) h = headers_parsed[h] - chip['interrupts'] = h['interrupts'] + # print("Got", len(chip['cores']), "cores") + for core in chip['cores']: + core_name = core['name'] + if not core_name in h['interrupts'] or not core_name in h['defines']: + core_name = 'all' + #print("Defining for core", core_name) - peris = {} - for pname, pkind in chip['peripherals'].items(): - addr = h['defines'].get(pname) - if addr is None: - if pname == 'ADC_COMMON': - addr = h['defines'].get('ADC1_COMMON') - if addr is None: - addr = h['defines'].get('ADC12_COMMON') + # Gather all interrupts and defines for this core + interrupts = h['interrupts'][core_name] + defines = h['defines'][core_name] + + core['interrupts'] = interrupts + # print("INterrupts for", core, ":", interrupts) + #print("Defines for", core, ":", defines) + + peris = {} + for pname, pkind in chip['peripherals'].items(): + addr = defines.get(pname) + if addr is None: + if pname == 'ADC_COMMON': + addr = defines.get('ADC_COMMON') if addr is None: - addr = h['defines'].get('ADC123_COMMON') - if addr is None: - continue - - p = OrderedDict({ - 'address': addr, - 'kind': pkind, - }) - - if pname in clocks[rcc]: - p['clock'] = clocks[rcc][pname] - elif chip['family'] == 'STM32H7' and pname == "SPI6": - p['clock'] = "APB4" - - if block := match_peri(chip_name+':'+pname+':'+pkind): - p['block'] = block - - if pname in chip['pins']: - if len(chip['pins'][pname]) > 0: - p['pins'] = chip['pins'][pname] - - # RNG Clock definitions are not easily determined, so lookup in mapping - if block is not None and block.startswith("rng_"): - if (clock := match_rng_clock(chip_name+':'+pname+':'+pkind)) != None: - p['clock'] = clock - - peris[pname] = p - - family_extra = "data/extra/family/" + chip['family'] + ".yaml"; - if os.path.exists(family_extra) : - with open(family_extra) as extra_f: - extra = yaml.load(extra_f, Loader=yaml.SafeLoader) - for (extra_name, extra_p) in extra['peripherals'].items(): - peris[extra_name] = extra_p - - # Handle GPIO specially. - for p in range(20): - port = 'GPIO' + chr(ord('A')+p) - if addr := h['defines'].get(port + '_BASE'): - block = 'gpio_v2/GPIO' - if chip['family'] == 'STM32F1': - block = 'gpio_v1/GPIO' + addr = defines.get('ADC1_COMMON') + if addr is None: + addr = defines.get('ADC12_COMMON') + if addr is None: + addr = defines.get('ADC123_COMMON') + if addr is None: + continue p = OrderedDict({ 'address': addr, - 'block': block, + 'kind': pkind, }) - peris[port] = p - # Handle DMA specially. - for dma in ('DMA1', "DMA2"): - if addr := h['defines'].get(dma + '_BASE'): - block = 'dma_v1/DMA' - if chip['family'] in ('STM32F4', 'STM32F7', 'STM32H7'): - block = 'dma_v2/DMA' - p = OrderedDict({ + if pname in clocks[rcc]: + p['clock'] = clocks[rcc][pname] + elif chip['family'] == 'STM32H7' and pname == "SPI6": + p['clock'] = "APB4" + + if block := match_peri(chip_name+':'+pname+':'+pkind): + p['block'] = block + + if pname in chip['pins']: + if len(chip['pins'][pname]) > 0: + p['pins'] = chip['pins'][pname] + + # RNG Clock definitions are not easily determined, so lookup in mapping + if block is not None and block.startswith("rng_"): + if (clock := match_rng_clock(chip_name+':'+pname+':'+pkind)) != None: + p['clock'] = clock + + peris[pname] = p + + family_extra = "data/extra/family/" + chip['family'] + ".yaml"; + if os.path.exists(family_extra) : + with open(family_extra) as extra_f: + extra = yaml.load(extra_f, Loader=yaml.SafeLoader) + for (extra_name, extra_p) in extra['peripherals'].items(): + peris[extra_name] = extra_p + + # Handle GPIO specially. + for p in range(20): + port = 'GPIO' + chr(ord('A')+p) + if addr := defines.get(port + '_BASE'): + block = 'gpio_v2/GPIO' + if chip['family'] == 'STM32F1': + block = 'gpio_v1/GPIO' + + p = OrderedDict({ + 'address': addr, + 'block': block, + }) + peris[port] = p + # Handle DMA specially. + for dma in ('DMA1', "DMA2"): + if addr := defines.get(dma + '_BASE'): + block = 'dma_v1/DMA' + if chip['family'] in ('STM32F4', 'STM32F7', 'STM32H7'): + block = 'dma_v2/DMA' + + p = OrderedDict({ + 'address': addr, + 'block': block, + }) + peris[dma] = p + + # EXTI is not in the cubedb XMLs + if addr := defines.get('EXTI_BASE'): + peris['EXTI'] = OrderedDict({ 'address': addr, - 'block': block, + 'kind': 'EXTI', + 'block': 'exti_v1/EXTI', }) - peris[dma] = p - # EXTI is not in the cubedb XMLs - if addr := h['defines'].get('EXTI_BASE'): - peris['EXTI'] = OrderedDict({ - 'address': addr, - 'kind': 'EXTI', - 'block': 'exti_v1/EXTI', - }) + # FLASH is not in the cubedb XMLs + if addr := defines.get('FLASH_R_BASE'): + kind = 'FLASH:' + chip_name[:7] + '_flash_v1_0' + flash_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + flash_peri['block'] = block + peris['FLASH'] = flash_peri - # FLASH is not in the cubedb XMLs - if addr := h['defines'].get('FLASH_R_BASE'): - kind = 'FLASH:' + chip_name[:7] + '_flash_v1_0' - flash_peri = OrderedDict({ - 'address': addr, - 'kind': kind, - }) - if block := match_peri(kind): - flash_peri['block'] = block - peris['FLASH'] = flash_peri + # DBGMCU is not in the cubedb XMLs + if addr := defines.get('DBGMCU_BASE'): + kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0' + dbg_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + dbg_peri['block'] = block + peris['DBGMCU'] = dbg_peri - # DBGMCU is not in the cubedb XMLs - if addr := h['defines'].get('DBGMCU_BASE'): - kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0' - dbg_peri = OrderedDict({ - 'address': addr, - 'kind': kind, - }) - if block := match_peri(kind): - dbg_peri['block'] = block - peris['DBGMCU'] = dbg_peri - - # CRS is not in the cubedb XMLs - if addr := h['defines'].get('CRS_BASE'): - kind = 'CRS:' + chip_name[:7] + '_crs_v1_0' - crs_peri = OrderedDict({ - 'address': addr, - 'kind': kind, - }) - if block := match_peri(kind): - crs_peri['block'] = block - peris['CRS'] = crs_peri - chip['peripherals'] = peris + # CRS is not in the cubedb XMLs + if addr := defines.get('CRS_BASE'): + kind = 'CRS:' + chip_name[:7] + '_crs_v1_0' + crs_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + crs_peri['block'] = block + peris['CRS'] = crs_peri + core['peripherals'] = peris # remove all pins from the root of the chip before emitting. del chip['pins'] + del chip['peripherals'] with open('data/chips/'+chip_name+'.yaml', 'w') as f: f.write(yaml.dump(chip))