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New repo structure: includes stm32-metapac, doesn't commit generated files.

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This commit is contained in:
Dario Nieuwenhuis
2023-03-20 01:29:54 +01:00
parent f23cd93430
commit a2333b8afb
34 changed files with 1711 additions and 203 deletions
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192
data/header_map.yaml Normal file
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@ -0,0 +1,192 @@
STM32F030x6: STM32F030F4
STM32F030x8: STM32F030x8
STM32F031x6: STM32F031C4, STM32F031F4, STM32F031G4, STM32F031K4
STM32F038xx: STM32F038xx
STM32F042x6: STM32F042C4, STM32F042F4, STM32F042G4, STM32F042K4, STM32F042x6
STM32F048xx: STM32F048xx
STM32F051x8: STM32F051C4, STM32F051C6, STM32F051C8, STM32F051K4, STM32F051K6, STM32F051K8, STM32F051R4, STM32F051R6,
STM32F058xx: STM32F058xx
STM32F070x6: STM32F070x6
STM32F070xB: STM32F070xB
STM32F071xB: STM32F071C8, STM32F071V8, STM32F071xB
STM32F072xB: STM32F072C8, STM32F072R8, STM32F072V8, STM32F072xB
STM32F078xx: STM32F078xx
STM32F030xC: STM32F030xC
STM32F091xC: STM32F091CB, STM32F091RB, STM32F091VB, STM32F091xC
STM32F098xx: STM32F098xx
STM32F100xB: STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB, STM32F100VB
STM32F100xE: STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE, STM32F100ZE
STM32F101x6: STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6, STM32F101T6
STM32F101xB: STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB, STM32F101VB
STM32F101xE: STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE, STM32F101ZE
STM32F101xG: STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG, STM32F101ZG
STM32F102x6: STM32F102C4, STM32F102R4, STM32F102C6, STM32F102R6
STM32F102xB: STM32F102C8, STM32F102R8, STM32F102CB, STM32F102RB
STM32F103x6: STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6, STM32F103T6
STM32F103xB: STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB, STM32F103VB
STM32F103xE: STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE, STM32F103ZE
STM32F103xG: STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG, STM32F103ZG
STM32F105xC: STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC, STM32F105VC
STM32F107xC: STM32F107RB, STM32F107VB, STM32F107RC, STM32F107VC
STM32F205xx: STM32F205RG, STM32F205VG, STM32F205ZG, STM32F205RF, STM32F205VF, STM32F205ZF, STM32F205RE, STM32F205VE, STM32F205ZE, STM32F205RC, STM32F205VC, STM32F205ZC, STM32F205RB, STM32F205VB
STM32F215xx: STM32F215RG, STM32F215VG, STM32F215ZG, STM32F215RE, STM32F215VE, STM32F215ZE
STM32F207xx: STM32F207VG, STM32F207ZG, STM32F207IG, STM32F207VF, STM32F207ZF, STM32F207IF, STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC, STM32F207IC
STM32F217xx: STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE, STM32F217IE
STM32F301x8: STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8, STM32F301R6, STM32F301R8
STM32F302x8: STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8, STM32F302R6, STM32F302R8
STM32F302xC: STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB, STM32F302VC
STM32F302xE: STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD, STM32F302VD, STM32F302ZD
STM32F303x8: STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, STM32F303R6, STM32F303R8
STM32F303xC: STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB, STM32F303VC
STM32F303xE: STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD, STM32F303VD, STM32F303ZD
STM32F373xC: STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC, STM32F373V8, STM32F373VB, STM32F373VC
STM32F334x8: STM32F334K4, STM32F334K6, STM32F334K8, STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6, STM32F334R8
STM32F318xx: STM32F318K8, STM32F318C8
STM32F328xx: STM32F328C8, STM32F328R8
STM32F358xx: STM32F358CC, STM32F358RC, STM32F358VC
STM32F378xx: STM32F378CC, STM32F378RC, STM32F378VC
STM32F398xx: STM32F398VE
STM32F405xx: STM32F405RG, STM32F405VG, STM32F405ZG
STM32F415xx: STM32F415RG, STM32F415VG, STM32F415ZG
STM32F407xx: STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE
STM32F417xx: STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG, STM32F417IE
STM32F427xx: STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II
STM32F437xx: STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II
STM32F429xx: STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, STM32F429IG, STM32F429II
STM32F439xx: STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, STM32F439IG, STM32F439II
STM32F401xC: STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC
STM32F401xE: STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE, STM32F401VE
STM32F410Tx: STM32F410T8, STM32F410TB
STM32F410Cx: STM32F410C8, STM32F410CB
STM32F410Rx: STM32F410R8, STM32F410RB
STM32F411xE: STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE, STM32F411VE
STM32F446xx: STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, STM32F446ZE
STM32F469xx: STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE, STM32F469NE
STM32F479xx: STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG, STM32F479NG
STM32F412Cx: STM32F412CEU, STM32F412CGU
STM32F412Zx: STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ
STM32F412Vx: STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH
STM32F412Rx: STM32F412RET, STM32F412RGT, STM32F412REY, STM32F412RGY
STM32F413xx: STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, STM32F413RG, STM32F413VG, STM32F413ZG
STM32F423xx: STM32F423CH, STM32F423RH, STM32F423VH, STM32F423ZH
STM32F756xx: STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG
STM32F746xx: STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG
STM32F745xx: STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG
STM32F765xx: STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG
STM32F767xx: STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI
STM32F769xx: STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, STM32F769NG, STM32F769NI, STM32F768AI
STM32F777xx: STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI
STM32F779xx: STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI
STM32F722xx: STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC, STM32F722VC, STM32F722RC
STM32F723xx: STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC
STM32F732xx: STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE
STM32F733xx: STM32F733IE, STM32F733ZE, STM32F733VE
STM32F730xx: STM32F730R, STM32F730V, STM32F730Z, STM32F730I
STM32F750xx: STM32F750V, STM32F750Z, STM32F750N
STM32L010x4: STM32L010K4, STM32L010F4
STM32L010x6: STM32L010C6
STM32L010x8: STM32L010K8, STM32L010R8
STM32L010xB: STM32L010RB
STM32L021xx: STM32L021D4, STM32L021F4, STM32L021G4, STM32L021K4
STM32L031xx: STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6
STM32L041xx: STM32L041C6, STM32L041K6, STM32L041G6, STM32L041F6, STM32L041E6
STM32L051xx: STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8, STM32L051K6, STM32L051T6, STM32L051T8
STM32L052xx: STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8, STM32L052T6, STM32L052T8
STM32L053xx: STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8
STM32L062xx: STM32L062K8
STM32L063xx: STM32L063C8, STM32L063R8
STM32L071xx: STM32L071V8, STM32L071K8, STM32L071VB, STM32L071RB, STM32L071CB, STM32L071KB, STM32L071VZ, STM32L071RZ, STM32L071CZ, STM32L071KZ, STM32L071C8
STM32L072xx: STM32L072V8, STM32L072VB, STM32L072RB, STM32L072CB, STM32L072VZ, STM32L072RZ, STM32L072CZ, STM32L072KB, STM32L072KZ
STM32L073xx: STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ, STM32L073CB, STM32L073CZ
STM32L081xx: STM32L081CB, STM32L081CZ, STM32L081KZ
STM32L082xx: STM32L082KB, STM32L082KZ, STM32L082CZ
STM32L083xx: STM32L083V8, STM32L083VB, STM32L083RB, STM32L083VZ, STM32L083RZ, STM32L083CB, STM32L083CZ
STM32L100xB: STM32L100C6, STM32L100R8, STM32L100RB
STM32L100xBA: STM32L100C6-A, STM32L100R8-A, STM32L100RB-A
STM32L100xC: STM32L100RC
STM32L151xB: STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB, STM32L151VB
STM32L151xBA: STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A, STM32L151VB-A
STM32L151xC: STM32L151CC, STM32L151UC, STM32L151RC, STM32L151VC
STM32L151xCA: STM32L151RC-A, STM32L151VC-A, STM32L151QC, STM32L151ZC
STM32L151xD: STM32L151QD, STM32L151RD, STM32L151VD, STM32L151ZD
STM32L151xDX: STM32L151VD-X
STM32L151xE: STM32L151QE, STM32L151RE, STM32L151VE, STM32L151ZE
STM32L152xB: STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB, STM32L152VB
STM32L152xBA: STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A, STM32L152VB-A
STM32L152xC: STM32L152CC, STM32L152UC, STM32L152RC, STM32L152VC
STM32L152xCA: STM32L152RC-A, STM32L152VC-A, STM32L152QC, STM32L152ZC
STM32L152xD: STM32L152QD, STM32L152RD, STM32L152VD, STM32L152ZD
STM32L152xDX: STM32L152VD-X
STM32L152xE: STM32L152QE, STM32L152RE, STM32L152VE, STM32L152ZE
STM32L162xC: STM32L162RC, STM32L162VC
STM32L162xCA: STM32L162RC-A, STM32L162VC-A, STM32L162QC, STM32L162ZC
STM32L162xD: STM32L162QD, STM32L162RD, STM32L162VD, STM32L162ZD
STM32L162xDX: STM32L162VD-X
STM32L162xE: STM32L162RE, STM32L162VE, STM32L162ZE
STM32L412xx: STM32L412xx
STM32L422xx: STM32L422xx
STM32L431xx: STM32L431xx
STM32L432xx: STM32L432xx
STM32L433xx: STM32L433xx
STM32L442xx: STM32L442xx
STM32L443xx: STM32L443xx
STM32L451xx: STM32L451xx
STM32L452xx: STM32L452xx
STM32L462xx: STM32L462xx
STM32L471xx: STM32L471xx
STM32L475xx: STM32L475xx
STM32L476xx: STM32L476xx
STM32L485xx: STM32L485xx
STM32L486xx: STM32L486xx
STM32L496xx: STM32L496xx
STM32L4A6xx: STM32L4A6xx
STM32L4P5xx: STM32L4Q5xx
STM32L4R5xx: STM32L4R5xx
STM32L4R7xx: STM32L4R7xx
STM32L4R9xx: STM32L4R9xx
STM32L4S5xx: STM32L4S5xx
STM32L4S7xx: STM32L4S7xx
STM32L4S9xx: STM32L4S9xx
STM32L552xx: STM32L552xx
STM32L562xx: STM32L562xx
STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI
STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI
STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI
STM32H750xx: STM32H750V, STM32H750I, STM32H750X
STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI
STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI
STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI
STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI
STM32H7B0xx: STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ
STM32H7A3xx: STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6
STM32H7A3xxQ: STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q
STM32H7B3xx: STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6
STM32H7B3xxQ: STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q
STM32H735xx: STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6
STM32H733xx: STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6
STM32H730xx: STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6
STM32H730xxQ: STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q
STM32H725xx: STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6
STM32H723xx: STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6
STM32G0B0xx: STM32G0B0xx
STM32G0B1xx: STM32G0B1xx
STM32G0C1xx: STM32G0C1xx
STM32G070xx: STM32G070xx
STM32G071xx: STM32G071xx
STM32G081xx: STM32G081xx
STM32G050xx: STM32G050xx
STM32G051xx: STM32G051xx
STM32G061xx: STM32G061xx
STM32G030xx: STM32G030xx
STM32G031xx: STM32G031xx
STM32G041xx: STM32G041xx
STM32G431xx: STM32G431xx
STM32G441xx: STM32G441xx
STM32G471xx: STM32G471xx
STM32G473xx: STM32G473xx
STM32G483xx: STM32G483xx
STM32G474xx: STM32G474xx
STM32G484xx: STM32G484xx
STM32G491xx: STM32G491xx
STM32G4A1xx: STM32G4A1xx
STM32GBK1CB: STM32GBK1CB

18
data/registers/usb_v4.yaml
View File

@ -97,7 +97,7 @@ fieldset/CNTR:
bit_offset: 2
bit_size: 1
- name: FSUSP
description: "Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set."
description: "Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set."
bit_offset: 3
bit_size: 1
- name: RESUME
@ -171,7 +171,7 @@ fieldset/EPR:
bit_offset: 0
bit_size: 4
- name: STAT_TX
description: "Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be “VALID” or “DISABLED”. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALL’ or 'NAK’ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC)"
description: "Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be VALID or DISABLED. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to STALL or NAK for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC)"
bit_offset: 4
bit_size: 2
enum: STAT
@ -184,11 +184,11 @@ fieldset/EPR:
bit_offset: 7
bit_size: 1
- name: EP_KIND
description: "endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALL’ instead of 'ACK’. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required."
description: "endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required."
bit_offset: 8
bit_size: 1
- name: EP_TYPE
description: "USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers"
description: "USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers"
bit_offset: 9
bit_size: 2
enum: EP_TYPE
@ -197,7 +197,7 @@ fieldset/EPR:
bit_offset: 11
bit_size: 1
- name: STAT_RX
description: "Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only “VALID” or “DISABLED”, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALL’ or 'NAK’ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: -\tDISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. -\tVALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate."
description: "Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALL or 'NAK for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: -\tDISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. -\tVALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate."
bit_offset: 12
bit_size: 2
enum: STAT
@ -218,7 +218,7 @@ fieldset/EPR:
bit_offset: 23
bit_size: 1
- name: LS_EP
description: Low speed endpoint – Host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint.
description: Low speed endpoint Host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint.
bit_offset: 24
bit_size: 1
- name: ERR_TX
@ -269,11 +269,11 @@ fieldset/ISTR:
bit_offset: 7
bit_size: 1
- name: ESOF
description: "Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect."
description: "Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect."
bit_offset: 8
bit_size: 1
- name: SOF
description: "Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect."
description: "Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect."
bit_offset: 9
bit_size: 1
- name: RESET
@ -281,7 +281,7 @@ fieldset/ISTR:
bit_offset: 10
bit_size: 1
- name: SUSP
description: "Suspend mode request This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect."
description: "Suspend mode request This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect."
bit_offset: 11
bit_size: 1
- name: WKUP