WL5/WLE: rename DAC1EN to DACEN in RCC, per reference manual and peripheral name

data/registers/rcc_wl5.yaml

@@ -417,8 +417,8 @@ fieldset/APB1ENR1:
     description: CPU1 I2C3 clocks enable
     bit_offset: 23
     bit_size: 1
-  - name: DAC1EN
-    description: CPU1 DAC1 clock enable
+  - name: DACEN
+    description: CPU1 DAC clock enable
     bit_offset: 29
     bit_size: 1
   - name: LPTIM1EN
@@ -468,7 +468,7 @@ fieldset/APB1RSTR1:
     bit_offset: 23
     bit_size: 1
   - name: DACRST
-    description: DAC1 reset
+    description: DAC reset
     bit_offset: 29
     bit_size: 1
   - name: LPTIM1RST
@@ -526,7 +526,7 @@ fieldset/APB1SMENR1:
     bit_offset: 23
     bit_size: 1
   - name: DACSMEN
-    description: DAC1 clock enable during CPU1 CSleep mode.
+    description: DAC clock enable during CPU1 CSleep mode.
     bit_offset: 29
     bit_size: 1
   - name: LPTIM1SMEN
@@ -868,8 +868,8 @@ fieldset/C2APB1ENR1:
     description: CPU2 I2C3 clocks enable
     bit_offset: 23
     bit_size: 1
-  - name: DAC1EN
-    description: CPU2 DAC1 clock enable
+  - name: DACEN
+    description: CPU2 DAC clock enable
     bit_offset: 29
     bit_size: 1
   - name: LPTIM1EN
@@ -922,8 +922,8 @@ fieldset/C2APB1SMENR1:
     description: I2C3 clock enable during CPU2 CSleep and CStop modes
     bit_offset: 23
     bit_size: 1
-  - name: DAC1SMEN
-    description: DAC1 clock enable during CPU2 CSleep mode.
+  - name: DACSMEN
+    description: DAC clock enable during CPU2 CSleep mode.
     bit_offset: 29
     bit_size: 1
   - name: LPTIM1SMEN

data/registers/rcc_wle.yaml

@@ -353,8 +353,8 @@ fieldset/APB1ENR1:
     description: CPU1 I2C3 clocks enable
     bit_offset: 23
     bit_size: 1
-  - name: DAC1EN
-    description: CPU1 DAC1 clock enable
+  - name: DACEN
+    description: CPU1 DAC clock enable
     bit_offset: 29
     bit_size: 1
   - name: LPTIM1EN