diff --git a/Cargo.lock b/Cargo.lock index d972fbc..413eae6 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -12,10 +12,58 @@ dependencies = [ ] [[package]] -name = "anyhow" -version = "1.0.71" +name = "anstream" +version = "0.6.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9c7d0618f0e0b7e8ff11427422b64564d5fb0be1940354bfe2e0529b18a9d9b8" +checksum = "d664a92ecae85fd0a7392615844904654d1d5f5514837f471ddef4a057aba1b6" +dependencies = [ + "anstyle", + "anstyle-parse", + "anstyle-query", + "anstyle-wincon", + "colorchoice", + "utf8parse", +] + +[[package]] +name = "anstyle" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7079075b41f533b8c61d2a4d073c4676e1f8b249ff94a393b0595db304e0dd87" + +[[package]] +name = "anstyle-parse" +version = "0.2.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c75ac65da39e5fe5ab759307499ddad880d724eed2f6ce5b5e8a26f4f387928c" +dependencies = [ + "utf8parse", +] + +[[package]] +name = "anstyle-query" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e28923312444cdd728e4738b3f9c9cac739500909bb3d3c94b43551b16517648" +dependencies = [ + "windows-sys", +] + +[[package]] +name = "anstyle-wincon" +version = "3.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1cd54b81ec8d6180e24654d0b371ad22fc3dd083b6ff8ba325b72e00c87660a7" +dependencies = [ + "anstyle", + "windows-sys", +] + +[[package]] +name = "anyhow" +version = "1.0.79" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "080e9890a082662b09c1ad45f567faeeb47f22b5fb23895fbe1e651e718e25ca" [[package]] name = "atty" @@ -36,9 +84,9 @@ checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" [[package]] name = "bitflags" -version = "1.3.2" +version = "2.4.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +checksum = "327762f6e5a765692301e5bb513e0d9fef63be86bbc14528052b1cd3e6f03e07" [[package]] name = "cfg-if" @@ -49,59 +97,66 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" [[package]] name = "chiptool" version = "0.1.0" -source = "git+https://github.com/embassy-rs/chiptool?rev=0621765f915cedb0a9242a888c1909374ebbf4fa#0621765f915cedb0a9242a888c1909374ebbf4fa" +source = "git+https://github.com/embassy-rs/chiptool?rev=67c6adc50306696e664ba5f71cd4db9d6dd9c46b#67c6adc50306696e664ba5f71cd4db9d6dd9c46b" dependencies = [ "anyhow", "clap", - "env_logger 0.9.3", + "env_logger 0.10.1", "inflections", "log", "proc-macro2", "quote", "regex", "serde", - "serde_yaml 0.8.26", + "serde_yaml", "svd-parser", ] [[package]] name = "clap" -version = "3.2.25" +version = "4.4.13" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4ea181bf566f71cb9a5d17a59e1871af638180a18fb0035c92ae62b705207123" +checksum = "52bdc885e4cacc7f7c9eedc1ef6da641603180c783c41a15c264944deeaab642" dependencies = [ - "atty", - "bitflags", + "clap_builder", "clap_derive", +] + +[[package]] +name = "clap_builder" +version = "4.4.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fb7fb5e4e979aec3be7791562fcba452f94ad85e954da024396433e0e25a79e9" +dependencies = [ + "anstream", + "anstyle", "clap_lex", - "indexmap 1.9.3", - "once_cell", "strsim", - "termcolor", - "textwrap", ] [[package]] name = "clap_derive" -version = "3.2.25" +version = "4.4.7" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ae6371b8bdc8b7d3959e9cf7b22d4435ef3e79e138688421ec654acf8c81b008" +checksum = "cf9804afaaf59a91e75b022a30fb7229a7901f60c755489cc61c9b423b836442" dependencies = [ "heck", - "proc-macro-error", "proc-macro2", "quote", - "syn 1.0.109", + "syn 2.0.48", ] [[package]] name = "clap_lex" -version = "0.2.4" +version = "0.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2850f2f5a82cbf437dd5af4d49848fbdfc27c157c3d010345776f952765261c5" -dependencies = [ - "os_str_bytes", -] +checksum = "702fc72eb24e5a1e48ce58027a675bc24edd52096d5397d4aea7c6dd9eca0bd1" + +[[package]] +name = "colorchoice" +version = "1.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "acbf1af155f9b9ef647e42cdc158db4b64a1b61f743629225fde6f3e0be2a7c7" [[package]] name = "crossbeam-channel" @@ -167,12 +222,12 @@ dependencies = [ [[package]] name = "env_logger" -version = "0.9.3" +version = "0.10.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a12e6657c4c97ebab115a42dcee77225f7f482cdd841cf7088c657a42e9e00e7" +checksum = "95b3f3e67048839cb0d0781f445682a35113da7121f7c949db0e2be96a4fbece" dependencies = [ - "atty", "humantime 2.1.0", + "is-terminal", "log", "regex", "termcolor", @@ -184,18 +239,22 @@ version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "88bffebc5d80432c9b140ee17875ff173a8ab62faad5b257da912bd2f6c1c0a1" +[[package]] +name = "errno" +version = "0.3.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a258e46cdc063eb8519c00b9fc845fc47bcfca4130e2f08e88665ceda8474245" +dependencies = [ + "libc", + "windows-sys", +] + [[package]] name = "glob" version = "0.3.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "d2fabcfbdc87f4758337ca535fb41a6d701b65693ce38287d856d1674551ec9b" -[[package]] -name = "hashbrown" -version = "0.12.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8a9ee70c43aaf417c914396645a0fa852624801b24ebb7ae78fe8272889ac888" - [[package]] name = "hashbrown" version = "0.14.0" @@ -226,6 +285,12 @@ dependencies = [ "libc", ] +[[package]] +name = "hermit-abi" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d77f7ec81a6d05a3abb01ab6eb7590f6083d08449fe5a1c8b1e620283546ccb7" + [[package]] name = "humantime" version = "1.3.0" @@ -241,16 +306,6 @@ version = "2.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9a3a5bfb195931eeb336b2a7b4d761daec841b97f947d34394601737a7bba5e4" -[[package]] -name = "indexmap" -version = "1.9.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bd070e393353796e801d209ad339e89596eb4c8d430d18ede6a1cced8fafbd99" -dependencies = [ - "autocfg", - "hashbrown 0.12.3", -] - [[package]] name = "indexmap" version = "2.0.0" @@ -258,7 +313,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "d5477fe2230a79769d8dc68e0eabf5437907c0457a5614a9e8dddb67f65eb65d" dependencies = [ "equivalent", - "hashbrown 0.14.0", + "hashbrown", ] [[package]] @@ -267,6 +322,17 @@ version = "1.1.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "a257582fdcde896fd96463bf2d40eefea0580021c0712a0e2b028b60b47a837a" +[[package]] +name = "is-terminal" +version = "0.4.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0bad00257d07be169d870ab665980b06cdb366d792ad690bf2e76876dc503455" +dependencies = [ + "hermit-abi 0.3.3", + "rustix", + "windows-sys", +] + [[package]] name = "itertools" version = "0.10.5" @@ -284,15 +350,15 @@ checksum = "453ad9f582a441959e5f0d088b02ce04cfe8d51a8eaf077f12ac6d3e94164ca6" [[package]] name = "libc" -version = "0.2.147" +version = "0.2.152" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b4668fb0ea861c1df094127ac5f1da3409a82116a4ba74fca2e58ef927159bb3" +checksum = "13e3bf6590cbc649f4d1a3eefc9d5d6eb746f5200ffb04e5e142700b8faa56e7" [[package]] -name = "linked-hash-map" -version = "0.5.6" +name = "linux-raw-sys" +version = "0.4.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0717cef1bc8b636c6e1c1bbdefc09e6322da8a9321966e8928ef80d20f7f770f" +checksum = "c4cd1a83af159aa67994778be9070f0ae1bd732942279cabb14f86f986a21456" [[package]] name = "log" @@ -302,9 +368,9 @@ checksum = "b06a4cde4c0f271a446782e3eff8de789548ce57dbc8eca9292c27f4a42004b4" [[package]] name = "memchr" -version = "2.5.0" +version = "2.7.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2dffe52ecf27772e601905b7522cb4ef790d2cc203488bbd0e2fe85fcb74566d" +checksum = "523dc4f511e55ab87b694dc30d0f820d60906ef06413f93d4d7a1385599cc149" [[package]] name = "memoffset" @@ -407,12 +473,6 @@ version = "1.18.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "dd8b5dd2ae5ed71462c540258bedcb51965123ad7e7ccf4b9a8cafaa4a63576d" -[[package]] -name = "os_str_bytes" -version = "6.5.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4d5d9eb14b174ee9aa2ef96dc2b94637a2d4b6e7cb873c7e171f0c20c6cf3eac" - [[package]] name = "pretty_env_logger" version = "0.4.0" @@ -423,35 +483,11 @@ dependencies = [ "log", ] -[[package]] -name = "proc-macro-error" -version = "1.0.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5ce38c" -dependencies = [ - "proc-macro-error-attr", - "proc-macro2", - "quote", - "syn 1.0.109", - "version_check", -] - -[[package]] -name = "proc-macro-error-attr" -version = "1.0.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35f869" -dependencies = [ - "proc-macro2", - "quote", - "version_check", -] - [[package]] name = "proc-macro2" -version = "1.0.63" +version = "1.0.76" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7b368fba921b0dce7e60f5e04ec15e565b3303972b42bcfde1d0713b881959eb" +checksum = "95fc56cda0b5c3325f5fbbd7ff9fda9e02bb00bb3dac51252d2f1bfa1cb8cc8c" dependencies = [ "unicode-ident", ] @@ -474,9 +510,9 @@ dependencies = [ [[package]] name = "quote" -version = "1.0.28" +version = "1.0.35" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1b9ab9c7eadfd8df19006f1cf1a4aed13540ed5cbc047010ece5826e10825488" +checksum = "291ec9ab5efd934aaf503a6466c5d5251535d108ee747472c3977cc5acc868ef" dependencies = [ "proc-macro2", ] @@ -511,9 +547,21 @@ checksum = "a0d51660a68078997855ba5602f73ab3a5031bd7ad480a9d4c90fbbf04e1fff0" [[package]] name = "regex" -version = "1.8.4" +version = "1.9.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d0ab3ca65655bb1e41f2a8c8cd662eb4fb035e67c3f78da1d61dffe89d07300f" +checksum = "ebee201405406dbf528b8b672104ae6d6d63e6d118cb10e4d51abbc7b58044ff" +dependencies = [ + "aho-corasick", + "memchr", + "regex-automata", + "regex-syntax", +] + +[[package]] +name = "regex-automata" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "59b23e92ee4318893fa3fe3e6fb365258efbfe6ac6ab30f090cdcbb7aa37efa9" dependencies = [ "aho-corasick", "memchr", @@ -522,9 +570,28 @@ dependencies = [ [[package]] name = "regex-syntax" -version = "0.7.2" +version = "0.7.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "436b050e76ed2903236f032a59761c1eb99e1b0aead2c257922771dab1fc8c78" +checksum = "dbb5fb1acd8a1a18b3dd5be62d25485eb770e05afb408a9627d14d451bae12da" + +[[package]] +name = "roxmltree" +version = "0.19.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3cd14fd5e3b777a7422cca79358c57a8f6e3a703d9ac187448d0daf220c2407f" + +[[package]] +name = "rustix" +version = "0.38.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72e572a5e8ca657d7366229cdde4bd14c4eb5499a9573d4d366fe1b599daa316" +dependencies = [ + "bitflags", + "errno", + "libc", + "linux-raw-sys", + "windows-sys", +] [[package]] name = "ryu" @@ -540,22 +607,22 @@ checksum = "d29ab0c6d3fc0ee92fe66e2d99f700eab17a8d57d1c1d3b748380fb20baa78cd" [[package]] name = "serde" -version = "1.0.164" +version = "1.0.195" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9e8c8cf938e98f769bc164923b06dce91cea1751522f46f8466461af04c9027d" +checksum = "63261df402c67811e9ac6def069e4786148c4563f4b50fd4bf30aa370d626b02" dependencies = [ "serde_derive", ] [[package]] name = "serde_derive" -version = "1.0.164" +version = "1.0.195" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d9735b638ccc51c28bf6914d90a2e9725b377144fc612c49a611fddd1b631d68" +checksum = "46fe8f8603d81ba86327b23a2e9cdf49e1255fb94a4c5f297f6ee0547178ea2c" dependencies = [ "proc-macro2", "quote", - "syn 2.0.22", + "syn 2.0.48", ] [[package]] @@ -571,23 +638,11 @@ dependencies = [ [[package]] name = "serde_yaml" -version = "0.8.26" +version = "0.9.30" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "578a7433b776b56a35785ed5ce9a7e777ac0598aac5a6dd1b4b18a307c7fc71b" +checksum = "b1bf28c79a99f70ee1f1d83d10c875d2e70618417fda01ad1785e027579d9d38" dependencies = [ - "indexmap 1.9.3", - "ryu", - "serde", - "yaml-rust", -] - -[[package]] -name = "serde_yaml" -version = "0.9.22" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "452e67b9c20c37fa79df53201dc03839651086ed9bbe92b3ca585ca9fdaa7d85" -dependencies = [ - "indexmap 2.0.0", + "indexmap", "itoa", "ryu", "serde", @@ -610,7 +665,7 @@ dependencies = [ "regex", "serde", "serde_json", - "serde_yaml 0.9.22", + "serde_yaml", "stm32-data-serde", ] @@ -655,16 +710,25 @@ checksum = "73473c0e59e6d5812c5dfe2a064a6444949f089e20eec9a2e5506596494e4623" [[package]] name = "svd-parser" -version = "0.10.2" +version = "0.14.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "697e7645ad9f5311fe3d872d094b135627b1616aea9e1573dddd28ca522579b9" +checksum = "3d17a2c2ef5aa450e80d714232a5932e7d8a39cac092e9e9ef8411bc833de3c4" dependencies = [ "anyhow", + "roxmltree", + "svd-rs", + "thiserror", +] + +[[package]] +name = "svd-rs" +version = "0.14.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1c82f375efa1d0145467e6cc98fa0e4e1a3f3d497cece4bcdda247f4904a77d4" +dependencies = [ "once_cell", - "rayon", "regex", "thiserror", - "xmltree", ] [[package]] @@ -680,9 +744,9 @@ dependencies = [ [[package]] name = "syn" -version = "2.0.22" +version = "2.0.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2efbeae7acf4eabd6bcdcbd11c92f45231ddda7539edc7806bd1a04a03b24616" +checksum = "0f3531638e407dfc0814761abb7c00a5b54992b849452a0646b7f65c9f770f3f" dependencies = [ "proc-macro2", "quote", @@ -698,12 +762,6 @@ dependencies = [ "winapi-util", ] -[[package]] -name = "textwrap" -version = "0.16.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "222a222a5bfe1bba4a77b45ec488a741b3cb8872e5e499451fd7d0129c9c7c3d" - [[package]] name = "thiserror" version = "1.0.40" @@ -721,7 +779,7 @@ checksum = "f9456a42c5b0d803c8cd86e73dd7cc9edd429499f37a3550d286d5e86720569f" dependencies = [ "proc-macro2", "quote", - "syn 2.0.22", + "syn 2.0.48", ] [[package]] @@ -732,15 +790,15 @@ checksum = "b15811caf2415fb889178633e7724bad2509101cde276048e013b9def5e51fa0" [[package]] name = "unsafe-libyaml" -version = "0.2.8" +version = "0.2.10" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1865806a559042e51ab5414598446a5871b561d21b6764f2eabb0dd481d880a6" +checksum = "ab4c90930b95a82d00dc9e9ac071b4991924390d46cbd0dfe566148667605e4b" [[package]] -name = "version_check" -version = "0.9.4" +name = "utf8parse" +version = "0.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f" +checksum = "711b9620af191e0cdc7468a8d14e709c3dcdb115b36f838e601583af800a370a" [[package]] name = "winapi" @@ -774,28 +832,67 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f" [[package]] -name = "xml-rs" -version = "0.7.0" +name = "windows-sys" +version = "0.52.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3c1cb601d29fe2c2ac60a2b2e5e293994d87a1f6fa9687a31a15270f909be9c2" +checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" dependencies = [ - "bitflags", + "windows-targets", ] [[package]] -name = "xmltree" -version = "0.8.0" +name = "windows-targets" +version = "0.52.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ff8eaee9d17062850f1e6163b509947969242990ee59a35801af437abe041e70" +checksum = "8a18201040b24831fbb9e4eb208f8892e1f50a37feb53cc7ff887feb8f50e7cd" dependencies = [ - "xml-rs", + "windows_aarch64_gnullvm", + "windows_aarch64_msvc", + "windows_i686_gnu", + "windows_i686_msvc", + "windows_x86_64_gnu", + "windows_x86_64_gnullvm", + "windows_x86_64_msvc", ] [[package]] -name = "yaml-rust" -version = "0.4.5" +name = "windows_aarch64_gnullvm" +version = "0.52.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "56c1936c4cc7a1c9ab21a1ebb602eb942ba868cbd44a99cb7cdc5892335e1c85" -dependencies = [ - "linked-hash-map", -] +checksum = "cb7764e35d4db8a7921e09562a0304bf2f93e0a51bfccee0bd0bb0b666b015ea" + +[[package]] +name = "windows_aarch64_msvc" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bbaa0368d4f1d2aaefc55b6fcfee13f41544ddf36801e793edbbfd7d7df075ef" + +[[package]] +name = "windows_i686_gnu" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a28637cb1fa3560a16915793afb20081aba2c92ee8af57b4d5f28e4b3e7df313" + +[[package]] +name = "windows_i686_msvc" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ffe5e8e31046ce6230cc7215707b816e339ff4d4d67c65dffa206fd0f7aa7b9a" + +[[package]] +name = "windows_x86_64_gnu" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3d6fa32db2bc4a2f5abeacf2b69f7992cd09dca97498da74a151a3132c26befd" + +[[package]] +name = "windows_x86_64_gnullvm" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1a657e1e9d3f514745a572a6846d3c7aa7dbe1658c056ed9c3344c4109a6949e" + +[[package]] +name = "windows_x86_64_msvc" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dff9641d1cd4be8d1a070daf9e3773c5f67e78b4d9d42263020c057706765c04" diff --git a/data/registers/adc_f3_v1_1.yaml b/data/registers/adc_f3_v1_1.yaml index 72a1fa7..9f373e6 100644 --- a/data/registers/adc_f3_v1_1.yaml +++ b/data/registers/adc_f3_v1_1.yaml @@ -232,10 +232,12 @@ fieldset/CR2: description: External event select for injected group bit_offset: 16 bit_size: 4 + enum: JEXTSEL - name: JEXTEN description: External trigger enable for injected channels bit_offset: 20 bit_size: 2 + enum: EXTEN - name: JSWSTART description: Start conversion of injected channels bit_offset: 22 @@ -244,10 +246,12 @@ fieldset/CR2: description: External event select for regular group bit_offset: 24 bit_size: 4 + enum: EXTSEL - name: EXTEN description: External trigger enable for regular channels bit_offset: 28 bit_size: 2 + enum: EXTEN - name: SWSTART description: Start conversion of regular channels bit_offset: 30 @@ -584,7 +588,7 @@ enum/DELS: description: Delay 255 APB clock cycles after the conversion value: 7 enum/EXTEN: - bit_size: 3 + bit_size: 2 variants: - name: DISABLED description: Trigger detection disabled @@ -599,7 +603,7 @@ enum/EXTEN: description: Trigger detection on both edges value: 3 enum/EXTSEL: - bit_size: 3 + bit_size: 4 variants: - name: TIM9_CC2 description: Timer 9 CC2 event @@ -638,7 +642,7 @@ enum/EXTSEL: description: External interrupt line 11 value: 15 enum/JEXTSEL: - bit_size: 3 + bit_size: 4 variants: - name: TIM9_CC1 description: Timer 9 CC1 event diff --git a/data/registers/adc_v4.yaml b/data/registers/adc_v4.yaml index f029aa5..14868c2 100644 --- a/data/registers/adc_v4.yaml +++ b/data/registers/adc_v4.yaml @@ -740,7 +740,7 @@ enum/OVRMOD: description: Overwrite DR register when an overrun is detected value: 1 enum/PCSEL: - bit_size: 20 + bit_size: 1 variants: - name: NotPreselected description: Input channel x is not pre-selected diff --git a/data/registers/adf_v1.yaml b/data/registers/adf_v1.yaml index 406a7a0..65206c0 100644 --- a/data/registers/adf_v1.yaml +++ b/data/registers/adf_v1.yaml @@ -581,7 +581,7 @@ enum/SADST: value: 2 enum/SCKSRC: description: Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface. - bit_size: 1 + bit_size: 2 variants: - name: CCK0 description: Serial clock source is CCK0. @@ -589,6 +589,12 @@ enum/SCKSRC: - name: CCK1 description: Serial clock source is CCK1. value: 1 + - name: CKI0 + description: Serial clock source is CCI0. + value: 2 + - name: CKI1 + description: Serial clock source is CCI1. + value: 3 enum/SITFMOD: description: Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode. bit_size: 2 @@ -607,14 +613,104 @@ enum/SITFMOD: value: 3 enum/BSSEL: description: Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0. - bit_size: 1 + bit_size: 5 variants: - - name: BSR - description: bs0_r provided to DFLT0. + - name: BS0_R + description: bsx_r provided to DFLTy (and SCDy). value: 0 - - name: BSF - description: bs0_f provided to DFLT0. + - name: BS0_F + description: bsx_f provided to DFLTy (and SCDy). value: 1 + - name: BS1_R + description: bsx_r provided to DFLTy (and SCDy). + value: 2 + - name: BS1_F + description: bsx_f provided to DFLTy (and SCDy). + value: 3 + - name: BS2_R + description: bsx_r provided to DFLTy (and SCDy). + value: 4 + - name: BS2_F + description: bsx_f provided to DFLTy (and SCDy). + value: 5 + - name: BS3_R + description: bsx_r provided to DFLTy (and SCDy). + value: 6 + - name: BS3_F + description: bsx_f provided to DFLTy (and SCDy). + value: 7 + - name: BS4_R + description: bsx_r provided to DFLTy (and SCDy). + value: 8 + - name: BS4_F + description: bsx_f provided to DFLTy (and SCDy). + value: 9 + - name: BS5_R + description: bsx_r provided to DFLTy (and SCDy). + value: 10 + - name: BS5_F + description: bsx_f provided to DFLTy (and SCDy). + value: 11 + - name: BS6_R + description: bsx_r provided to DFLTy (and SCDy). + value: 12 + - name: BS6_F + description: bsx_f provided to DFLTy (and SCDy). + value: 13 + - name: BS7_R + description: bsx_r provided to DFLTy (and SCDy). + value: 14 + - name: BS7_F + description: bsx_f provided to DFLTy (and SCDy). + value: 15 + - name: BS8_R + description: bsx_r provided to DFLTy (and SCDy). + value: 16 + - name: BS8_F + description: bsx_f provided to DFLTy (and SCDy). + value: 17 + - name: BS9_R + description: bsx_r provided to DFLTy (and SCDy). + value: 18 + - name: BS9_F + description: bsx_f provided to DFLTy (and SCDy). + value: 19 + - name: BS10_R + description: bsx_r provided to DFLTy (and SCDy). + value: 20 + - name: BS10_F + description: bsx_f provided to DFLTy (and SCDy). + value: 21 + - name: BS11_R + description: bsx_r provided to DFLTy (and SCDy). + value: 22 + - name: BS11_F + description: bsx_f provided to DFLTy (and SCDy). + value: 23 + - name: BS12_R + description: bsx_r provided to DFLTy (and SCDy). + value: 24 + - name: BS12_F + description: bsx_f provided to DFLTy (and SCDy). + value: 25 + - name: BS13_R + description: bsx_r provided to DFLTy (and SCDy). + value: 26 + - name: BS13_F + description: bsx_f provided to DFLTy (and SCDy). + value: 27 + - name: BS14_R + description: bsx_r provided to DFLTy (and SCDy). + value: 28 + - name: BS14_F + description: bsx_f provided to DFLTy (and SCDy). + value: 29 + - name: BS15_R + description: bsx_r provided to DFLTy (and SCDy). + value: 30 + - name: BS15_F + description: bsx_f provided to DFLTy (and SCDy). + value: 31 enum/DATSRC: description: Source data for the digital filter. bit_size: 2 @@ -774,5 +870,3 @@ enum/SNTHR: - name: NOISE PLUS 30_1 description: Threshold is 30.1 dB higher than ANLVL value: 9 - - diff --git a/data/registers/flash_f4.yaml b/data/registers/flash_f4.yaml index 00596cc..6707e6b 100644 --- a/data/registers/flash_f4.yaml +++ b/data/registers/flash_f4.yaml @@ -31,7 +31,7 @@ fieldset/ACR: - name: LATENCY description: Latency bit_offset: 0 - bit_size: 3 + bit_size: 4 enum: LATENCY - name: PRFTEN description: Prefetch enable @@ -168,7 +168,7 @@ fieldset/SR: bit_offset: 16 bit_size: 1 enum/LATENCY: - bit_size: 3 + bit_size: 4 variants: - name: WS0 description: 0 wait states diff --git a/data/registers/flash_g4.yaml b/data/registers/flash_g4.yaml index a220f74..e0c03cf 100644 --- a/data/registers/flash_g4.yaml +++ b/data/registers/flash_g4.yaml @@ -359,7 +359,7 @@ fieldset/WRP1BR: bit_offset: 16 bit_size: 7 enum/LATENCY: - bit_size: 3 + bit_size: 4 variants: - name: WS0 description: Zero wait states diff --git a/data/registers/icache_v1.yaml b/data/registers/icache_v1.yaml index b47fb2f..72180ad 100644 --- a/data/registers/icache_v1.yaml +++ b/data/registers/icache_v1.yaml @@ -29,10 +29,12 @@ fieldset/CRRX: description: AHB cache master selection for region. bit_offset: 28 bit_size: 1 + enum: MSTSEL - name: HBURST description: output burst type for region. bit_offset: 31 bit_size: 1 + enum: HBURST block/ICACHE: description: Instruction Cache Control Registers. items: @@ -214,4 +216,4 @@ enum/WAYSEL: value: 0 - name: NWaySetAssociative description: n-way set associative cache (reset value) - value: 1 \ No newline at end of file + value: 1 diff --git a/data/registers/ipcc_v1.yaml b/data/registers/ipcc_v1.yaml index 8212dff..43ec9be 100644 --- a/data/registers/ipcc_v1.yaml +++ b/data/registers/ipcc_v1.yaml @@ -14,126 +14,71 @@ block/IPCC_CPU: - name: CR description: Control register CPUx byte_offset: 0 - fieldset: C1CR + fieldset: CxCR - name: MR description: Mask register CPUx byte_offset: 4 - fieldset: C1MR + fieldset: CxMR - name: SCR - description: Status Set or Clear register CPU1 + description: Status Set or Clear register CPUx byte_offset: 8 access: Write - fieldset: C1SCR + fieldset: CxSCR - name: SR - description: CPU1 to CPU2 status register + description: CPUx to CPUy status register byte_offset: 12 access: Read - fieldset: C1TO2SR -fieldset/C1CR: - description: Control register CPU1 + fieldset: CxTOySR +fieldset/CxCR: + description: Control register CPUx fields: - name: RXOIE - description: processor 1 Receive channel occupied interrupt enable + description: processor x Receive channel occupied interrupt enable bit_offset: 0 bit_size: 1 - name: TXFIE - description: processor 1 Transmit channel free interrupt enable + description: processor x Transmit channel free interrupt enable bit_offset: 16 bit_size: 1 -fieldset/C1MR: - description: Mask register CPU1 +fieldset/CxMR: + description: Mask register CPUx fields: - name: CHOM - description: processor 1 Receive channel x occupied interrupt enable + description: processor x Receive channel y occupied interrupt enable bit_offset: 0 bit_size: 1 array: len: 6 stride: 1 - name: CHFM - description: processor 1 Transmit channel x free interrupt mask + description: processor x Transmit channel y free interrupt mask bit_offset: 16 bit_size: 1 array: len: 6 stride: 1 -fieldset/C1SCR: - description: Status Set or Clear register CPU1 +fieldset/CxSCR: + description: Status Set or Clear register CPUx fields: - name: CHC - description: processor 1 Receive channel x status clear + description: processor x Receive channel y status clear bit_offset: 0 bit_size: 1 array: len: 6 stride: 1 - name: CHS - description: processor 1 Transmit channel x status set + description: processor x Transmit channel y status set bit_offset: 16 bit_size: 1 array: len: 6 stride: 1 -fieldset/C1TO2SR: - description: CPU1 to CPU2 status register +fieldset/CxTOySR: + description: CPUx to CPUy status register fields: - name: CHF - description: processor 1 transmit to process 2 Receive channel x status flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 -fieldset/C2CR: - description: Control register CPU2 - fields: - - name: RXOIE - description: processor 2 Receive channel occupied interrupt enable - bit_offset: 0 - bit_size: 1 - - name: TXFIE - description: processor 2 Transmit channel free interrupt enable - bit_offset: 16 - bit_size: 1 -fieldset/C2MR: - description: Mask register CPU2 - fields: - - name: CHOM - description: processor 2 Receive channel x occupied interrupt enable - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CHFM - description: processor 2 Transmit channel 1 free interrupt mask - bit_offset: 16 - bit_size: 1 - array: - len: 6 - stride: 1 -fieldset/C2SCR: - description: Status Set or Clear register CPU2 - fields: - - name: CHC - description: processor 2 Receive channel x status clear - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CHS - description: processor 2 Transmit channel 1 status set - bit_offset: 16 - bit_size: 1 - array: - len: 6 - stride: 1 -fieldset/C2TOC1SR: - description: CPU2 to CPU1 status register - fields: - - name: CHF - description: processor 2 transmit to process 1 Receive channel x status flag + description: processor x transmit to process y Receive channel z status flag bit_offset: 0 bit_size: 1 array: diff --git a/data/registers/octospi_v1.yaml b/data/registers/octospi_v1.yaml index be0c349..3531730 100644 --- a/data/registers/octospi_v1.yaml +++ b/data/registers/octospi_v1.yaml @@ -214,6 +214,7 @@ fieldset/CR: description: Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. bit_offset: 7 bit_size: 1 + enum: FlashSelect - name: FTHRES description: 'FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value.' bit_offset: 8 @@ -247,6 +248,7 @@ fieldset/CR: description: Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode. bit_offset: 23 bit_size: 1 + enum: MatchMode - name: FMODE description: Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. bit_offset: 28 @@ -349,6 +351,7 @@ fieldset/HLCR: description: Latency mode. This bit selects the Latency mode. bit_offset: 0 bit_size: 1 + enum: LatencyMode - name: WZL description: Write zero latency. This bit enables zero latency on write operations. bit_offset: 1 @@ -595,7 +598,7 @@ fieldset/WPTCR: bit_offset: 0 bit_size: 5 - name: DHQC - description: Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. + description: Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. bit_offset: 28 bit_size: 1 - name: SSHIFT @@ -610,15 +613,6 @@ fieldset/WTCR: description: Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. bit_offset: 0 bit_size: 5 -enum/CycleDelay: - bit_size: 1 - variants: - - name: None - description: No delay hold - value: 0 - - name: QuarterCycle - description: 1/4 cycle hold - value: 1 enum/FlashSelect: bit_size: 1 variants: @@ -643,7 +637,7 @@ enum/FunctionalMode: - name: MemoryMapped description: Memory-mapped mode value: 3 -enum/Latency: +enum/LatencyMode: bit_size: 1 variants: - name: Variable @@ -682,18 +676,6 @@ enum/MemType: - name: HyperBusRegister description: HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used. value: 5 -enum/NcsCycleHold: - bit_size: 6 - variants: - - name: OneCycle - description: NCS stays high for at least 1 cycle between external device commands. - value: 0 - - name: TwoCycles - description: NCS stays high for at least 2 cycles between external device commands. - value: 1 - - name: SixtyFourCycles - description: NCS stays high for at least 64 cycles between external device commands. - value: 63 enum/PhaseMode: bit_size: 3 variants: diff --git a/data/registers/octospi_v2.yaml b/data/registers/octospi_v2.yaml index b170156..7bba8e5 100644 --- a/data/registers/octospi_v2.yaml +++ b/data/registers/octospi_v2.yaml @@ -214,6 +214,7 @@ fieldset/CR: description: Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. bit_offset: 7 bit_size: 1 + enum: FlashSelect - name: FTHRES description: 'FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value.' bit_offset: 8 @@ -247,6 +248,7 @@ fieldset/CR: description: Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode. bit_offset: 23 bit_size: 1 + enum: MatchMode - name: FMODE description: Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. bit_offset: 28 @@ -345,6 +347,7 @@ fieldset/HLCR: description: Latency mode. This bit selects the Latency mode. bit_offset: 0 bit_size: 1 + enum: LatencyMode - name: WZL description: Write zero latency. This bit enables zero latency on write operations. bit_offset: 1 @@ -591,7 +594,7 @@ fieldset/WPTCR: bit_offset: 0 bit_size: 5 - name: DHQC - description: Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. + description: Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. bit_offset: 28 bit_size: 1 - name: SSHIFT @@ -606,15 +609,6 @@ fieldset/WTCR: description: Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. bit_offset: 0 bit_size: 5 -enum/CycleDelay: - bit_size: 1 - variants: - - name: None - description: No delay hold - value: 0 - - name: QuarterCycle - description: 1/4 cycle hold - value: 1 enum/FlashSelect: bit_size: 1 variants: @@ -639,7 +633,7 @@ enum/FunctionalMode: - name: MemoryMapped description: Memory-mapped mode value: 3 -enum/Latency: +enum/LatencyMode: bit_size: 1 variants: - name: Variable @@ -678,18 +672,6 @@ enum/MemType: - name: HyperBusRegister description: HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used. value: 5 -enum/NcsCycleHold: - bit_size: 6 - variants: - - name: OneCycle - description: NCS stays high for at least 1 cycle between external device commands. - value: 0 - - name: TwoCycles - description: NCS stays high for at least 2 cycles between external device commands. - value: 1 - - name: SixtyFourCycles - description: NCS stays high for at least 64 cycles between external device commands. - value: 63 enum/PhaseMode: bit_size: 3 variants: diff --git a/data/registers/opamp_f3.yaml b/data/registers/opamp_f3.yaml index 26205d1..4a59086 100644 --- a/data/registers/opamp_f3.yaml +++ b/data/registers/opamp_f3.yaml @@ -13,17 +13,20 @@ fieldset/OPAMP_CSR: bit_offset: 0 bit_size: 1 - name: FORCE_VP - description: FORCE_VP + description: Forces a calibration reference voltage on non-inverting input and disables external connections. bit_offset: 1 bit_size: 1 + enum: FORCE_VP - name: VP_SEL description: OPAMP Non inverting input selection bit_offset: 2 bit_size: 2 + enum: VP_SEL - name: VM_SEL description: OPAMP inverting input selection bit_offset: 5 bit_size: 2 + enum: VM_SEL - name: TCM_EN description: Timer controlled Mux mode enable bit_offset: 7 @@ -32,10 +35,12 @@ fieldset/OPAMP_CSR: description: OPAMP inverting input secondary selection bit_offset: 8 bit_size: 1 + enum: VMS_SEL - name: VPS_SEL description: OPAMP Non inverting input secondary selection bit_offset: 9 bit_size: 2 + enum: VPS_SEL - name: CALON description: Calibration mode enable bit_offset: 11 @@ -44,10 +49,12 @@ fieldset/OPAMP_CSR: description: Calibration selection bit_offset: 12 bit_size: 2 + enum: CALSEL - name: PGA_GAIN description: Gain in PGA mode bit_offset: 14 bit_size: 4 + enum: PGA_GAIN - name: USER_TRIM description: User trimming enable bit_offset: 18 @@ -61,13 +68,14 @@ fieldset/OPAMP_CSR: bit_offset: 24 bit_size: 5 - name: TSTREF - description: TSTREF + description: Output the internal reference voltage bit_offset: 29 bit_size: 1 - name: OUTCAL description: OPAMP ouput status flag bit_offset: 30 bit_size: 1 + enum: OUTCAL - name: LOCK description: OPAMP lock bit_offset: 31 @@ -144,15 +152,6 @@ enum/PGA_GAIN: - name: Gain16_VM1 description: Gain 16, feedback connected to VM1 value: 15 -enum/TSTREF: - bit_size: 1 - variants: - - name: Output - description: VREFOPAMP2 is output - value: 0 - - name: NotOutput - description: VREFOPAMP2 is not output - value: 1 enum/VMS_SEL: bit_size: 1 variants: diff --git a/data/registers/otg_v1.yaml b/data/registers/otg_v1.yaml index 29dcf16..e5e8c2a 100644 --- a/data/registers/otg_v1.yaml +++ b/data/registers/otg_v1.yaml @@ -1076,21 +1076,6 @@ fieldset/GLPMCFG: description: Enable best effort service latency bit_offset: 28 bit_size: 1 -fieldset/GNPTXSTS: - description: Non-periodic transmit FIFO/queue status register - fields: - - name: NPTXFSAV - description: Non-periodic TxFIFO space available - bit_offset: 0 - bit_size: 16 - - name: NPTQXSAV - description: Non-periodic transmit request queue space available - bit_offset: 16 - bit_size: 8 - - name: NPTXQTOP - description: Top of the non-periodic transmit request queue - bit_offset: 24 - bit_size: 7 fieldset/GOTGCTL: description: Control and status register fields: diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index 596fbd4..09be17c 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -477,7 +477,7 @@ fieldset/CFGR: - name: MCOSEL description: Microcontroller clock output bit_offset: 24 - bit_size: 3 + bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller Clock Output Prescaler @@ -845,7 +845,7 @@ enum/MCOPRE: description: MCO is divided by 128 value: 7 enum/MCOSEL: - bit_size: 3 + bit_size: 4 variants: - name: NoMCO description: MCO output disabled, no clock on MCO diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 98bc4fe..bad21c3 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1260,7 +1260,7 @@ fieldset/CFGR: description: I2S clock selection bit_offset: 23 bit_size: 1 - enum: ISSRC + enum: I2SSRC_CFGR - name: MCO1PRE description: MCO1 prescaler bit_offset: 24 @@ -1539,7 +1539,7 @@ fieldset/DCKCFGR: - name: CKDFSDM1ASEL description: DFSDM1 audio clock selection bit_offset: 15 - bit_size: 5 + bit_size: 1 enum: CKDFSDMASEL - name: PLLSAIDIVR description: division factor for LCD_CLK @@ -1580,7 +1580,7 @@ fieldset/DCKCFGR: description: I2SSRC bit_offset: 25 bit_size: 2 - enum: ISSRC + enum: I2SSRC_DCKCFGR - name: CLK48SEL description: 48 MHz clock source selection bit_offset: 27 @@ -1865,7 +1865,7 @@ enum/I2S1SRC: - name: HSI_HSE description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) value: 3 -enum/ISSRC: +enum/I2SSRC_CFGR: bit_size: 1 variants: - name: PLLI2S @@ -1874,6 +1874,21 @@ enum/ISSRC: - name: CKIN description: External clock mapped on the I2S_CKIN pin used as I2S clock source value: 1 +enum/I2SSRC_DCKCFGR: + bit_size: 2 + variants: + - name: PLLI2S_R + description: clock frequency = f(PLLI2S_R) + value: 0 + - name: I2S_CKIN + description: clock frequency = I2S_CKIN Alternate function input frequency + value: 1 + - name: PLL_R + description: clock frequency = f(PLL_R) + value: 2 + - name: HSI_HSE + description: clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + value: 3 enum/LPTIMSEL: bit_size: 2 variants: @@ -2243,21 +2258,6 @@ enum/PLLI2SDIVR: - name: Div32 description: PLLI2SDIVQ = /32 value: 31 -enum/PLLI2SP: - bit_size: 2 - variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 enum/PLLI2SSRC: bit_size: 1 variants: @@ -3338,21 +3338,6 @@ enum/PLLSAIDIVR: - name: Div16 description: PLLSAIDIVR = /16 value: 3 -enum/PLLSAIP: - bit_size: 2 - variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 enum/PLLSRC: bit_size: 1 variants: diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 67f055d..7563d19 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1965,21 +1965,6 @@ enum/PLLI2SDIVQ: - name: Div32 description: PLLI2SDIVQ = /32 value: 31 -enum/PLLI2SP: - bit_size: 2 - variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 enum/PLLM: bit_size: 6 variants: @@ -3051,21 +3036,6 @@ enum/PLLSAIDIVR: - name: Div16 description: PLLSAIDIVR = /16 value: 3 -enum/PLLSAIP: - bit_size: 2 - variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 enum/PLLSRC: bit_size: 1 variants: diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index 12b6c02..763223c 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -849,12 +849,12 @@ fieldset/CFGR: - name: MCO1SEL description: Microcontroller clock output bit_offset: 24 - bit_size: 3 + bit_size: 4 enum: MCOSEL - name: MCO1PRE description: Microcontroller clock output prescaler bit_offset: 28 - bit_size: 3 + bit_size: 4 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register @@ -1765,7 +1765,7 @@ enum/PLLSRC: description: HSE selected as PLL entry clock source value: 3 enum/PPRE: - bit_size: 4 + bit_size: 3 variants: - name: Div1 description: HCLK not divided diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index 21108fc..969ee68 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1743,7 +1743,7 @@ enum/PLLN: - name: Mul127 value: 127 enum/PLLP: - bit_size: 7 + bit_size: 5 variants: - name: Div2 value: 2 @@ -1847,7 +1847,7 @@ enum/PLLSRC: description: HSE selected as PLL entry clock source value: 3 enum/PPRE: - bit_size: 4 + bit_size: 3 variants: - name: Div1 description: HCLK not divided diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 3dfd9a6..2a1c2e1 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -5,6 +5,10 @@ block/RCC: description: clock control register byte_offset: 0 fieldset: CR + - name: ICSCR + description: RCC Internal Clock Source Calibration Register + byte_offset: 4 + fieldset: ICSCR - name: HSICFGR description: RCC HSI configuration register byte_offset: 4 diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index c83d3b9..f3e4b7b 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -5,6 +5,10 @@ block/RCC: description: clock control register byte_offset: 0 fieldset: CR + - name: ICSCR + description: RCC Internal Clock Source Calibration Register + byte_offset: 4 + fieldset: ICSCR - name: HSICFGR description: RCC HSI configuration register byte_offset: 4 diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index 84fba96..8db6f31 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -881,7 +881,7 @@ enum/MCOPRE: description: Division by 16 value: 4 enum/MCOSEL: - bit_size: 4 + bit_size: 3 variants: - name: DISABLE description: No clock diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 6e74237..904cf86 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -2394,7 +2394,7 @@ enum/PLLN: - name: Mul127 value: 127 enum/PLLP: - bit_size: 7 + bit_size: 5 variants: - name: Div2 value: 2 diff --git a/data/registers/rtc_v3l5.yaml b/data/registers/rtc_v3l5.yaml index 7405a64..b20930e 100644 --- a/data/registers/rtc_v3l5.yaml +++ b/data/registers/rtc_v3l5.yaml @@ -854,18 +854,6 @@ enum/RECALPF: - name: Pending description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 value: 1 -enum/SSRUF: - bit_size: 1 - variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 -enum/SSRUMF: - bit_size: 1 - variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 enum/TAMPALRM_TYPE: bit_size: 1 variants: diff --git a/data/registers/sdmmc_v1.yaml b/data/registers/sdmmc_v1.yaml index 72e5810..cb9263a 100644 --- a/data/registers/sdmmc_v1.yaml +++ b/data/registers/sdmmc_v1.yaml @@ -29,7 +29,7 @@ block/SDMMC: stride: 4 byte_offset: 20 access: Read - fieldset: RESP1R + fieldset: RESPxR - name: DTIMER description: data timer register byte_offset: 36 @@ -361,28 +361,7 @@ fieldset/POWER: description: PWRCTRL bit_offset: 0 bit_size: 2 -fieldset/RESP1R: - description: response 1..4 register - fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 -fieldset/RESP2R: - description: response 1..4 register - fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 -fieldset/RESP3R: - description: response 1..4 register - fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 -fieldset/RESP4R: +fieldset/RESPxR: description: response 1..4 register fields: - name: CARDSTATUS diff --git a/data/registers/sdmmc_v2.yaml b/data/registers/sdmmc_v2.yaml index 3210812..a8710cc 100644 --- a/data/registers/sdmmc_v2.yaml +++ b/data/registers/sdmmc_v2.yaml @@ -29,7 +29,7 @@ block/SDMMC: stride: 4 byte_offset: 20 access: Read - fieldset: RESP1R + fieldset: RESPxR - name: DTIMER description: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. byte_offset: 36 @@ -501,34 +501,13 @@ fieldset/POWER: description: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). bit_offset: 4 bit_size: 1 -fieldset/RESP1R: +fieldset/RESPxR: description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. fields: - name: CARDSTATUS description: see Table 432 bit_offset: 0 bit_size: 32 -fieldset/RESP2R: - description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. - fields: - - name: CARDSTATUS - description: see Table404. - bit_offset: 0 - bit_size: 32 -fieldset/RESP3R: - description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. - fields: - - name: CARDSTATUS - description: see Table404. - bit_offset: 0 - bit_size: 32 -fieldset/RESP4R: - description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. - fields: - - name: CARDSTATUS - description: see Table404. - bit_offset: 0 - bit_size: 32 fieldset/RESPCMDR: description: SDMMC command response register fields: diff --git a/data/registers/syscfg_c0.yaml b/data/registers/syscfg_c0.yaml index a7ec916..2ab18d7 100644 --- a/data/registers/syscfg_c0.yaml +++ b/data/registers/syscfg_c0.yaml @@ -417,105 +417,69 @@ enum/MEM_MODE: enum/PINMUX0: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 + - name: PB7 description: PB7 value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2 - description: PA1 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 + - name: PC14 description: PC14 value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2 - description: PA2 - value: 1 enum/PINMUX1: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + - name: PF2 description: PF2 value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3 - description: PF2 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + - name: PA0 description: PA0 value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3 - description: PA0 - value: 1 - - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + - name: PA1 description: PA1 value: 2 - - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + - name: PA2 description: PA2 value: 3 enum/PINMUX2: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 + - name: PA8 description: PA8 value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1 - description: PA8 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 - description: PA11 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1 + - name: PA11 description: PA11 value: 1 enum/PINMUX3: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + - name: PA14 description: PA14 value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2 - description: PA5 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + - name: PB6 description: PB6 value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2 - description: PA6 - value: 1 - - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + - name: PC15 description: PC15 value: 2 enum/PINMUX4: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 + - name: PA7 description: PA7 value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1 - description: PA7 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 - description: PA12 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1 + - name: PA12 description: PA12 value: 1 enum/PINMUX5: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + - name: PA3 description: PA3 value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3 - description: PA3 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + - name: PA4 description: PA4 value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3 - description: PA4 - value: 1 - - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + - name: PA5 description: PA5 value: 2 - - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + - name: PA6 description: PA6 value: 3 diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml index de839ae..9619f74 100644 --- a/data/registers/syscfg_f0.yaml +++ b/data/registers/syscfg_f0.yaml @@ -25,125 +25,179 @@ fieldset/CFGR1: bit_size: 2 enum: MEM_MODE - name: PA11_PA12_RMP - description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) + description: | + PA11 and PA12 remapping bit for small packages (28 and 20 pins) + 0: Pin pair PA9/PA10 mapped on the pins + 1: Pin pair PA11/PA12 mapped instead of PA9/PA10 bit_offset: 4 bit_size: 1 - enum: PA11_PA12_RMP - name: IR_MOD description: IR Modulation Envelope signal selection bit_offset: 6 bit_size: 2 enum: IR_MOD - name: ADC_DMA_RMP - description: ADC DMA remapping bit + description: | + ADC DMA remapping bit + 0: ADC DMA request mapped on DMA channel 1 + 1: ADC DMA request mapped on DMA channel 2 bit_offset: 8 bit_size: 1 - enum: ADC_DMA_RMP - name: USART1_TX_DMA_RMP - description: USART1_TX DMA remapping bit + description: | + USART1_TX DMA remapping bit + 0: USART1_TX DMA request mapped on DMA channel 2 + 1: USART1_TX DMA request mapped on DMA channel 4 bit_offset: 9 bit_size: 1 - enum: USART1_TX_DMA_RMP - name: USART1_RX_DMA_RMP - description: USART1_RX DMA request remapping bit + description: | + USART1_RX DMA request remapping bit + 0: USART1_RX DMA request mapped on DMA channel 3 + 1: USART1_RX DMA request mapped on DMA channel 5 bit_offset: 10 bit_size: 1 - enum: USART1_RX_DMA_RMP - name: TIM16_DMA_RMP - description: TIM16 DMA request remapping bit + description: | + TIM16 DMA request remapping bit + 0: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 + 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - enum: TIM16_DMA_RMP - name: TIM17_DMA_RMP - description: TIM17 DMA request remapping bit + description: | + TIM17 DMA request remapping bit + 0: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 + 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - enum: TIM17_DMA_RMP - name: TIM16_DMA_RMP2 - description: TIM16 alternate DMA request remapping bit + description: | + TIM16 alternate DMA request remapping bit + 0: TIM16 DMA request mapped according to TIM16_DMA_RMP bit + 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 bit_offset: 13 bit_size: 1 - enum: TIM16_DMA_RMP2 - name: TIM17_DMA_RMP2 - description: TIM17 alternate DMA request remapping bit + description: | + TIM17 alternate DMA request remapping bit + 0: TIM17 DMA request mapped according to TIM16_DMA_RMP bit + 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 bit_offset: 14 bit_size: 1 - enum: TIM17_DMA_RMP2 - name: I2C_PB6_FMP - description: Fast Mode Plus (FM plus) driving capability activation bits. + description: | + Fast Mode Plus (FM plus) driving capability activation bits. + 0: PB6 pin operate in standard mode + 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed bit_offset: 16 bit_size: 1 - enum: I2C_PB6_FMP + enum: FMP - name: I2C_PB7_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB7 pin operate in standard mode + 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed bit_offset: 17 bit_size: 1 - enum: I2C_PB7_FMP + enum: FMP - name: I2C_PB8_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB8 pin operate in standard mode + 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed bit_offset: 18 bit_size: 1 - enum: I2C_PB8_FMP + enum: FMP - name: I2C_PB9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB9 pin operate in standard mode + 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed bit_offset: 19 bit_size: 1 - enum: I2C_PB9_FMP + enum: FMP - name: I2C1_FMP - description: FM+ driving capability activation for I2C1 + description: | + FM+ driving capability activation for I2C1 + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers bit_offset: 20 bit_size: 1 - enum: I2C1_FMP + enum: FMP - name: I2C2_FMP - description: FM+ driving capability activation for I2C2 + description: | + FM+ driving capability activation for I2C2 + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers bit_offset: 21 bit_size: 1 - enum: I2C2_FMP + enum: FMP - name: I2C_PA9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits + description: | + Fast Mode Plus (FM+) driving capability activation bits + 0: PA9 pin operate in standard mode + 1: I2C FM+ mode enabled on PA9 and the Speed control is bypassed bit_offset: 22 bit_size: 1 - enum: I2C_PA9_FMP + enum: FMP - name: I2C_PA10_FMP - description: Fast Mode Plus (FM+) driving capability activation bits + description: | + Fast Mode Plus (FM+) driving capability activation bits + 0: PA10 pin operate in standard mode + 1: I2C FM+ mode enabled on PA10 and the Speed control is bypassed bit_offset: 23 bit_size: 1 - enum: I2C_PA10_FMP + enum: FMP - name: SPI2_DMA_RMP - description: SPI2 DMA request remapping bit + description: | + SPI2 DMA request remapping bit + 0: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively + 1: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 24 bit_size: 1 - enum: SPI2_DMA_RMP - name: USART2_DMA_RMP - description: USART2 DMA request remapping bit + description: | + USART2 DMA request remapping bit + 0: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively + 1: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 25 bit_size: 1 - enum: USART2_DMA_RMP - name: USART3_DMA_RMP - description: USART3 DMA request remapping bit + description: | + USART3 DMA request remapping bit + 0: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) + 1: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively bit_offset: 26 bit_size: 1 - enum: USART3_DMA_RMP - name: I2C1_DMA_RMP - description: I2C1 DMA request remapping bit + description: | + I2C1 DMA request remapping bit + 0: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively + 1: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively bit_offset: 27 bit_size: 1 - enum: I2C1_DMA_RMP - name: TIM1_DMA_RMP - description: TIM1 DMA request remapping bit + description: | + TIM1 DMA request remapping bit + 0: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively + 1: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 bit_offset: 28 bit_size: 1 - enum: TIM1_DMA_RMP - name: TIM2_DMA_RMP - description: TIM2 DMA request remapping bit + description: | + TIM2 DMA request remapping bit + 0: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively + 1: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 bit_offset: 29 bit_size: 1 - enum: TIM2_DMA_RMP - name: TIM3_DMA_RMP - description: TIM3 DMA request remapping bit + description: | + TIM3 DMA request remapping bit + 0: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 + 1: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 bit_offset: 30 bit_size: 1 - enum: TIM3_DMA_RMP fieldset/CFGR2: description: configuration register 2 fields: @@ -151,17 +205,14 @@ fieldset/CFGR2: description: Cortex-M0 LOCKUP bit enable bit bit_offset: 0 bit_size: 1 - enum: LOCKUP_LOCK - name: SRAM_PARITY_LOCK description: SRAM parity lock bit bit_offset: 1 bit_size: 1 - enum: SRAM_PARITY_LOCK - name: PVD_LOCK description: PVD lock enable bit bit_offset: 2 bit_size: 1 - enum: PVD_LOCK - name: SRAM_PEF description: SRAM parity flag bit_offset: 8 @@ -176,95 +227,14 @@ fieldset/EXTICR: array: len: 4 stride: 4 -enum/ADC_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: ADC DMA request mapped on DMA channel 1 - value: 0 - - name: Remapped - description: ADC DMA request mapped on DMA channel 2 - value: 1 -enum/I2C1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively - value: 0 - - name: Remapped - description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively - value: 1 -enum/I2C1_FMP: +enum/FMP: bit_size: 1 variants: - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only + description: Standard value: 0 - name: FMP - description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers - value: 1 -enum/I2C2_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers - value: 1 -enum/I2C_PA10_FMP: - bit_size: 1 - variants: - - name: Standard - description: PA10 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed - value: 1 -enum/I2C_PA9_FMP: - bit_size: 1 - variants: - - name: Standard - description: PA9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed - value: 1 -enum/I2C_PB6_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB6 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - value: 1 -enum/I2C_PB7_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB7 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - value: 1 -enum/I2C_PB8_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB8 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - value: 1 -enum/I2C_PB9_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + description: FM+ value: 1 enum/IR_MOD: bit_size: 2 @@ -278,15 +248,6 @@ enum/IR_MOD: - name: USART4 description: USART4 selected value: 2 -enum/LOCKUP_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input - value: 1 enum/MEM_MODE: bit_size: 2 variants: @@ -302,138 +263,3 @@ enum/MEM_MODE: - name: SRAM description: Embedded SRAM mapped at 0x0000_0000 value: 3 -enum/PA11_PA12_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Pin pair PA9/PA10 mapped on the pins - value: 0 - - name: Remapped - description: Pin pair PA11/PA12 mapped instead of PA9/PA10 - value: 1 -enum/PVD_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: PVD interrupt disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: PVD interrupt connected to TIM1/15/16/17 Break input - value: 1 -enum/SPI2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively - value: 0 - - name: Remapped - description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively - value: 1 -enum/SRAM_PARITY_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: SRAM parity error disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: SRAM parity error connected to TIM1/15/16/17 Break input - value: 1 -enum/TIM16_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 - value: 0 - - name: Remapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 - value: 1 -enum/TIM16_DMA_RMP2: - bit_size: 1 - variants: - - name: NotAlternateRemapped - description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit - value: 0 - - name: AlternateRemapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 - value: 1 -enum/TIM17_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 - value: 0 - - name: Remapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 - value: 1 -enum/TIM17_DMA_RMP2: - bit_size: 1 - variants: - - name: NotAlternateRemapped - description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit - value: 0 - - name: AlternateRemapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 - value: 1 -enum/TIM1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively - value: 0 - - name: Remapped - description: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 - value: 1 -enum/TIM2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively - value: 0 - - name: Remapped - description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 - value: 1 -enum/TIM3_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 - value: 0 - - name: Remapped - description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 - value: 1 -enum/USART1_RX_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART1_RX DMA request mapped on DMA channel 3 - value: 0 - - name: Remapped - description: USART1_RX DMA request mapped on DMA channel 5 - value: 1 -enum/USART1_TX_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART1_TX DMA request mapped on DMA channel 2 - value: 0 - - name: Remapped - description: USART1_TX DMA request mapped on DMA channel 4 - value: 1 -enum/USART2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively - value: 0 - - name: Remapped - description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively - value: 1 -enum/USART3_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) - value: 0 - - name: Remapped - description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively - value: 1 diff --git a/data/registers/syscfg_f3.yaml b/data/registers/syscfg_f3.yaml index 2445026..0fb3c1e 100644 --- a/data/registers/syscfg_f3.yaml +++ b/data/registers/syscfg_f3.yaml @@ -37,115 +37,164 @@ fieldset/CFGR1: bit_size: 2 enum: MEM_MODE - name: USB_IT_RMP - description: USB interrupt remap + description: | + USB interrupt remap + 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively + 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively bit_offset: 5 bit_size: 1 - enum: USB_IT_RMP - name: TIM1_ITR3_RMP - description: Timer 1 ITR3 selection + description: | + Timer 1 ITR3 selection + 0: Not remapped + 1: TIM1_ITR3 = TIM17_OC bit_offset: 6 bit_size: 1 - enum: TIM1_ITR3_RMP - name: DAC1_TRIG_RMP - description: DAC trigger remap (when TSEL = 001) + description: | + DAC trigger remap (when TSEL = 001) + 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices + 1: DAC trigger is TIM3_TRGO bit_offset: 7 bit_size: 1 - enum: DAC1_TRIG_RMP - name: DAC_TRIG_RMP - description: DAC trigger remap (when TSEL = 001) + description: | + DAC trigger remap (when TSEL = 001) + 0: Not remapped + 1: DAC trigger is TIM3_TRGO bit_offset: 7 bit_size: 1 - enum: DAC_TRIG_RMP - name: ADC2_DMA_RMP - description: ADC24 DMA remapping bit + description: | + ADC24 DMA remapping bit + 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 + 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4 bit_offset: 8 bit_size: 1 - enum: ADC2_DMA_RMP_CFGR1 - name: TIM16_DMA_RMP - description: TIM16 DMA request remapping bit + description: | + TIM16 DMA request remapping bit + 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 + 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - enum: TIM16_DMA_RMP - name: TIM17_DMA_RMP - description: TIM17 DMA request remapping bit + description: | + TIM17 DMA request remapping bit + 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - enum: TIM17_DMA_RMP - name: TIM6_DAC1_CH1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit + description: | + TIM6 and DAC1 DMA request remapping bit + 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - enum: TIM6_DAC1_CH1_DMA_RMP - name: TIM6_DAC1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit + description: | + TIM6 and DAC1 DMA request remapping bit + 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - enum: TIM6_DAC1_DMA_RMP - name: TIM6_DAC1_OUT1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit + description: | + TIM6 and DAC1 DMA request remapping bit + 0: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 + 1: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - enum: TIM6_DAC1_OUT1_DMA_RMP - name: TIM7_DAC1_CH2_DMA_RMP - description: TIM7 and DAC2 DMA request remapping bit + description: | + TIM7 and DAC2 DMA request remapping bit + 0: Not remapped + 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 bit_offset: 14 bit_size: 1 - enum: TIM7_DAC1_CH2_DMA_RMP - name: TIM7_DAC1_OUT2_DMA_RMP - description: TIM7 and DAC2 DMA request remapping bit + description: | + TIM7 and DAC2 DMA request remapping bit + 0: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 + 1: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 bit_offset: 14 bit_size: 1 - enum: TIM7_DAC1_OUT2_DMA_RMP - name: DAC2_CH1_DMA_RMP - description: DAC2 channel1 DMA remap + description: | + DAC2 channel1 DMA remap + 0: Not remapped + 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5 bit_offset: 15 bit_size: 1 - enum: DAC2_CH1_DMA_RMP - name: TIM18_DAC2_OUT1_DMA_RMP - description: TIM18 and DAC2_OUT1 DMA request remapping bit + description: | + TIM18 and DAC2_OUT1 DMA request remapping bit + 0: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 + 1: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 bit_offset: 15 bit_size: 1 - enum: TIM18_DAC2_OUT1_DMA_RMP - name: I2C_PB6_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB6 pin operate in standard mode + 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed bit_offset: 16 bit_size: 1 - enum: I2C_PB6_FMP + enum: FMP - name: I2C_PB7_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB7 pin operate in standard mode + 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed bit_offset: 17 bit_size: 1 - enum: I2C_PB7_FMP + enum: FMP - name: I2C_PB8_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB8 pin operate in standard mode + 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed bit_offset: 18 bit_size: 1 - enum: I2C_PB8_FMP + enum: FMP - name: I2C_PB9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB9 pin operate in standard mode + 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed bit_offset: 19 bit_size: 1 - enum: I2C_PB9_FMP + enum: FMP - name: I2C1_FMP - description: I2C1 Fast Mode Plus + description: | + I2C1 Fast Mode Plus + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits bit_offset: 20 bit_size: 1 - enum: I2C1_FMP + enum: FMP - name: I2C2_FMP - description: I2C2 Fast Mode Plus + description: | + I2C2 Fast Mode Plus + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits bit_offset: 21 bit_size: 1 - enum: I2C2_FMP + enum: FMP - name: ENCODER_MODE description: Encoder mode bit_offset: 22 bit_size: 2 enum: ENCODER_MODE - name: I2C3_FMP - description: I2C3 Fast Mode Plus + description: | + I2C3 Fast Mode Plus + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits bit_offset: 24 bit_size: 1 - enum: I2C3_FMP + enum: FMP - name: VBAT_MON description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input bit_offset: 24 @@ -170,22 +219,18 @@ fieldset/CFGR2: description: Cortex-M0 LOCKUP bit enable bit bit_offset: 0 bit_size: 1 - enum: LOCKUP_LOCK - name: SRAM_PARITY_LOCK description: SRAM parity lock bit bit_offset: 1 bit_size: 1 - enum: SRAM_PARITY_LOCK - name: PVD_LOCK description: PVD lock enable bit bit_offset: 2 bit_size: 1 - enum: PVD_LOCK - name: BYP_ADDR_PAR description: Bypass address bit 29 in parity calculation bit_offset: 4 bit_size: 1 - enum: BYP_ADDR_PAR - name: SRAM_PEF description: SRAM parity flag bit_offset: 8 @@ -224,10 +269,12 @@ fieldset/CFGR3: bit_size: 1 enum: DAC1_TRIG3_RMP - name: DAC1_TRIG5_RMP - description: DAC1_CH1 / DAC1_CH2 Trigger remap + description: | + DAC1_CH1 / DAC1_CH2 Trigger remap + 0: Not remapped + 1: DAC trigger is HRTIM1_DAC1_TRIG2 bit_offset: 17 bit_size: 1 - enum: DAC1_TRIG5_RMP fieldset/CFGR4: description: configuration register 4 fields: @@ -393,15 +440,6 @@ enum/ADC12_JEXT6_RMP: - name: Tim20 description: Trigger source is TIM20_TRGO2 value: 1 -enum/ADC2_DMA_RMP_CFGR1: - bit_size: 1 - variants: - - name: NotRemapped - description: ADC24 DMA requests mapped on DMA2 channels 1 and 2 - value: 2 - - name: Remapped - description: ADC24 DMA requests mapped on DMA2 channels 3 and 4 - value: 3 enum/ADC2_DMA_RMP_CFGR3: bit_size: 2 variants: @@ -465,15 +503,6 @@ enum/ADC34_JEXT5_RMP: - name: Tim20 description: Trigger source is TIM20_TRGO value: 1 -enum/BYP_ADDR_PAR: - bit_size: 1 - variants: - - name: NoBypass - description: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated - value: 0 - - name: Bypass - description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated - value: 1 enum/DAC1_TRIG3_RMP: bit_size: 1 variants: @@ -483,42 +512,6 @@ enum/DAC1_TRIG3_RMP: - name: HrTim1 description: DAC trigger is HRTIM1_DAC1_TRIG1 value: 1 -enum/DAC1_TRIG5_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC trigger is HRTIM1_DAC1_TRIG2 - value: 1 -enum/DAC1_TRIG_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices - value: 0 - - name: Remapped - description: DAC trigger is TIM3_TRGO - value: 1 -enum/DAC2_CH1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC2_CH1 DMA requests mapped on DMA1 channel 5 - value: 1 -enum/DAC_TRIG_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC trigger is TIM3_TRGO - value: 1 enum/ENCODER_MODE: bit_size: 2 variants: @@ -531,14 +524,14 @@ enum/ENCODER_MODE: - name: MapTim3Tim15 description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively value: 2 -enum/I2C1_FMP: +enum/FMP: bit_size: 1 variants: - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only + description: Standard value: 0 - name: FMP - description: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits + description: FM+ value: 1 enum/I2C1_RX_DMA_RMP: bit_size: 2 @@ -564,69 +557,6 @@ enum/I2C1_TX_DMA_RMP: - name: MapDma1Ch4 description: I2C1_TX mapped on DMA1 CH4 value: 2 -enum/I2C2_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits - value: 1 -enum/I2C3_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits - value: 1 -enum/I2C_PB6_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB6 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - value: 1 -enum/I2C_PB7_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB7 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - value: 1 -enum/I2C_PB8_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB8 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - value: 1 -enum/I2C_PB9_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - value: 1 -enum/LOCKUP_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT. - value: 0 - - name: Connected - description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 1 enum/MEM_MODE: bit_size: 2 variants: @@ -642,15 +572,6 @@ enum/MEM_MODE: - name: SRAM description: Embedded SRAM mapped at 0x0000_0000 value: 3 -enum/PVD_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: PVD interrupt disconnected from TIM15/16/17 Break input - value: 0 - - name: Connected - description: PVD interrupt connected to TIM15/16/17 Break input - value: 1 enum/SPI1_RX_DMA_RMP: bit_size: 2 variants: @@ -675,102 +596,3 @@ enum/SPI1_TX_DMA_RMP: - name: MapDma1Ch7 description: SPI1_TX mapped on DMA1 CH7 value: 2 -enum/SRAM_PARITY_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 0 - - name: Connected - description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 1 -enum/TIM16_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 - value: 0 - - name: Remapped - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 - value: 1 -enum/TIM17_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - value: 0 - - name: Remapped - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 - value: 1 -enum/TIM18_DAC2_OUT1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 - value: 0 - - name: Remapped - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 - value: 1 -enum/TIM1_ITR3_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: TIM1_ITR3 = TIM17_OC - value: 1 -enum/TIM6_DAC1_CH1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - value: 1 -enum/TIM6_DAC1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - value: 1 -enum/TIM6_DAC1_OUT1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 - value: 1 -enum/TIM7_DAC1_CH2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 - value: 1 -enum/TIM7_DAC1_OUT2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 - value: 0 - - name: Remapped - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 - value: 1 -enum/USB_IT_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively - value: 0 - - name: Remapped - description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively - value: 1 diff --git a/data/registers/usart_v1.yaml b/data/registers/usart_v1.yaml index 64bcf56..e12a0e3 100644 --- a/data/registers/usart_v1.yaml +++ b/data/registers/usart_v1.yaml @@ -267,10 +267,6 @@ fieldset/SR: description: LIN break detection flag bit_offset: 8 bit_size: 1 -fieldset/SR_USART: - extends: SR - description: Status register - fields: - name: CTS description: CTS flag bit_offset: 9 diff --git a/data/registers/usart_v2.yaml b/data/registers/usart_v2.yaml index c8c04e6..7fe23e2 100644 --- a/data/registers/usart_v2.yaml +++ b/data/registers/usart_v2.yaml @@ -276,10 +276,6 @@ fieldset/SR: description: LIN break detection flag bit_offset: 8 bit_size: 1 -fieldset/SR_USART: - extends: SR - description: Status register - fields: - name: CTS description: CTS flag bit_offset: 9 diff --git a/stm32-data-gen/Cargo.toml b/stm32-data-gen/Cargo.toml index 03ba382..4eb95f4 100644 --- a/stm32-data-gen/Cargo.toml +++ b/stm32-data-gen/Cargo.toml @@ -10,14 +10,14 @@ default = ["rayon"] rayon = ["dep:rayon"] [dependencies] -anyhow = "1.0.70" +anyhow = "1.0.79" glob = "0.3.1" num = "0.4.0" quick-xml = { version = "0.26.0", features = ["serialize"] } regex = "1.7.1" serde = { version = "1.0.157", features = ["derive"] } serde_yaml = "0.9.19" -chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "0621765f915cedb0a9242a888c1909374ebbf4fa" } +chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "67c6adc50306696e664ba5f71cd4db9d6dd9c46b" } serde_json = "1.0.94" rayon = { version = "1.7.0", optional = true } stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" } diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 7e1d238..77f3b5a 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -491,6 +491,7 @@ impl PeriMatcher { ("STM32U5.*:TAMP:.*", ("tamp", "u5", "TAMP")), ("STM32WL.*:TAMP:.*", ("tamp", "wl", "TAMP")), (".*:OCTOSPIM:OCTOSPIM:.*", ("octospim", "v1", "OCTOSPIM")), + // it's actually STM32L4+, not STM32L4 ( "STM32L4.*:OCTOSPI[12]:OCTOSPI:octospi_v1_0.*", ("octospi", "v1", "OCTOSPI"), diff --git a/stm32-data-gen/src/registers.rs b/stm32-data-gen/src/registers.rs index fd2cd84..4392a18 100644 --- a/stm32-data-gen/src/registers.rs +++ b/stm32-data-gen/src/registers.rs @@ -1,7 +1,8 @@ use std::collections::HashMap; use anyhow::anyhow; -use chiptool::ir::{BlockItemInner, IR}; +use chiptool::ir::IR; +use chiptool::validate; pub struct Registers { pub registers: HashMap, @@ -24,28 +25,23 @@ impl Registers { .map_err(|e| anyhow!("failed to parse {f:?}: {e:?}"))?; // validate yaml file - for (name, block) in &ir.blocks { - for item in &block.items { - match &item.inner { - BlockItemInner::Block(inner_block) => { - if !ir.blocks.contains_key(&inner_block.block) { - return Err(anyhow!( - "block {name} specified block {} but it does not exist", - inner_block.block - )); - } - } - BlockItemInner::Register(inner_register) => { - if let Some(fieldset) = &inner_register.fieldset { - if !ir.fieldsets.contains_key(fieldset) { - return Err(anyhow!( - "block {name} specified fieldset {fieldset} but it does not exist", - )); - } - } - } - } - } + // we allow register overlap and field overlap for now + let validate_option = validate::Options { + allow_register_overlap: true, + allow_field_overlap: true, + allow_enum_dup_value: false, + allow_unused_enums: false, + allow_unused_fieldsets: false, + }; + let err_vec = validate::validate(&ir, validate_option); + let err_string = err_vec.iter().fold(String::new(), |mut acc, cur| { + acc.push_str(cur); + acc.push('\n'); + acc + }); + + if !err_string.is_empty() { + return Err(anyhow!(format!("\n{ff}:\n{err_string}"))); } registers.insert(ff, ir); diff --git a/stm32-metapac-gen/Cargo.toml b/stm32-metapac-gen/Cargo.toml index 16e6c43..fc5c430 100644 --- a/stm32-metapac-gen/Cargo.toml +++ b/stm32-metapac-gen/Cargo.toml @@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0" [dependencies] regex = "1.7.1" -chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "0621765f915cedb0a9242a888c1909374ebbf4fa" } +chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "67c6adc50306696e664ba5f71cd4db9d6dd9c46b" } serde = { version = "1.0.157", features = [ "derive" ] } serde_json = "1.0.94" proc-macro2 = "1.0.52" diff --git a/transforms/SYSCFG_F0.yaml b/transforms/SYSCFG_F0.yaml new file mode 100644 index 0000000..e1fd25f --- /dev/null +++ b/transforms/SYSCFG_F0.yaml @@ -0,0 +1,13 @@ +transforms: + - !DeleteEnums + from: .*_RMP2? + bit_size: 1 + keep_desc: true + + - !MergeEnums + from: .*_FMP + to: FMP + keep_desc: true + + - !DeleteEnums + from: ^(LOCKUP_LOCK|PVD_LOCK|SRAM_PARITY_LOCK)$ diff --git a/transforms/SYSCFG_F3.yaml b/transforms/SYSCFG_F3.yaml index 0d52e10..dbddfbc 100644 --- a/transforms/SYSCFG_F3.yaml +++ b/transforms/SYSCFG_F3.yaml @@ -7,3 +7,31 @@ transforms: fieldsets: CFGR1 from: FPU_IE\d to: FPU_IE + + - !DeleteEnums + from: ADC2_DMA_RMP_CFGR1 + bit_size: 1 + keep_desc: true + + - !DeleteEnums + from: (DAC1_TRIG5_RMP|DAC1_TRIG_RMP|DAC2_CH1_DMA_RMP|DAC_TRIG_RMP) + bit_size: 1 + keep_desc: true + + - !DeleteEnums + from: (TIM16_DMA_RMP|TIM17_DMA_RMP|TIM18_DAC2_OUT1_DMA_RMP|TIM1_ITR3_RMP|TIM6_DAC1_CH1_DMA_RMP|TIM6_DAC1_DMA_RMP|TIM6_DAC1_OUT1_DMA_RMP|TIM7_DAC1_CH2_DMA_RMP|TIM7_DAC1_OUT2_DMA_RMP) + bit_size: 1 + keep_desc: true + + - !DeleteEnums + from: USB_IT_RMP + bit_size: 1 + keep_desc: true + + - !MergeEnums + from: .*_FMP + to: FMP + keep_desc: true + + - !DeleteEnums + from: ^(BYP_ADDR_PAR|LOCKUP_LOCK|PVD_LOCK|SRAM_PARITY_LOCK)$