copy and check desc and variant from v2

2024-02-22 00:21:28 +08:00 · 2024-02-22 00:21:28 +08:00 · 9ea25e944d
commit 9ea25e944d
parent 6d0865711f
1 changed files with 62 additions and 18 deletions
--- a/data/registers/iwdg_v3.yaml
+++ b/data/registers/iwdg_v3.yaml
@ -1,24 +1,24 @@
 block/IWDG:
-  description: Independent watchdog.
+  description: Independent watchdog
  items:
  - name: KR
-    description: IWDG key register.
+    description: Key register
    byte_offset: 0
    fieldset: KR
  - name: PR
-    description: IWDG prescaler register.
+    description: Prescaler register
    byte_offset: 4
    fieldset: PR
  - name: RLR
-    description: IWDG reload register.
+    description: Reload register
    byte_offset: 8
    fieldset: RLR
  - name: SR
-    description: IWDG status register.
+    description: Status register
    byte_offset: 12
    fieldset: SR
  - name: WINR
-    description: IWDG window register.
+    description: Window register
    byte_offset: 16
    fieldset: WINR
  - name: EWCR
@ -41,39 +41,41 @@ fieldset/EWCR:
    bit_offset: 15
    bit_size: 1
 fieldset/KR:
-  description: IWDG key register.
+  description: Key register
  fields:
  - name: KEY
-    description: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see ) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected).
+    description: Key value (write only, read 0000h)
    bit_offset: 0
    bit_size: 16
+    enum: KEY
 fieldset/PR:
-  description: IWDG prescaler register.
+  description: Prescaler register
  fields:
  - name: PR
-    description: 'Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Others: divider / 1024 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.'
+    description: Prescaler divider
    bit_offset: 0
    bit_size: 4
+    enum: PR
 fieldset/RLR:
-  description: IWDG reload register.
+  description: Reload register
  fields:
  - name: RL
-    description: 'Watchdog counter reload value These bits are write access protected see . They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the . The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. The RVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the status register (IWDG_SR) is reset.'
+    description: Watchdog counter reload value
    bit_offset: 0
    bit_size: 12
 fieldset/SR:
-  description: IWDG status register.
+  description: Status register
  fields:
  - name: PVU
-    description: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The prescaler value can be updated only when PVU bit is reset.
+    description: Watchdog prescaler value update
    bit_offset: 0
    bit_size: 1
  - name: RVU
-    description: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The reload value can be updated only when RVU bit is reset.
+    description: Watchdog counter reload value update
    bit_offset: 1
    bit_size: 1
  - name: WVU
-    description: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The window value can be updated only when WVU bit is reset. This bit is generated only if generic “window” = 1.
+    description: Watchdog counter window value update
    bit_offset: 2
    bit_size: 1
  - name: EWU
@ -85,9 +87,51 @@ fieldset/SR:
    bit_offset: 14
    bit_size: 1
 fieldset/WINR:
-  description: IWDG window register.
+  description: Window register
  fields:
  - name: WIN
-    description: 'Watchdog counter window value These bits are write access protected, see , they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0]+1 and greater than 1. The WVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the (IWDG_SR) is reset.'
+    description: Watchdog counter window value
    bit_offset: 0
    bit_size: 12
+enum/KEY:
+  bit_size: 16
+  variants:
+  - name: Enable
+    description: Enable access to PR, RLR and WINR registers (0x5555)
+    value: 21845
+  - name: Reset
+    description: Reset the watchdog value (0xAAAA)
+    value: 43690
+  - name: Start
+    description: Start the watchdog (0xCCCC)
+    value: 52428
+enum/PR:
+  bit_size: 4
+  variants:
+  - name: DivideBy4
+    description: Divider /4
+    value: 0
+  - name: DivideBy8
+    description: Divider /8
+    value: 1
+  - name: DivideBy16
+    description: Divider /16
+    value: 2
+  - name: DivideBy32
+    description: Divider /32
+    value: 3
+  - name: DivideBy64
+    description: Divider /64
+    value: 4
+  - name: DivideBy128
+    description: Divider /128
+    value: 5
+  - name: DivideBy256
+    description: Divider /256
+    value: 6
+  - name: DivideBy512
+    description: Divider /512
+    value: 7
+  - name: DivideBy1024
+    description: Divider /1024
+    value: 8