diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index f64e561..a62cb68 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -691,6 +691,10 @@ fn process_core(
         want_nvic_name
     };
     let chip_nvic = group.ips.values().find(|x| x.name == want_nvic_name).unwrap();
+
+    // With the current data sources, this value is always either 2 or 4, and never unwraps to None(0)
+    let nvic_priority_bits = *(defines.0.get("__NVIC_PRIO_BITS").unwrap_or(&0)) as u8;
+
     let mut header_irqs = h.interrupts.get(core_name).unwrap().clone();
     let chip_irqs = chip_interrupts
         .0
@@ -963,6 +967,7 @@ fn process_core(
     stm32_data_serde::chip::Core {
         name: real_core_name.clone(),
         peripherals,
+        nvic_priority_bits,
         interrupts,
         dma_channels: core_dma_channels,
     }
diff --git a/stm32-data-serde/src/lib.rs b/stm32-data-serde/src/lib.rs
index 1280645..46fc255 100644
--- a/stm32-data-serde/src/lib.rs
+++ b/stm32-data-serde/src/lib.rs
@@ -62,6 +62,7 @@ pub mod chip {
     pub struct Core {
         pub name: String,
         pub peripherals: Vec<core::Peripheral>,
+        pub nvic_priority_bits: u8,
         pub interrupts: Vec<core::Interrupt>,
         pub dma_channels: Vec<core::DmaChannels>,
     }
diff --git a/stm32-metapac-gen/res/Cargo.toml b/stm32-metapac-gen/res/Cargo.toml
index 5999220..4b9a9c1 100644
--- a/stm32-metapac-gen/res/Cargo.toml
+++ b/stm32-metapac-gen/res/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "stm32-metapac"
-version = "0.1.0"
+version = "1.0.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/stm32-data"
diff --git a/stm32-metapac-gen/res/src/metadata.rs b/stm32-metapac-gen/res/src/metadata.rs
index d05830e..3e7efc0 100644
--- a/stm32-metapac-gen/res/src/metadata.rs
+++ b/stm32-metapac-gen/res/src/metadata.rs
@@ -5,6 +5,7 @@ pub struct Metadata {
     pub line: &'static str,
     pub memory: &'static [MemoryRegion],
     pub peripherals: &'static [Peripheral],
+    pub nvic_priority_bits: u8,
     pub interrupts: &'static [Interrupt],
     pub dma_channels: &'static [DmaChannel],
 }
diff --git a/stm32-metapac-gen/src/data.rs b/stm32-metapac-gen/src/data.rs
index 17eccfe..3298398 100644
--- a/stm32-metapac-gen/src/data.rs
+++ b/stm32-metapac-gen/src/data.rs
@@ -38,6 +38,7 @@ pub enum MemoryRegionKind {
 pub struct Core {
     pub name: String,
     pub peripherals: Vec<Peripheral>,
+    pub nvic_priority_bits: u8,
     pub interrupts: Vec<Interrupt>,
     pub dma_channels: Vec<DmaChannel>,
 }
diff --git a/stm32-metapac-gen/src/lib.rs b/stm32-metapac-gen/src/lib.rs
index d98e666..4a91e2c 100644
--- a/stm32-metapac-gen/src/lib.rs
+++ b/stm32-metapac-gen/src/lib.rs
@@ -50,6 +50,7 @@ impl Gen {
         let mut ir = ir::IR::new();
 
         let mut dev = ir::Device {
+            nvic_priority_bits: core.nvic_priority_bits,
             interrupts: Vec::new(),
             peripherals: Vec::new(),
         };
@@ -194,6 +195,7 @@ impl Gen {
                 line: {:?},
                 memory: {},
                 peripherals: PERIPHERALS,
+                nvic_priority_bits: {},
                 interrupts: INTERRUPTS,
                 dma_channels: DMA_CHANNELS,
             }};",
@@ -202,6 +204,7 @@ impl Gen {
             &chip.family,
             &chip.line,
             stringify(&chip.memory),
+            &core.nvic_priority_bits,
         );
 
         let mut file = File::create(chip_dir.join("metadata.rs")).unwrap();