From 454854d5275c5cde6f24df26b059958ddd646f5c Mon Sep 17 00:00:00 2001 From: Dominik Boehi Date: Sat, 19 Jun 2021 19:17:25 +0200 Subject: [PATCH 1/3] Add EXTI for STM32WB55 --- data/registers/exti_wb55.yaml | 450 ++++++++++++++++++++++++++++++++++ parse.py | 18 +- 2 files changed, 465 insertions(+), 3 deletions(-) create mode 100644 data/registers/exti_wb55.yaml diff --git a/data/registers/exti_wb55.yaml b/data/registers/exti_wb55.yaml new file mode 100644 index 0000000..899a6d0 --- /dev/null +++ b/data/registers/exti_wb55.yaml @@ -0,0 +1,450 @@ +--- +block/EXTI: + description: External interrupt/event controller + items: + - name: RTSR1 + description: rising trigger selection register + byte_offset: 0 + fieldset: RTSR1 + - name: FTSR1 + description: falling trigger selection register + byte_offset: 4 + fieldset: FTSR1 + - name: SWIER1 + description: software interrupt event register + byte_offset: 8 + fieldset: SWIER1 + - name: PR1 + description: EXTI pending register + byte_offset: 12 + fieldset: PR1 + - name: RTSR2 + description: rising trigger selection register + byte_offset: 32 + fieldset: RTSR2 + - name: FTSR2 + description: falling trigger selection register + byte_offset: 36 + fieldset: FTSR2 + - name: SWIER2 + description: software interrupt event register + byte_offset: 40 + fieldset: SWIER2 + - name: PR2 + description: pending register + byte_offset: 44 + fieldset: PR2 + - name: C1IMR1 + description: CPUm wakeup with interrupt mask register + byte_offset: 128 + fieldset: C1IMR1 + - name: C1EMR1 + description: CPUm wakeup with event mask register + byte_offset: 132 + fieldset: C1EMR1 + - name: C1IMR2 + description: CPUm wakeup with interrupt mask register + byte_offset: 144 + fieldset: C1IMR2 + - name: C1EMR2 + description: CPUm wakeup with event mask register + byte_offset: 148 + fieldset: C1EMR2 + - name: C2IMR1 + description: CPUm wakeup with interrupt mask register + byte_offset: 192 + fieldset: C2IMR1 + - name: C2EMR1 + description: CPUm wakeup with event mask register + byte_offset: 196 + fieldset: C2EMR1 + - name: C2IMR2 + description: CPUm wakeup with interrupt mask register + byte_offset: 208 + fieldset: C2IMR2 + - name: C2EMR2 + description: CPUm wakeup with event mask register + byte_offset: 212 + fieldset: C2EMR2 + - name: HWCFGR7 + description: EXTI Hardware configuration registers + byte_offset: 984 + access: Read + fieldset: HWCFGR7 + - name: HWCFGR6 + description: Hardware configuration registers + byte_offset: 988 + access: Read + fieldset: HWCFGR6 + - name: HWCFGR5 + description: Hardware configuration registers + byte_offset: 992 + access: Read + fieldset: HWCFGR5 + - name: HWCFGR4 + description: Hardware configuration registers + byte_offset: 996 + access: Read + fieldset: HWCFGR4 + - name: HWCFGR3 + description: Hardware configuration registers + byte_offset: 1000 + access: Read + fieldset: HWCFGR3 + - name: HWCFGR2 + description: Hardware configuration registers + byte_offset: 1004 + access: Read + fieldset: HWCFGR2 + - name: HWCFGR1 + description: Hardware configuration register 1 + byte_offset: 1008 + access: Read + fieldset: HWCFGR1 + - name: VERR + description: EXTI IP Version register + byte_offset: 1012 + access: Read + fieldset: VERR + - name: IPIDR + description: Identification register + byte_offset: 1016 + access: Read + fieldset: IPIDR + - name: SIDR + description: Size ID register + byte_offset: 1020 + access: Read + fieldset: SIDR +fieldset/C1EMR1: + description: CPUm wakeup with event mask register + fields: + - name: EM0_15 + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 0 + bit_size: 16 + - name: EM17_21 + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 17 + bit_size: 5 +fieldset/C1EMR2: + description: CPUm wakeup with event mask register + fields: + - name: EM + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 8 + bit_size: 2 +fieldset/C1IMR1: + description: CPUm wakeup with interrupt mask register + fields: + - name: IM + description: CPU(m) wakeup with interrupt Mask on Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: MR +fieldset/C1IMR2: + description: CPUm wakeup with interrupt mask register + fields: + - name: IM + description: CPUm Wakeup with interrupt Mask on Event input + bit_offset: 0 + bit_size: 1 + array: + len: 17 + stride: 1 + enum: MR +fieldset/C2EMR1: + description: CPUm wakeup with event mask register + fields: + - name: EM0_15 + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 0 + bit_size: 16 + - name: EM17_21 + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 17 + bit_size: 5 +fieldset/C2EMR2: + description: CPUm wakeup with event mask register + fields: + - name: EM + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 8 + bit_size: 2 +fieldset/C2IMR1: + description: CPUm wakeup with interrupt mask register + fields: + - name: IM + description: CPU(m) wakeup with interrupt Mask on Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: MR +fieldset/C2IMR2: + description: CPUm wakeup with interrupt mask register + fields: + - name: IM + description: CPUm Wakeup with interrupt Mask on Event input + bit_offset: 0 + bit_size: 1 + array: + len: 17 + stride: 1 + enum: MR +fieldset/FTSR1: + description: falling trigger selection register + fields: + - name: FT + description: Falling trigger event configuration bit of Configurable Event input + bit_offset: 0 + bit_size: 1 + array: + len: 22 + stride: 1 + enum: FT + - name: FT_31 + description: Falling trigger event configuration bit of Configurable Event input + bit_offset: 31 + bit_size: 1 + enum: FT +fieldset/FTSR2: + description: falling trigger selection register + fields: + - name: FT + description: Falling trigger event configuration bit of Configurable Event input + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: FT + - name: FT40_41 + description: Falling trigger event configuration bit of Configurable Event input + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: FT +fieldset/HWCFGR1: + description: Hardware configuration register 1 + fields: + - name: NBEVENTS + description: HW configuration number of event + bit_offset: 0 + bit_size: 8 + - name: NBCPUS + description: HW configuration number of CPUs + bit_offset: 8 + bit_size: 4 + - name: CPUEVTEN + description: HW configuration of CPU(m) event output enable + bit_offset: 12 + bit_size: 4 +fieldset/HWCFGR2: + description: Hardware configuration registers + fields: + - name: EVENT_TRG + description: HW configuration event trigger type + bit_offset: 0 + bit_size: 32 +fieldset/HWCFGR3: + description: Hardware configuration registers + fields: + - name: EVENT_TRG + description: HW configuration event trigger type + bit_offset: 0 + bit_size: 32 +fieldset/HWCFGR4: + description: Hardware configuration registers + fields: + - name: EVENT_TRG + description: HW configuration event trigger type + bit_offset: 0 + bit_size: 32 +fieldset/HWCFGR5: + description: Hardware configuration registers + fields: + - name: CPUEVENT + description: HW configuration CPU event generation + bit_offset: 0 + bit_size: 32 +fieldset/HWCFGR6: + description: Hardware configuration registers + fields: + - name: CPUEVENT + description: HW configuration CPU event generation + bit_offset: 0 + bit_size: 32 +fieldset/HWCFGR7: + description: EXTI Hardware configuration registers + fields: + - name: CPUEVENT + description: HW configuration CPU event generation + bit_offset: 0 + bit_size: 32 +fieldset/IPIDR: + description: Identification register + fields: + - name: IPID + description: IP Identification + bit_offset: 0 + bit_size: 32 +fieldset/PR1: + description: EXTI pending register + fields: + - name: PIF + description: Configurable event inputs Pending bit + bit_offset: 0 + bit_size: 1 + array: + len: 22 + stride: 1 + enum_read: PRR + enum_write: PRW + - name: PIF_31 + description: Configurable event inputs Pending bit + bit_offset: 31 + bit_size: 1 + enum_read: PRR + enum_write: PRW +fieldset/PR2: + description: pending register + fields: + - name: PIF + description: Configurable event inputs x+32 Pending bit. + bit_offset: 1 + bit_size: 1 + enum_read: PRR + enum_write: PRW + - name: PIF40_41 + description: Configurable event inputs x+32 Pending bit. + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + enum_read: PRR + enum_write: PRW +fieldset/RTSR1: + description: rising trigger selection register + fields: + - name: RT + description: Rising trigger event configuration bit of Configurable Event input + bit_offset: 0 + bit_size: 22 + array: + len: 22 + stride: 1 + enum: RT + - name: RT_31 + description: Rising trigger event configuration bit of Configurable Event input + bit_offset: 31 + bit_size: 1 + enum: RT +fieldset/RTSR2: + description: rising trigger selection register + fields: + - name: RT + description: Rising trigger event configuration bit of Configurable Event input + bit_offset: 1 + bit_size: 1 + enum: RT + - name: RT40_41 + description: Rising trigger event configuration bit of Configurable Event input + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: RT +fieldset/SIDR: + description: Size ID register + fields: + - name: SID + description: Size Identification + bit_offset: 0 + bit_size: 32 +fieldset/SWIER1: + description: software interrupt event register + fields: + - name: SWI + description: Software interrupt on event + bit_offset: 0 + bit_size: 22 + - name: SWI_31 + description: Software interrupt on event + bit_offset: 31 + bit_size: 1 +fieldset/SWIER2: + description: software interrupt event register + fields: + - name: SWI + description: Software interrupt on event + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 0 + - name: SWI40_41 + description: Software interrupt on event + bit_offset: 8 + bit_size: 2 +fieldset/VERR: + description: EXTI IP Version register + fields: + - name: MINREV + description: Minor Revision number + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major Revision number + bit_offset: 4 + bit_size: 4 +enum/FT: + bit_size: 1 + variants: + - name: Disabled + description: Falling edge trigger is disabled + value: 0 + - name: Enabled + description: Falling edge trigger is enabled + value: 1 +enum/RT: + bit_size: 1 + variants: + - name: Disabled + description: Falling edge trigger is disabled + value: 0 + - name: Enabled + description: Falling edge trigger is enabled + value: 1 +enum/MR: + bit_size: 1 + variants: + - name: Masked + description: Interrupt request line is masked + value: 0 + - name: Unmasked + description: Interrupt request line is unmasked + value: 1 +enum/PRR: + bit_size: 1 + variants: + - name: NotPending + description: No trigger request occurred + value: 0 + - name: Pending + description: Selected trigger request occurred + value: 1 +enum/PRW: + bit_size: 1 + variants: + - name: Clear + description: Clears pending bit + value: 1 diff --git a/parse.py b/parse.py index 72809e3..33b137c 100644 --- a/parse.py +++ b/parse.py @@ -1,5 +1,10 @@ import xmltodict import yaml +try: + from yaml import CSafeLoader as SafeLoader +except ImportError: + from yaml import SafeLoader + import re import json import os @@ -66,7 +71,7 @@ def children(x, key): headers_parsed = {} header_map = {} with open('header_map.yaml', 'r') as f: - y = yaml.load(f, Loader=yaml.SafeLoader) + y = yaml.load(f, Loader=SafeLoader) for header, chips in y.items(): for chip in chips.split(','): header_map[chip.strip().lower()] = header.lower() @@ -556,6 +561,7 @@ def parse_chips(): #print("Defining for core", core_name) # Gather all interrupts and defines for this core + interrupts = h['interrupts'][core_name] defines = h['defines'][core_name] @@ -605,7 +611,7 @@ def parse_chips(): family_extra = "data/extra/family/" + chip['family'] + ".yaml" if os.path.exists(family_extra): with open(family_extra) as extra_f: - extra = yaml.load(extra_f, Loader=yaml.SafeLoader) + extra = yaml.load(extra_f, Loader=SafeLoader) for (extra_name, extra_p) in extra['peripherals'].items(): peris[extra_name] = extra_p @@ -637,10 +643,15 @@ def parse_chips(): # EXTI is not in the cubedb XMLs if addr := defines.get('EXTI_BASE'): + if chip_name.startswith("STM32WB55"): + block = 'exti_wb55/EXTI' + else: + block = 'exti_v1/EXTI' + peris['EXTI'] = OrderedDict({ 'address': addr, 'kind': 'EXTI', - 'block': 'exti_v1/EXTI', + 'block': block, }) # FLASH is not in the cubedb XMLs @@ -675,6 +686,7 @@ def parse_chips(): if block := match_peri(kind): crs_peri['block'] = block peris['CRS'] = crs_peri + core['peripherals'] = peris # remove all pins from the root of the chip before emitting. From 481e607977a5293a80dfbf9a921b1f004c1d4287 Mon Sep 17 00:00:00 2001 From: Dominik Boehi Date: Sun, 20 Jun 2021 14:30:09 +0200 Subject: [PATCH 2/3] Add IPCC peripheral to STM32WB55 --- data/registers/ipcc_v1.yaml | 202 ++++++++++++++++++++++++++++++++++++ parse.py | 2 + 2 files changed, 204 insertions(+) create mode 100644 data/registers/ipcc_v1.yaml diff --git a/data/registers/ipcc_v1.yaml b/data/registers/ipcc_v1.yaml new file mode 100644 index 0000000..9b42679 --- /dev/null +++ b/data/registers/ipcc_v1.yaml @@ -0,0 +1,202 @@ +--- +block/IPCC: + description: IPCC + items: + - name: C1CR + description: Control register CPU1 + byte_offset: 0 + fieldset: C1CR + - name: C1MR + description: Mask register CPU1 + byte_offset: 4 + fieldset: C1MR + - name: C1SCR + description: Status Set or Clear register CPU1 + byte_offset: 8 + access: Write + fieldset: C1SCR + - name: C1TO2SR + description: CPU1 to CPU2 status register + byte_offset: 12 + access: Read + fieldset: C1TO2SR + - name: C2CR + description: Control register CPU2 + byte_offset: 16 + fieldset: C2CR + - name: C2MR + description: Mask register CPU2 + byte_offset: 20 + fieldset: C2MR + - name: C2SCR + description: Status Set or Clear register CPU2 + byte_offset: 24 + access: Write + fieldset: C2SCR + - name: C2TOC1SR + description: CPU2 to CPU1 status register + byte_offset: 28 + access: Read + fieldset: C2TOC1SR + - name: HWCFGR + description: IPCC Hardware configuration register + byte_offset: 1008 + access: Read + fieldset: HWCFGR + - name: VERR + description: IPCC version register + byte_offset: 1012 + access: Read + fieldset: VERR + - name: IPIDR + description: IPCC indentification register + byte_offset: 1016 + access: Read + fieldset: IPIDR + - name: SIDR + description: IPCC size indentification register + byte_offset: 1020 + access: Read + fieldset: SIDR +fieldset/C1CR: + description: Control register CPU1 + fields: + - name: RXOIE + description: processor 1 Receive channel occupied interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXFIE + description: processor 1 Transmit channel free interrupt enable + bit_offset: 16 + bit_size: 1 +fieldset/C1MR: + description: Mask register CPU1 + fields: + - name: CHOM + description: processor 1 Receive channel x occupied interrupt enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHFM + description: processor 1 Transmit channel x free interrupt mask + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C1SCR: + description: Status Set or Clear register CPU1 + fields: + - name: CHC + description: processor 1 Receive channel x status clear + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHS + description: processor 1 Transmit channel x status set + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C1TO2SR: + description: CPU1 to CPU2 status register + fields: + - name: CHF + description: processor 1 transmit to process 2 Receive channel x status flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C2CR: + description: Control register CPU2 + fields: + - name: RXOIE + description: processor 2 Receive channel occupied interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXFIE + description: processor 2 Transmit channel free interrupt enable + bit_offset: 16 + bit_size: 1 +fieldset/C2MR: + description: Mask register CPU2 + fields: + - name: CHOM + description: processor 2 Receive channel x occupied interrupt enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHFM + description: processor 2 Transmit channel 1 free interrupt mask + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C2SCR: + description: Status Set or Clear register CPU2 + fields: + - name: CHC + description: processor 2 Receive channel x status clear + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHS + description: processor 2 Transmit channel 1 status set + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C2TOC1SR: + description: CPU2 to CPU1 status register + fields: + - name: CHF + description: processor 2 transmit to process 1 Receive channel x status flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/HWCFGR: + description: IPCC Hardware configuration register + fields: + - name: CHANNELS + description: "Number of channels per CPU supported by the IP, range 1 to 16" + bit_offset: 0 + bit_size: 8 +fieldset/IPIDR: + description: IPCC indentification register + fields: + - name: IPID + description: Identification Code + bit_offset: 0 + bit_size: 32 +fieldset/SIDR: + description: IPCC size indentification register + fields: + - name: SID + description: Size Identification Code + bit_offset: 0 + bit_size: 32 +fieldset/VERR: + description: IPCC version register + fields: + - name: MINREV + description: Minor Revision + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major Revision + bit_offset: 4 + bit_size: 4 diff --git a/parse.py b/parse.py index 33b137c..3e0d585 100644 --- a/parse.py +++ b/parse.py @@ -344,6 +344,8 @@ perimap = [ ('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'), ('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'), ('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'), + + ('.*:IPCC:v1_0', 'ipcc_v1/IPCC'), ] rng_clock_map = [ From 51395f941a61aec8ea209ac43f40c357a9079fe9 Mon Sep 17 00:00:00 2001 From: Dominik Boehi Date: Mon, 21 Jun 2021 17:47:55 +0200 Subject: [PATCH 3/3] Use arrays and blocks for everything in EXTI --- data/registers/exti_wb55.yaml | 446 +++++++--------------------------- data/registers/ipcc_v1.yaml | 92 ++----- 2 files changed, 101 insertions(+), 437 deletions(-) diff --git a/data/registers/exti_wb55.yaml b/data/registers/exti_wb55.yaml index 899a6d0..516901f 100644 --- a/data/registers/exti_wb55.yaml +++ b/data/registers/exti_wb55.yaml @@ -2,300 +2,91 @@ block/EXTI: description: External interrupt/event controller items: - - name: RTSR1 + - name: RTSR description: rising trigger selection register byte_offset: 0 - fieldset: RTSR1 - - name: FTSR1 - description: falling trigger selection register - byte_offset: 4 - fieldset: FTSR1 - - name: SWIER1 - description: software interrupt event register - byte_offset: 8 - fieldset: SWIER1 - - name: PR1 - description: EXTI pending register - byte_offset: 12 - fieldset: PR1 - - name: RTSR2 - description: rising trigger selection register - byte_offset: 32 - fieldset: RTSR2 - - name: FTSR2 - description: falling trigger selection register - byte_offset: 36 - fieldset: FTSR2 - - name: SWIER2 - description: software interrupt event register - byte_offset: 40 - fieldset: SWIER2 - - name: PR2 - description: pending register - byte_offset: 44 - fieldset: PR2 - - name: C1IMR1 - description: CPUm wakeup with interrupt mask register - byte_offset: 128 - fieldset: C1IMR1 - - name: C1EMR1 - description: CPUm wakeup with event mask register - byte_offset: 132 - fieldset: C1EMR1 - - name: C1IMR2 - description: CPUm wakeup with interrupt mask register - byte_offset: 144 - fieldset: C1IMR2 - - name: C1EMR2 - description: CPUm wakeup with event mask register - byte_offset: 148 - fieldset: C1EMR2 - - name: C2IMR1 - description: CPUm wakeup with interrupt mask register - byte_offset: 192 - fieldset: C2IMR1 - - name: C2EMR1 - description: CPUm wakeup with event mask register - byte_offset: 196 - fieldset: C2EMR1 - - name: C2IMR2 - description: CPUm wakeup with interrupt mask register - byte_offset: 208 - fieldset: C2IMR2 - - name: C2EMR2 - description: CPUm wakeup with event mask register - byte_offset: 212 - fieldset: C2EMR2 - - name: HWCFGR7 - description: EXTI Hardware configuration registers - byte_offset: 984 - access: Read - fieldset: HWCFGR7 - - name: HWCFGR6 - description: Hardware configuration registers - byte_offset: 988 - access: Read - fieldset: HWCFGR6 - - name: HWCFGR5 - description: Hardware configuration registers - byte_offset: 992 - access: Read - fieldset: HWCFGR5 - - name: HWCFGR4 - description: Hardware configuration registers - byte_offset: 996 - access: Read - fieldset: HWCFGR4 - - name: HWCFGR3 - description: Hardware configuration registers - byte_offset: 1000 - access: Read - fieldset: HWCFGR3 - - name: HWCFGR2 - description: Hardware configuration registers - byte_offset: 1004 - access: Read - fieldset: HWCFGR2 - - name: HWCFGR1 - description: Hardware configuration register 1 - byte_offset: 1008 - access: Read - fieldset: HWCFGR1 - - name: VERR - description: EXTI IP Version register - byte_offset: 1012 - access: Read - fieldset: VERR - - name: IPIDR - description: Identification register - byte_offset: 1016 - access: Read - fieldset: IPIDR - - name: SIDR - description: Size ID register - byte_offset: 1020 - access: Read - fieldset: SIDR -fieldset/C1EMR1: - description: CPUm wakeup with event mask register - fields: - - name: EM0_15 - description: CPU(m) Wakeup with event generation Mask on Event input - bit_offset: 0 - bit_size: 16 - - name: EM17_21 - description: CPU(m) Wakeup with event generation Mask on Event input - bit_offset: 17 - bit_size: 5 -fieldset/C1EMR2: - description: CPUm wakeup with event mask register - fields: - - name: EM - description: CPU(m) Wakeup with event generation Mask on Event input - bit_offset: 8 - bit_size: 2 -fieldset/C1IMR1: - description: CPUm wakeup with interrupt mask register - fields: - - name: IM - description: CPU(m) wakeup with interrupt Mask on Event input - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 - enum: MR -fieldset/C1IMR2: - description: CPUm wakeup with interrupt mask register - fields: - - name: IM - description: CPUm Wakeup with interrupt Mask on Event input - bit_offset: 0 - bit_size: 1 - array: - len: 17 - stride: 1 - enum: MR -fieldset/C2EMR1: - description: CPUm wakeup with event mask register - fields: - - name: EM0_15 - description: CPU(m) Wakeup with event generation Mask on Event input - bit_offset: 0 - bit_size: 16 - - name: EM17_21 - description: CPU(m) Wakeup with event generation Mask on Event input - bit_offset: 17 - bit_size: 5 -fieldset/C2EMR2: - description: CPUm wakeup with event mask register - fields: - - name: EM - description: CPU(m) Wakeup with event generation Mask on Event input - bit_offset: 8 - bit_size: 2 -fieldset/C2IMR1: - description: CPUm wakeup with interrupt mask register - fields: - - name: IM - description: CPU(m) wakeup with interrupt Mask on Event input - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 - enum: MR -fieldset/C2IMR2: - description: CPUm wakeup with interrupt mask register - fields: - - name: IM - description: CPUm Wakeup with interrupt Mask on Event input - bit_offset: 0 - bit_size: 1 - array: - len: 17 - stride: 1 - enum: MR -fieldset/FTSR1: - description: falling trigger selection register - fields: - - name: FT - description: Falling trigger event configuration bit of Configurable Event input - bit_offset: 0 - bit_size: 1 - array: - len: 22 - stride: 1 - enum: FT - - name: FT_31 - description: Falling trigger event configuration bit of Configurable Event input - bit_offset: 31 - bit_size: 1 - enum: FT -fieldset/FTSR2: - description: falling trigger selection register - fields: - - name: FT - description: Falling trigger event configuration bit of Configurable Event input - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 0 - enum: FT - - name: FT40_41 - description: Falling trigger event configuration bit of Configurable Event input - bit_offset: 8 - bit_size: 1 + fieldset: RTSR array: len: 2 + stride: 32 + - name: FTSR + description: falling trigger selection register + byte_offset: 4 + fieldset: FTSR + array: + len: 2 + stride: 32 + - name: SWIER + description: software interrupt event register + byte_offset: 8 + fieldset: SWIER + array: + len: 2 + stride: 32 + - name: PR + description: EXTI pending register + byte_offset: 12 + fieldset: PR + array: + len: 2 + stride: 32 + - name: CPU + description: CPU specific registers + byte_offset: 128 + block: CPU_MASK + array: + len: 2 + stride: 64 +block/CPU_MASK: + description: CPU-specific mask registers + items: + - name: IMR + description: CPUm wakeup with interrupt mask register + byte_offset: 0 + fieldset: C1IMR + array: + len: 2 + stride: 16 + - name: EMR + description: CPUm wakeup with event mask register + byte_offset: 4 + fieldset: C1EMR + array: + len: 2 + stride: 16 +fieldset/C1EMR: + description: CPUm wakeup with event mask register + fields: + - name: EM + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 0 + bit_size: 16 + array: + len: 32 + stride: 1 +fieldset/C1IMR: + description: CPUm wakeup with interrupt mask register + fields: + - name: IM + description: CPU(m) wakeup with interrupt Mask on Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: MR +fieldset/FTSR: + description: falling trigger selection register + fields: + - name: FT + description: Falling trigger event configuration bit of Configurable Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 stride: 1 enum: FT -fieldset/HWCFGR1: - description: Hardware configuration register 1 - fields: - - name: NBEVENTS - description: HW configuration number of event - bit_offset: 0 - bit_size: 8 - - name: NBCPUS - description: HW configuration number of CPUs - bit_offset: 8 - bit_size: 4 - - name: CPUEVTEN - description: HW configuration of CPU(m) event output enable - bit_offset: 12 - bit_size: 4 -fieldset/HWCFGR2: - description: Hardware configuration registers - fields: - - name: EVENT_TRG - description: HW configuration event trigger type - bit_offset: 0 - bit_size: 32 -fieldset/HWCFGR3: - description: Hardware configuration registers - fields: - - name: EVENT_TRG - description: HW configuration event trigger type - bit_offset: 0 - bit_size: 32 -fieldset/HWCFGR4: - description: Hardware configuration registers - fields: - - name: EVENT_TRG - description: HW configuration event trigger type - bit_offset: 0 - bit_size: 32 -fieldset/HWCFGR5: - description: Hardware configuration registers - fields: - - name: CPUEVENT - description: HW configuration CPU event generation - bit_offset: 0 - bit_size: 32 -fieldset/HWCFGR6: - description: Hardware configuration registers - fields: - - name: CPUEVENT - description: HW configuration CPU event generation - bit_offset: 0 - bit_size: 32 -fieldset/HWCFGR7: - description: EXTI Hardware configuration registers - fields: - - name: CPUEVENT - description: HW configuration CPU event generation - bit_offset: 0 - bit_size: 32 -fieldset/IPIDR: - description: Identification register - fields: - - name: IPID - description: IP Identification - bit_offset: 0 - bit_size: 32 -fieldset/PR1: +fieldset/PR: description: EXTI pending register fields: - name: PIF @@ -303,98 +94,31 @@ fieldset/PR1: bit_offset: 0 bit_size: 1 array: - len: 22 + len: 32 stride: 1 enum_read: PRR enum_write: PRW - - name: PIF_31 - description: Configurable event inputs Pending bit - bit_offset: 31 - bit_size: 1 - enum_read: PRR - enum_write: PRW -fieldset/PR2: - description: pending register - fields: - - name: PIF - description: Configurable event inputs x+32 Pending bit. - bit_offset: 1 - bit_size: 1 - enum_read: PRR - enum_write: PRW - - name: PIF40_41 - description: Configurable event inputs x+32 Pending bit. - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - enum_read: PRR - enum_write: PRW -fieldset/RTSR1: +fieldset/RTSR: description: rising trigger selection register fields: - name: RT description: Rising trigger event configuration bit of Configurable Event input bit_offset: 0 - bit_size: 22 - array: - len: 22 - stride: 1 - enum: RT - - name: RT_31 - description: Rising trigger event configuration bit of Configurable Event input - bit_offset: 31 - bit_size: 1 - enum: RT -fieldset/RTSR2: - description: rising trigger selection register - fields: - - name: RT - description: Rising trigger event configuration bit of Configurable Event input - bit_offset: 1 - bit_size: 1 - enum: RT - - name: RT40_41 - description: Rising trigger event configuration bit of Configurable Event input - bit_offset: 8 bit_size: 1 array: - len: 2 + len: 32 stride: 1 enum: RT -fieldset/SIDR: - description: Size ID register - fields: - - name: SID - description: Size Identification - bit_offset: 0 - bit_size: 32 -fieldset/SWIER1: +fieldset/SWIER: description: software interrupt event register fields: - name: SWI description: Software interrupt on event bit_offset: 0 - bit_size: 22 - - name: SWI_31 - description: Software interrupt on event - bit_offset: 31 - bit_size: 1 -fieldset/SWIER2: - description: software interrupt event register - fields: - - name: SWI - description: Software interrupt on event - bit_offset: 1 bit_size: 1 array: - len: 1 - stride: 0 - - name: SWI40_41 - description: Software interrupt on event - bit_offset: 8 - bit_size: 2 + len: 32 + stride: 1 fieldset/VERR: description: EXTI IP Version register fields: diff --git a/data/registers/ipcc_v1.yaml b/data/registers/ipcc_v1.yaml index 9b42679..7b38019 100644 --- a/data/registers/ipcc_v1.yaml +++ b/data/registers/ipcc_v1.yaml @@ -2,62 +2,34 @@ block/IPCC: description: IPCC items: - - name: C1CR - description: Control register CPU1 + - name: CPU + description: CPU specific registers + byte_offset: 0 + array: + len: 2 + stride: 16 + +block/IPCC_CPU: + description: IPCC + items: + - name: CR + description: Control register CPUx byte_offset: 0 fieldset: C1CR - - name: C1MR - description: Mask register CPU1 + - name: MR + description: Mask register CPUx byte_offset: 4 fieldset: C1MR - - name: C1SCR + - name: SCR description: Status Set or Clear register CPU1 byte_offset: 8 access: Write fieldset: C1SCR - - name: C1TO2SR + - name: SR description: CPU1 to CPU2 status register byte_offset: 12 access: Read fieldset: C1TO2SR - - name: C2CR - description: Control register CPU2 - byte_offset: 16 - fieldset: C2CR - - name: C2MR - description: Mask register CPU2 - byte_offset: 20 - fieldset: C2MR - - name: C2SCR - description: Status Set or Clear register CPU2 - byte_offset: 24 - access: Write - fieldset: C2SCR - - name: C2TOC1SR - description: CPU2 to CPU1 status register - byte_offset: 28 - access: Read - fieldset: C2TOC1SR - - name: HWCFGR - description: IPCC Hardware configuration register - byte_offset: 1008 - access: Read - fieldset: HWCFGR - - name: VERR - description: IPCC version register - byte_offset: 1012 - access: Read - fieldset: VERR - - name: IPIDR - description: IPCC indentification register - byte_offset: 1016 - access: Read - fieldset: IPIDR - - name: SIDR - description: IPCC size indentification register - byte_offset: 1020 - access: Read - fieldset: SIDR fieldset/C1CR: description: Control register CPU1 fields: @@ -168,35 +140,3 @@ fieldset/C2TOC1SR: array: len: 6 stride: 1 -fieldset/HWCFGR: - description: IPCC Hardware configuration register - fields: - - name: CHANNELS - description: "Number of channels per CPU supported by the IP, range 1 to 16" - bit_offset: 0 - bit_size: 8 -fieldset/IPIDR: - description: IPCC indentification register - fields: - - name: IPID - description: Identification Code - bit_offset: 0 - bit_size: 32 -fieldset/SIDR: - description: IPCC size indentification register - fields: - - name: SID - description: Size Identification Code - bit_offset: 0 - bit_size: 32 -fieldset/VERR: - description: IPCC version register - fields: - - name: MINREV - description: Minor Revision - bit_offset: 0 - bit_size: 4 - - name: MAJREV - description: Major Revision - bit_offset: 4 - bit_size: 4