diff --git a/data/registers/exti_wb55.yaml b/data/registers/exti_wb55.yaml new file mode 100644 index 0000000..516901f --- /dev/null +++ b/data/registers/exti_wb55.yaml @@ -0,0 +1,174 @@ +--- +block/EXTI: + description: External interrupt/event controller + items: + - name: RTSR + description: rising trigger selection register + byte_offset: 0 + fieldset: RTSR + array: + len: 2 + stride: 32 + - name: FTSR + description: falling trigger selection register + byte_offset: 4 + fieldset: FTSR + array: + len: 2 + stride: 32 + - name: SWIER + description: software interrupt event register + byte_offset: 8 + fieldset: SWIER + array: + len: 2 + stride: 32 + - name: PR + description: EXTI pending register + byte_offset: 12 + fieldset: PR + array: + len: 2 + stride: 32 + - name: CPU + description: CPU specific registers + byte_offset: 128 + block: CPU_MASK + array: + len: 2 + stride: 64 +block/CPU_MASK: + description: CPU-specific mask registers + items: + - name: IMR + description: CPUm wakeup with interrupt mask register + byte_offset: 0 + fieldset: C1IMR + array: + len: 2 + stride: 16 + - name: EMR + description: CPUm wakeup with event mask register + byte_offset: 4 + fieldset: C1EMR + array: + len: 2 + stride: 16 +fieldset/C1EMR: + description: CPUm wakeup with event mask register + fields: + - name: EM + description: CPU(m) Wakeup with event generation Mask on Event input + bit_offset: 0 + bit_size: 16 + array: + len: 32 + stride: 1 +fieldset/C1IMR: + description: CPUm wakeup with interrupt mask register + fields: + - name: IM + description: CPU(m) wakeup with interrupt Mask on Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: MR +fieldset/FTSR: + description: falling trigger selection register + fields: + - name: FT + description: Falling trigger event configuration bit of Configurable Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: FT +fieldset/PR: + description: EXTI pending register + fields: + - name: PIF + description: Configurable event inputs Pending bit + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum_read: PRR + enum_write: PRW +fieldset/RTSR: + description: rising trigger selection register + fields: + - name: RT + description: Rising trigger event configuration bit of Configurable Event input + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: RT +fieldset/SWIER: + description: software interrupt event register + fields: + - name: SWI + description: Software interrupt on event + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/VERR: + description: EXTI IP Version register + fields: + - name: MINREV + description: Minor Revision number + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major Revision number + bit_offset: 4 + bit_size: 4 +enum/FT: + bit_size: 1 + variants: + - name: Disabled + description: Falling edge trigger is disabled + value: 0 + - name: Enabled + description: Falling edge trigger is enabled + value: 1 +enum/RT: + bit_size: 1 + variants: + - name: Disabled + description: Falling edge trigger is disabled + value: 0 + - name: Enabled + description: Falling edge trigger is enabled + value: 1 +enum/MR: + bit_size: 1 + variants: + - name: Masked + description: Interrupt request line is masked + value: 0 + - name: Unmasked + description: Interrupt request line is unmasked + value: 1 +enum/PRR: + bit_size: 1 + variants: + - name: NotPending + description: No trigger request occurred + value: 0 + - name: Pending + description: Selected trigger request occurred + value: 1 +enum/PRW: + bit_size: 1 + variants: + - name: Clear + description: Clears pending bit + value: 1 diff --git a/data/registers/ipcc_v1.yaml b/data/registers/ipcc_v1.yaml new file mode 100644 index 0000000..7b38019 --- /dev/null +++ b/data/registers/ipcc_v1.yaml @@ -0,0 +1,142 @@ +--- +block/IPCC: + description: IPCC + items: + - name: CPU + description: CPU specific registers + byte_offset: 0 + array: + len: 2 + stride: 16 + +block/IPCC_CPU: + description: IPCC + items: + - name: CR + description: Control register CPUx + byte_offset: 0 + fieldset: C1CR + - name: MR + description: Mask register CPUx + byte_offset: 4 + fieldset: C1MR + - name: SCR + description: Status Set or Clear register CPU1 + byte_offset: 8 + access: Write + fieldset: C1SCR + - name: SR + description: CPU1 to CPU2 status register + byte_offset: 12 + access: Read + fieldset: C1TO2SR +fieldset/C1CR: + description: Control register CPU1 + fields: + - name: RXOIE + description: processor 1 Receive channel occupied interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXFIE + description: processor 1 Transmit channel free interrupt enable + bit_offset: 16 + bit_size: 1 +fieldset/C1MR: + description: Mask register CPU1 + fields: + - name: CHOM + description: processor 1 Receive channel x occupied interrupt enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHFM + description: processor 1 Transmit channel x free interrupt mask + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C1SCR: + description: Status Set or Clear register CPU1 + fields: + - name: CHC + description: processor 1 Receive channel x status clear + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHS + description: processor 1 Transmit channel x status set + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C1TO2SR: + description: CPU1 to CPU2 status register + fields: + - name: CHF + description: processor 1 transmit to process 2 Receive channel x status flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C2CR: + description: Control register CPU2 + fields: + - name: RXOIE + description: processor 2 Receive channel occupied interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXFIE + description: processor 2 Transmit channel free interrupt enable + bit_offset: 16 + bit_size: 1 +fieldset/C2MR: + description: Mask register CPU2 + fields: + - name: CHOM + description: processor 2 Receive channel x occupied interrupt enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHFM + description: processor 2 Transmit channel 1 free interrupt mask + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C2SCR: + description: Status Set or Clear register CPU2 + fields: + - name: CHC + description: processor 2 Receive channel x status clear + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHS + description: processor 2 Transmit channel 1 status set + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 +fieldset/C2TOC1SR: + description: CPU2 to CPU1 status register + fields: + - name: CHF + description: processor 2 transmit to process 1 Receive channel x status flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 diff --git a/parse.py b/parse.py index 72809e3..3e0d585 100644 --- a/parse.py +++ b/parse.py @@ -1,5 +1,10 @@ import xmltodict import yaml +try: + from yaml import CSafeLoader as SafeLoader +except ImportError: + from yaml import SafeLoader + import re import json import os @@ -66,7 +71,7 @@ def children(x, key): headers_parsed = {} header_map = {} with open('header_map.yaml', 'r') as f: - y = yaml.load(f, Loader=yaml.SafeLoader) + y = yaml.load(f, Loader=SafeLoader) for header, chips in y.items(): for chip in chips.split(','): header_map[chip.strip().lower()] = header.lower() @@ -339,6 +344,8 @@ perimap = [ ('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'), ('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'), ('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'), + + ('.*:IPCC:v1_0', 'ipcc_v1/IPCC'), ] rng_clock_map = [ @@ -556,6 +563,7 @@ def parse_chips(): #print("Defining for core", core_name) # Gather all interrupts and defines for this core + interrupts = h['interrupts'][core_name] defines = h['defines'][core_name] @@ -605,7 +613,7 @@ def parse_chips(): family_extra = "data/extra/family/" + chip['family'] + ".yaml" if os.path.exists(family_extra): with open(family_extra) as extra_f: - extra = yaml.load(extra_f, Loader=yaml.SafeLoader) + extra = yaml.load(extra_f, Loader=SafeLoader) for (extra_name, extra_p) in extra['peripherals'].items(): peris[extra_name] = extra_p @@ -637,10 +645,15 @@ def parse_chips(): # EXTI is not in the cubedb XMLs if addr := defines.get('EXTI_BASE'): + if chip_name.startswith("STM32WB55"): + block = 'exti_wb55/EXTI' + else: + block = 'exti_v1/EXTI' + peris['EXTI'] = OrderedDict({ 'address': addr, 'kind': 'EXTI', - 'block': 'exti_v1/EXTI', + 'block': block, }) # FLASH is not in the cubedb XMLs @@ -675,6 +688,7 @@ def parse_chips(): if block := match_peri(kind): crs_peri['block'] = block peris['CRS'] = crs_peri + core['peripherals'] = peris # remove all pins from the root of the chip before emitting.