From 2b56ec9e99f78e79ab745c19c91842d84c135ffa Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Mon, 29 Nov 2021 10:16:37 +0100 Subject: [PATCH] Add correct H7 timer register blocks. --- stm32data/__main__.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index bd368be..977377f 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -207,6 +207,13 @@ perimap = [ ('.*LPTIM\d.*:G0xx_lptimer1_v1_4', 'lptim_g0/LPTIM'), + ('STM32H7.*:TIM1:.*', 'timer_v1/TIM_ADV'), + ('STM32H7.*:TIM2:.*', 'timer_v1/TIM_GP32'), + ('STM32H7.*:TIM5:.*', 'timer_v1/TIM_GP32'), + ('STM32H7.*:TIM6:.*', 'timer_v1/TIM_BASIC'), + ('STM32H7.*:TIM7:.*', 'timer_v1/TIM_BASIC'), + ('STM32H7.*:TIM8:.*', 'timer_v1/TIM_ADV'), + ('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), ('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'), ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),