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Remove enums from enable registers

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Add transform for RCC
This commit is contained in:
Ulf Lilleengen 2021-06-02 16:32:43 +02:00
parent c433eb4d47
commit 9ad584c149
2 changed files with 45 additions and 265 deletions
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265
data/registers/rcc_l0.yaml
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@ -96,32 +96,26 @@ fieldset/AHBENR:
description: DMA clock enable bit
bit_offset: 0
bit_size: 1
enum: CRYPEN
- name: MIFEN
description: NVM interface clock enable bit
bit_offset: 8
bit_size: 1
enum: CRYPEN
- name: CRCEN
description: CRC clock enable bit
bit_offset: 12
bit_size: 1
enum: CRYPEN
- name: TOUCHEN
description: Touch Sensing clock enable bit
bit_offset: 16
bit_size: 1
enum: CRYPEN
- name: RNGEN
description: Random Number Generator clock enable bit
bit_offset: 20
bit_size: 1
enum: CRYPEN
- name: CRYPEN
description: Crypto clock enable bit
bit_offset: 24
bit_size: 1
enum: CRYPEN
fieldset/AHBRSTR:
description: AHB peripheral reset register
fields:
@ -162,22 +156,18 @@ fieldset/AHBSMENR:
description: DMA clock enable during sleep mode bit
bit_offset: 0
bit_size: 1
enum: DMASMEN
- name: MIFSMEN
description: NVM interface clock enable during sleep mode bit
bit_offset: 8
bit_size: 1
enum: MIFSMEN
- name: SRAMSMEN
description: SRAM interface clock enable during sleep mode bit
bit_offset: 9
bit_size: 1
enum: SRAMSMEN
- name: CRCSMEN
description: CRC clock enable during sleep mode bit
bit_offset: 12
bit_size: 1
enum: CRCSMEN
- name: TOUCHSMEN
description: Touch Sensing clock enable during sleep mode bit
bit_offset: 16
@ -190,7 +180,6 @@ fieldset/AHBSMENR:
description: Crypto clock enable during sleep mode bit
bit_offset: 24
bit_size: 1
enum: CRYPSMEN
fieldset/APB1ENR:
description: APB1 peripheral clock enable register
fields:
@ -198,92 +187,74 @@ fieldset/APB1ENR:
description: Timer2 clock enable bit
bit_offset: 0
bit_size: 1
enum: LPTIMEN
- name: TIM3EN
description: Timer3 clock enable bit
bit_offset: 1
bit_size: 1
enum: LPTIMEN
- name: TIM6EN
description: Timer 6 clock enable bit
bit_offset: 4
bit_size: 1
enum: LPTIMEN
- name: TIM7EN
description: Timer 7 clock enable bit
bit_offset: 5
bit_size: 1
enum: LPTIMEN
- name: WWDGEN
description: Window watchdog clock enable bit
bit_offset: 11
bit_size: 1
enum: LPTIMEN
- name: SPI2EN
description: SPI2 clock enable bit
bit_offset: 14
bit_size: 1
enum: LPTIMEN
- name: USART2EN
description: UART2 clock enable bit
bit_offset: 17
bit_size: 1
enum: LPTIMEN
- name: LPUART1EN
description: LPUART1 clock enable bit
bit_offset: 18
bit_size: 1
enum: LPTIMEN
- name: USART4EN
description: USART4 clock enable bit
bit_offset: 19
bit_size: 1
enum: LPTIMEN
- name: USART5EN
description: USART5 clock enable bit
bit_offset: 20
bit_size: 1
enum: LPTIMEN
- name: I2C1EN
description: I2C1 clock enable bit
bit_offset: 21
bit_size: 1
enum: LPTIMEN
- name: I2C2EN
description: I2C2 clock enable bit
bit_offset: 22
bit_size: 1
enum: LPTIMEN
- name: USBEN
description: USB clock enable bit
bit_offset: 23
bit_size: 1
enum: LPTIMEN
- name: CRSEN
description: Clock recovery system clock enable bit
bit_offset: 27
bit_size: 1
enum: LPTIMEN
- name: PWREN
description: Power interface clock enable bit
bit_offset: 28
bit_size: 1
enum: LPTIMEN
- name: DACEN
description: DAC interface clock enable bit
bit_offset: 29
bit_size: 1
enum: LPTIMEN
- name: I2C3EN
description: I2C3 clock enable bit
bit_offset: 30
bit_size: 1
enum: LPTIMEN
- name: LPTIM1EN
description: Low power timer clock enable bit
bit_offset: 31
bit_size: 1
enum: LPTIMEN
fieldset/APB1RSTR:
description: APB1 peripheral reset register
fields:
@ -384,92 +355,74 @@ fieldset/APB1SMENR:
description: Timer2 clock enable during sleep mode bit
bit_offset: 0
bit_size: 1
enum: LPTIMSMEN
- name: TIM3SMEN
description: Timer3 clock enable during Sleep mode bit
bit_offset: 1
bit_size: 1
enum: LPTIMSMEN
- name: TIM6SMEN
description: Timer 6 clock enable during sleep mode bit
bit_offset: 4
bit_size: 1
enum: LPTIMSMEN
- name: TIM7SMEN
description: Timer 7 clock enable during Sleep mode bit
bit_offset: 5
bit_size: 1
enum: LPTIMSMEN
- name: WWDGSMEN
description: Window watchdog clock enable during sleep mode bit
bit_offset: 11
bit_size: 1
enum: LPTIMSMEN
- name: SPI2SMEN
description: SPI2 clock enable during sleep mode bit
bit_offset: 14
bit_size: 1
enum: LPTIMSMEN
- name: USART2SMEN
description: UART2 clock enable during sleep mode bit
bit_offset: 17
bit_size: 1
enum: LPTIMSMEN
- name: LPUART1SMEN
description: LPUART1 clock enable during sleep mode bit
bit_offset: 18
bit_size: 1
enum: LPTIMSMEN
- name: USART4SMEN
description: USART4 clock enable during Sleep mode bit
bit_offset: 19
bit_size: 1
enum: LPTIMSMEN
- name: USART5SMEN
description: USART5 clock enable during Sleep mode bit
bit_offset: 20
bit_size: 1
enum: LPTIMSMEN
- name: I2C1SMEN
description: I2C1 clock enable during sleep mode bit
bit_offset: 21
bit_size: 1
enum: LPTIMSMEN
- name: I2C2SMEN
description: I2C2 clock enable during sleep mode bit
bit_offset: 22
bit_size: 1
enum: LPTIMSMEN
- name: USBSMEN
description: USB clock enable during sleep mode bit
bit_offset: 23
bit_size: 1
enum: LPTIMSMEN
- name: CRSSMEN
description: Clock recovery system clock enable during sleep mode bit
bit_offset: 27
bit_size: 1
enum: LPTIMSMEN
- name: PWRSMEN
description: Power interface clock enable during sleep mode bit
bit_offset: 28
bit_size: 1
enum: LPTIMSMEN
- name: DACSMEN
description: DAC interface clock enable during sleep mode bit
bit_offset: 29
bit_size: 1
enum: LPTIMSMEN
- name: I2C3SMEN
description: 2C3 clock enable during Sleep mode bit
bit_offset: 30
bit_size: 1
enum: LPTIMSMEN
- name: LPTIM1SMEN
description: Low power timer clock enable during sleep mode bit
bit_offset: 31
bit_size: 1
enum: LPTIMSMEN
fieldset/APB2ENR:
description: APB2 peripheral clock enable register
fields:
@ -477,42 +430,34 @@ fieldset/APB2ENR:
description: System configuration controller clock enable bit
bit_offset: 0
bit_size: 1
enum: DBGEN
- name: TIM21EN
description: TIM21 timer clock enable bit
bit_offset: 2
bit_size: 1
enum: DBGEN
- name: TIM22EN
description: TIM22 timer clock enable bit
bit_offset: 5
bit_size: 1
enum: DBGEN
- name: MIFIEN
description: MiFaRe Firewall clock enable bit
bit_offset: 7
bit_size: 1
enum: DBGEN
- name: ADCEN
description: ADC clock enable bit
bit_offset: 9
bit_size: 1
enum: DBGEN
- name: SPI1EN
description: SPI1 clock enable bit
bit_offset: 12
bit_size: 1
enum: DBGEN
- name: USART1EN
description: USART1 clock enable bit
bit_offset: 14
bit_size: 1
enum: DBGEN
- name: DBGEN
description: DBG clock enable bit
bit_offset: 22
bit_size: 1
enum: DBGEN
fieldset/APB2RSTR:
description: APB2 peripheral reset register
fields:
@ -558,37 +503,30 @@ fieldset/APB2SMENR:
description: System configuration controller clock enable during sleep mode bit
bit_offset: 0
bit_size: 1
enum: DBGSMEN
- name: TIM21SMEN
description: TIM21 timer clock enable during sleep mode bit
bit_offset: 2
bit_size: 1
enum: DBGSMEN
- name: TIM22SMEN
description: TIM22 timer clock enable during sleep mode bit
bit_offset: 5
bit_size: 1
enum: DBGSMEN
- name: ADCSMEN
description: ADC clock enable during sleep mode bit
bit_offset: 9
bit_size: 1
enum: DBGSMEN
- name: SPI1SMEN
description: SPI1 clock enable during sleep mode bit
bit_offset: 12
bit_size: 1
enum: DBGSMEN
- name: USART1SMEN
description: USART1 clock enable during sleep mode bit
bit_offset: 14
bit_size: 1
enum: DBGSMEN
- name: DBGSMEN
description: DBG clock enable during sleep mode bit
bit_offset: 22
bit_size: 1
enum: DBGSMEN
fieldset/CCIPR:
description: Clock configuration register
fields:
@ -737,42 +675,34 @@ fieldset/CIER:
description: LSI ready interrupt flag
bit_offset: 0
bit_size: 1
enum: HSIRDYIE
- name: LSERDYIE
description: LSE ready interrupt flag
bit_offset: 1
bit_size: 1
enum: HSIRDYIE
- name: HSI16RDYIE
description: HSI16 ready interrupt flag
bit_offset: 2
bit_size: 1
enum: HSIRDYIE
- name: HSERDYIE
description: HSE ready interrupt flag
bit_offset: 3
bit_size: 1
enum: HSIRDYIE
- name: PLLRDYIE
description: PLL ready interrupt flag
bit_offset: 4
bit_size: 1
enum: HSIRDYIE
- name: MSIRDYIE
description: MSI ready interrupt flag
bit_offset: 5
bit_size: 1
enum: HSIRDYIE
- name: HSI48RDYIE
description: HSI48 ready interrupt flag
bit_offset: 6
bit_size: 1
enum: HSIRDYIE
- name: CSSLSE
description: LSE CSS interrupt flag
bit_offset: 7
bit_size: 1
enum: CSSLSE
fieldset/CIFR:
description: Clock interrupt flag register
fields:
@ -828,12 +758,10 @@ fieldset/CR:
description: 16 MHz high-speed internal clock enable
bit_offset: 0
bit_size: 1
enum: PLLON
- name: HSI16KERON
description: High-speed internal clock enable bit for some IP kernels
bit_offset: 1
bit_size: 1
enum: PLLON
- name: HSI16RDYF
description: Internal high-speed clock ready flag
bit_offset: 2
@ -843,7 +771,6 @@ fieldset/CR:
description: HSI16DIVEN
bit_offset: 3
bit_size: 1
enum: HSIDIVEN
- name: HSI16DIVF
description: HSI16DIVF
bit_offset: 4
@ -853,12 +780,10 @@ fieldset/CR:
description: 16 MHz high-speed internal clock output enable
bit_offset: 5
bit_size: 1
enum: HSIOUTEN
- name: MSION
description: MSI clock enable bit
bit_offset: 8
bit_size: 1
enum: PLLON
- name: MSIRDY
description: MSI clock ready flag
bit_offset: 9
@ -868,7 +793,6 @@ fieldset/CR:
description: HSE clock enable bit
bit_offset: 16
bit_size: 1
enum: PLLON
- name: HSERDY
description: HSE clock ready flag
bit_offset: 17
@ -883,7 +807,6 @@ fieldset/CR:
description: Clock security system on HSE enable bit
bit_offset: 19
bit_size: 1
enum: PLLON
- name: RTCPRE
description: TC/LCD prescaler
bit_offset: 20
@ -893,7 +816,6 @@ fieldset/CR:
description: PLL enable bit
bit_offset: 24
bit_size: 1
enum: PLLON
- name: PLLRDY
description: PLL clock ready flag
bit_offset: 25
@ -925,7 +847,6 @@ fieldset/CSR:
description: Internal low-speed oscillator enable
bit_offset: 0
bit_size: 1
enum: CSSLSEON
- name: LSIRDY
description: Internal low-speed oscillator ready bit
bit_offset: 1
@ -935,7 +856,6 @@ fieldset/CSR:
description: External low-speed oscillator enable bit
bit_offset: 8
bit_size: 1
enum: CSSLSEON
- name: LSERDY
description: External low-speed oscillator ready bit
bit_offset: 9
@ -955,7 +875,6 @@ fieldset/CSR:
description: CSSLSEON
bit_offset: 13
bit_size: 1
enum: CSSLSEON
- name: CSSLSED
description: CSS on LSE failure detection flag
bit_offset: 14
@ -970,7 +889,6 @@ fieldset/CSR:
description: RTC clock enable bit
bit_offset: 18
bit_size: 1
enum: RTCEN
- name: RTCRST
description: RTC software reset bit
bit_offset: 19
@ -1047,32 +965,26 @@ fieldset/IOPENR:
description: IO port A clock enable bit
bit_offset: 0
bit_size: 1
enum: IOPHEN
- name: IOPBEN
description: IO port B clock enable bit
bit_offset: 1
bit_size: 1
enum: IOPHEN
- name: IOPCEN
description: IO port A clock enable bit
bit_offset: 2
bit_size: 1
enum: IOPHEN
- name: IOPDEN
description: I/O port D clock enable bit
bit_offset: 3
bit_size: 1
enum: IOPHEN
- name: IOPEEN
description: I/O port E clock enable bit
bit_offset: 4
bit_size: 1
enum: IOPHEN
- name: IOPHEN
description: I/O port H clock enable bit
bit_offset: 7
bit_size: 1
enum: IOPHEN
fieldset/IOPRSTR:
description: GPIO reset register
fields:
@ -1113,65 +1025,32 @@ fieldset/IOPSMEN:
description: IOPASMEN
bit_offset: 0
bit_size: 1
enum: IOPHSMEN
- name: IOPBSMEN
description: IOPBSMEN
bit_offset: 1
bit_size: 1
enum: IOPHSMEN
- name: IOPCSMEN
description: IOPCSMEN
bit_offset: 2
bit_size: 1
enum: IOPHSMEN
- name: IOPDSMEN
description: IOPDSMEN
bit_offset: 3
bit_size: 1
enum: IOPHSMEN
- name: IOPESMEN
description: Port E clock enable during Sleep mode bit
bit_offset: 4
bit_size: 1
enum: IOPHSMEN
- name: IOPHSMEN
description: IOPHSMEN
bit_offset: 7
bit_size: 1
enum: IOPHSMEN
enum/CRCSMEN:
bit_size: 1
variants:
- name: Disabled
description: Test integration module clock disabled in Sleep mode
value: 0
- name: Enabled
description: Test integration module clock enabled in Sleep mode (if enabled by CRCEN)
value: 1
enum/CRYPEN:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/CRYPRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/CRYPSMEN:
bit_size: 1
variants:
- name: Disabled
description: Crypto clock disabled in Sleep mode
value: 0
- name: Enabled
description: Crypto clock enabled in Sleep mode
value: 1
enum/CSSHSECW:
bit_size: 1
variants:
@ -1187,15 +1066,6 @@ enum/CSSHSEF:
- name: Clock
description: Clock security interrupt caused by HSE clock failure
value: 1
enum/CSSLSE:
bit_size: 1
variants:
- name: Disabled
description: LSE CSS interrupt disabled
value: 0
- name: Enabled
description: LSE CSS interrupt enabled
value: 1
enum/CSSLSED:
bit_size: 1
variants:
@ -1214,48 +1084,12 @@ enum/CSSLSEF:
- name: Failure
description: Failure detected on LSE clock failure
value: 1
enum/CSSLSEON:
bit_size: 1
variants:
- name: "Off"
description: Oscillator OFF
value: 0
- name: "On"
description: Oscillator ON
value: 1
enum/DBGEN:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/DBGRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/DBGSMEN:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/DMASMEN:
bit_size: 1
variants:
- name: Disabled
description: DMA clock disabled in Sleep mode
value: 0
- name: Enabled
description: DMA clock enabled in Sleep mode
value: 1
enum/HPRE:
bit_size: 4
variants:
@ -1322,15 +1156,6 @@ enum/HSI48RDYFR:
- name: Interrupted
description: Clock ready interrupt
value: 1
enum/HSIDIVEN:
bit_size: 1
variants:
- name: NotDivided
description: no 16 MHz HSI division requested
value: 0
- name: Div4
description: 16 MHz HSI division by 4 requested
value: 1
enum/HSIDIVFR:
bit_size: 1
variants:
@ -1340,24 +1165,6 @@ enum/HSIDIVFR:
- name: Div4
description: 16 MHz HSI clock divided by 4
value: 1
enum/HSIOUTEN:
bit_size: 1
variants:
- name: Disabled
description: HSI output clock disabled
value: 0
- name: Enabled
description: HSI output clock enabled
value: 1
enum/HSIRDYIE:
bit_size: 1
variants:
- name: Disabled
description: Ready interrupt disabled
value: 0
- name: Enabled
description: Ready interrupt enabled
value: 1
enum/ICSEL:
bit_size: 2
variants:
@ -1370,39 +1177,12 @@ enum/ICSEL:
- name: HSI16
description: HSI16 clock selected as peripheral clock
value: 2
enum/IOPHEN:
bit_size: 1
variants:
- name: Disabled
description: Port clock disabled
value: 0
- name: Enabled
description: Port clock enabled
value: 1
enum/IOPHRST:
bit_size: 1
variants:
- name: Reset
description: Reset I/O port
value: 1
enum/IOPHSMEN:
bit_size: 1
variants:
- name: Disabled
description: Port x clock is disabled in Sleep mode
value: 0
- name: Enabled
description: Port x clock is enabled in Sleep mode (if enabled by IOPHEN)
value: 1
enum/LPTIMEN:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/LPTIMRSTW:
bit_size: 1
variants:
@ -1424,15 +1204,6 @@ enum/LPTIMSEL:
- name: LSE
description: LSE clock selected as Timer clock
value: 3
enum/LPTIMSMEN:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/LPUARTSEL:
bit_size: 2
variants:
@ -1535,15 +1306,6 @@ enum/MCOSEL:
- name: LSE
description: LSE oscillator clock selected
value: 7
enum/MIFSMEN:
bit_size: 1
variants:
- name: Disabled
description: NVM interface clock disabled in Sleep mode
value: 0
- name: Enabled
description: NVM interface clock enabled in Sleep mode
value: 1
enum/MSIRANGE:
bit_size: 3
variants:
@ -1613,15 +1375,6 @@ enum/PLLMUL:
- name: Mul48
description: PLL clock entry x 48
value: 8
enum/PLLON:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/PLLRDYR:
bit_size: 1
variants:
@ -1664,15 +1417,6 @@ enum/RMVFW:
- name: Clear
description: Clears the reset flag
value: 1
enum/RTCEN:
bit_size: 1
variants:
- name: Disabled
description: RTC clock disabled
value: 0
- name: Enabled
description: RTC clock enabled
value: 1
enum/RTCPRE:
bit_size: 2
variants:
@ -1709,15 +1453,6 @@ enum/RTCSEL:
- name: HSE
description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock"
value: 3
enum/SRAMSMEN:
bit_size: 1
variants:
- name: Disabled
description: NVM interface clock disabled in Sleep mode
value: 0
- name: Enabled
description: NVM interface clock enabled in Sleep mode
value: 1
enum/STOPWUCK:
bit_size: 1
variants:

45
transform-RCC.yaml Normal file
View File

@ -0,0 +1,45 @@
transforms:
- MergeEnums:
from: CCMR\d_Input_CC\dS
to: CCMR_Input_CCS
check: Layout
# Remove digits from enum names
- MergeEnums:
from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]*
to: $1$2$3
skip_unmergeable: true
- MakeFieldArray:
fieldsets: .*
from: ([A-Z]+)\d+
to: $1
allow_cursed: true
- MakeFieldArray:
fieldsets: .*
from: P\d+WP
to: PWP
# - MakeRegisterArray:
# blocks: .*
# from: ([A-Z]+)\d+
# to: $1
- MakeRegisterArray:
blocks: .*
from: EXTICR\d+
to: EXTICR
- MergeEnums:
from: '[HL](IFCR|ISR)_(.*)'
to: $2
- MergeFieldsets:
from: '[HL](IFCR|ISR)'
to: $1
- MergeFieldsets:
from: EXTICR\d
to: EXTICR
- MakeRegisterArray:
blocks: .*
from: '[HL](IFCR|ISR)'
to: $1
- DeleteEnums:
from: '.*[EN]'
bit_size: 1