diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml
index 3b7a5d2..57fd23e 100644
--- a/data/registers/rcc_f1.yaml
+++ b/data/registers/rcc_f1.yaml
@@ -42,14 +42,6 @@ block/RCC:
       description: Control/status register (RCC_CSR)
       byte_offset: 36
       fieldset: CSR
-    - name: AHBRSTR
-      description: AHB peripheral clock reset register (RCC_AHBRSTR)
-      byte_offset: 40
-      fieldset: AHBRSTR
-    - name: CFGR2
-      description: Clock configuration register 2
-      byte_offset: 44
-      fieldset: CFGR2
 fieldset/AHBENR:
   description: AHB Peripheral Clock enable register (RCC_AHBENR)
   fields:
@@ -81,33 +73,6 @@ fieldset/AHBENR:
       description: SDIO clock enable
       bit_offset: 10
       bit_size: 1
-    - name: USB_OTG_FSEN
-      description: USB OTG FS clock enable
-      bit_offset: 12
-      bit_size: 1
-    - name: ETHEN
-      description: Ethernet MAC clock enable
-      bit_offset: 14
-      bit_size: 1
-    - name: ETHTXEN
-      description: Ethernet MAC TX clock enable
-      bit_offset: 15
-      bit_size: 1
-    - name: ETHRXEN
-      description: Ethernet MAC RX clock enable
-      bit_offset: 16
-      bit_size: 1
-fieldset/AHBRSTR:
-  description: AHB peripheral clock reset register (RCC_AHBRSTR)
-  fields:
-    - name: USB_OTG_FSRST
-      description: USB OTG FS reset
-      bit_offset: 12
-      bit_size: 1
-    - name: ETHRST
-      description: Ethernet MAC reset
-      bit_offset: 14
-      bit_size: 1
 fieldset/APB1ENR:
   description: APB1 peripheral clock enable register (RCC_APB1ENR)
   fields:
@@ -187,18 +152,10 @@ fieldset/APB1ENR:
       description: USB clock enable
       bit_offset: 23
       bit_size: 1
-    - name: CAN1EN
-      description: CAN1 clock enable
-      bit_offset: 25
-      bit_size: 1
     - name: CANEN
       description: CAN clock enable
       bit_offset: 25
       bit_size: 1
-    - name: CAN2EN
-      description: CAN2 clock enable
-      bit_offset: 26
-      bit_size: 1
     - name: BKPEN
       description: Backup interface clock enable
       bit_offset: 27
@@ -211,10 +168,6 @@ fieldset/APB1ENR:
       description: DAC interface clock enable
       bit_offset: 29
       bit_size: 1
-    - name: CECEN
-      description: CEC clock enable
-      bit_offset: 30
-      bit_size: 1
 fieldset/APB1RSTR:
   description: APB1 peripheral reset register (RCC_APB1RSTR)
   fields:
@@ -294,18 +247,10 @@ fieldset/APB1RSTR:
       description: USB reset
       bit_offset: 23
       bit_size: 1
-    - name: CAN1RST
-      description: CAN1 reset
-      bit_offset: 25
-      bit_size: 1
     - name: CANRST
       description: CAN reset
       bit_offset: 25
       bit_size: 1
-    - name: CAN2RST
-      description: CAN2 reset
-      bit_offset: 26
-      bit_size: 1
     - name: BKPRST
       description: Backup interface reset
       bit_offset: 27
@@ -318,10 +263,6 @@ fieldset/APB1RSTR:
       description: DAC interface reset
       bit_offset: 29
       bit_size: 1
-    - name: CECRST
-      description: CEC reset
-      bit_offset: 30
-      bit_size: 1
 fieldset/APB2ENR:
   description: APB2 peripheral clock enable register (RCC_APB2ENR)
   fields:
@@ -385,18 +326,6 @@ fieldset/APB2ENR:
       description: ADC3 interface clock enable
       bit_offset: 15
       bit_size: 1
-    - name: TIM15EN
-      description: TIM15 Timer clock enable
-      bit_offset: 16
-      bit_size: 1
-    - name: TIM16EN
-      description: TIM16 Timer clock enable
-      bit_offset: 17
-      bit_size: 1
-    - name: TIM17EN
-      description: TIM17 Timer clock enable
-      bit_offset: 18
-      bit_size: 1
     - name: TIM9EN
       description: TIM9 Timer clock enable
       bit_offset: 19
@@ -472,18 +401,6 @@ fieldset/APB2RSTR:
       description: ADC 3 interface reset
       bit_offset: 15
       bit_size: 1
-    - name: TIM15RST
-      description: TIM15 timer reset
-      bit_offset: 16
-      bit_size: 1
-    - name: TIM16RST
-      description: TIM16 timer reset
-      bit_offset: 17
-      bit_size: 1
-    - name: TIM17RST
-      description: TIM17 timer reset
-      bit_offset: 18
-      bit_size: 1
     - name: TIM9RST
       description: TIM9 timer reset
       bit_offset: 19
@@ -572,11 +489,6 @@ fieldset/CFGR:
       bit_offset: 18
       bit_size: 4
       enum: PLLMUL
-    - name: OTGFSPRE
-      description: USB OTG FS prescaler
-      bit_offset: 22
-      bit_size: 1
-      enum: OTGFSPRE
     - name: USBPRE
       description: USB prescaler
       bit_offset: 22
@@ -587,44 +499,6 @@ fieldset/CFGR:
       bit_offset: 24
       bit_size: 3
       enum: MCO
-fieldset/CFGR2:
-  description: Clock configuration register2 (RCC_CFGR2)
-  fields:
-    - name: PREDIV1
-      description: PREDIV1 division factor
-      bit_offset: 0
-      bit_size: 4
-      enum: PREDIV1
-    - name: PREDIV2
-      description: PREDIV2 division factor
-      bit_offset: 4
-      bit_size: 4
-      enum: PREDIV1
-    - name: PLL2MUL
-      description: PLL2 Multiplication Factor
-      bit_offset: 8
-      bit_size: 4
-      enum: PLL2MUL
-    - name: PLL3MUL
-      description: PLL3 Multiplication Factor
-      bit_offset: 12
-      bit_size: 4
-      enum: PLL2MUL
-    - name: PREDIV1SRC
-      description: PREDIV1 entry clock source
-      bit_offset: 16
-      bit_size: 1
-      enum: PREDIV1SRC
-    - name: I2S2SRC
-      description: I2S2 clock source
-      bit_offset: 17
-      bit_size: 1
-      enum: I2S2SRC
-    - name: I2S3SRC
-      description: I2S3 clock source
-      bit_offset: 18
-      bit_size: 1
-      enum: I2S2SRC
 fieldset/CIR:
   description: Clock interrupt register (RCC_CIR)
   fields:
@@ -648,14 +522,6 @@ fieldset/CIR:
       description: PLL Ready Interrupt flag
       bit_offset: 4
       bit_size: 1
-    - name: PLL2RDYF
-      description: PLL2 Ready Interrupt flag
-      bit_offset: 5
-      bit_size: 1
-    - name: PLL3RDYF
-      description: PLL3 Ready Interrupt flag
-      bit_offset: 6
-      bit_size: 1
     - name: CSSF
       description: Clock Security System Interrupt flag
       bit_offset: 7
@@ -680,14 +546,6 @@ fieldset/CIR:
       description: PLL Ready Interrupt Enable
       bit_offset: 12
       bit_size: 1
-    - name: PLL2RDYIE
-      description: PLL2 Ready Interrupt Enable
-      bit_offset: 13
-      bit_size: 1
-    - name: PLL3RDYIE
-      description: PLL3 Ready Interrupt Enable
-      bit_offset: 14
-      bit_size: 1
     - name: LSIRDYC
       description: LSI Ready Interrupt Clear
       bit_offset: 16
@@ -708,14 +566,6 @@ fieldset/CIR:
       description: PLL Ready Interrupt Clear
       bit_offset: 20
       bit_size: 1
-    - name: PLL2RDYC
-      description: PLL2 Ready Interrupt Clear
-      bit_offset: 21
-      bit_size: 1
-    - name: PLL3RDYC
-      description: PLL3 Ready Interrupt Clear
-      bit_offset: 22
-      bit_size: 1
     - name: CSSC
       description: Clock security system interrupt clear
       bit_offset: 23
@@ -763,22 +613,6 @@ fieldset/CR:
       description: PLL clock ready flag
       bit_offset: 25
       bit_size: 1
-    - name: PLL2ON
-      description: PLL2 enable
-      bit_offset: 26
-      bit_size: 1
-    - name: PLL2RDY
-      description: PLL2 clock ready flag
-      bit_offset: 27
-      bit_size: 1
-    - name: PLL3ON
-      description: PLL3 enable
-      bit_offset: 28
-      bit_size: 1
-    - name: PLL3RDY
-      description: PLL3 clock ready flag
-      bit_offset: 29
-      bit_size: 1
 fieldset/CSR:
   description: Control/status register (RCC_CSR)
   fields:
@@ -828,10 +662,10 @@ enum/ADCPRE:
       description: PCLK2 divided by 4
       value: 1
     - name: Div6
-      description: PCLK2 divided by 8
+      description: PCLK2 divided by 6
       value: 2
     - name: Div8
-      description: PCLK2 divided by 16
+      description: PCLK2 divided by 8
       value: 3
 enum/HPRE:
   bit_size: 4
@@ -863,15 +697,6 @@ enum/HPRE:
     - name: Div512
       description: SYSCLK divided by 512
       value: 15
-enum/I2S2SRC:
-  bit_size: 1
-  variants:
-    - name: SYSCLK
-      description: System clock (SYSCLK) selected as I2S clock entry
-      value: 0
-    - name: PLL3
-      description: PLL3 VCO clock selected as I2S clock entry
-      value: 1
 enum/MCO:
   bit_size: 3
   variants:
@@ -890,45 +715,6 @@ enum/MCO:
     - name: PLL
       description: PLL clock divided by 2 selected
       value: 7
-enum/OTGFSPRE:
-  bit_size: 1
-  variants:
-    - name: DIV1_5
-      description: PLL clock is divided by 1.5
-      value: 0
-    - name: DIV1
-      description: PLL clock is not divided
-      value: 1
-enum/PLL2MUL:
-  bit_size: 4
-  variants:
-    - name: Mul8
-      description: PLL clock entry x8
-      value: 6
-    - name: Mul9
-      description: PLL clock entry x9
-      value: 7
-    - name: Mul10
-      description: PLL clock entry x10
-      value: 8
-    - name: Mul11
-      description: PLL clock entry x11
-      value: 9
-    - name: Mul12
-      description: PLL clock entry x12
-      value: 10
-    - name: Mul13
-      description: PLL clock entry x13
-      value: 11
-    - name: Mul14
-      description: PLL clock entry x14
-      value: 12
-    - name: Mul16
-      description: PLL clock entry x16
-      value: 14
-    - name: Mul20
-      description: PLL clock entry x20
-      value: 15
 enum/PLLMUL:
   bit_size: 4
   variants:
@@ -1016,66 +802,6 @@ enum/PPRE1:
     - name: Div16
       description: HCLK divided by 16
       value: 7
-enum/PREDIV1:
-  bit_size: 4
-  variants:
-    - name: Div1
-      description: PREDIV input clock not divided
-      value: 0
-    - name: Div2
-      description: PREDIV input clock divided by 2
-      value: 1
-    - name: Div3
-      description: PREDIV input clock divided by 3
-      value: 2
-    - name: Div4
-      description: PREDIV input clock divided by 4
-      value: 3
-    - name: Div5
-      description: PREDIV input clock divided by 5
-      value: 4
-    - name: Div6
-      description: PREDIV input clock divided by 6
-      value: 5
-    - name: Div7
-      description: PREDIV input clock divided by 7
-      value: 6
-    - name: Div8
-      description: PREDIV input clock divided by 8
-      value: 7
-    - name: Div9
-      description: PREDIV input clock divided by 9
-      value: 8
-    - name: Div10
-      description: PREDIV input clock divided by 10
-      value: 9
-    - name: Div11
-      description: PREDIV input clock divided by 11
-      value: 10
-    - name: Div12
-      description: PREDIV input clock divided by 12
-      value: 11
-    - name: Div13
-      description: PREDIV input clock divided by 13
-      value: 12
-    - name: Div14
-      description: PREDIV input clock divided by 14
-      value: 13
-    - name: Div15
-      description: PREDIV input clock divided by 15
-      value: 14
-    - name: Div16
-      description: PREDIV input clock divided by 16
-      value: 15
-enum/PREDIV1SRC:
-  bit_size: 1
-  variants:
-    - name: HSE
-      description: HSE oscillator clock selected as PREDIV1 clock entry
-      value: 0
-    - name: PLL2
-      description: PLL2 selected as PREDIV1 clock entry
-      value: 1
 enum/RTCSEL:
   bit_size: 2
   variants:
diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml
new file mode 100644
index 0000000..6caf3a9
--- /dev/null
+++ b/data/registers/rcc_f100.yaml
@@ -0,0 +1,865 @@
+---
+block/RCC:
+  description: Reset and clock control
+  items:
+    - name: CR
+      description: Clock control register
+      byte_offset: 0
+      fieldset: CR
+    - name: CFGR
+      description: Clock configuration register (RCC_CFGR)
+      byte_offset: 4
+      fieldset: CFGR
+    - name: CIR
+      description: Clock interrupt register (RCC_CIR)
+      byte_offset: 8
+      fieldset: CIR
+    - name: APB2RSTR
+      description: APB2 peripheral reset register (RCC_APB2RSTR)
+      byte_offset: 12
+      fieldset: APB2RSTR
+    - name: APB1RSTR
+      description: APB1 peripheral reset register (RCC_APB1RSTR)
+      byte_offset: 16
+      fieldset: APB1RSTR
+    - name: AHBENR
+      description: AHB Peripheral Clock enable register (RCC_AHBENR)
+      byte_offset: 20
+      fieldset: AHBENR
+    - name: APB2ENR
+      description: APB2 peripheral clock enable register (RCC_APB2ENR)
+      byte_offset: 24
+      fieldset: APB2ENR
+    - name: APB1ENR
+      description: APB1 peripheral clock enable register (RCC_APB1ENR)
+      byte_offset: 28
+      fieldset: APB1ENR
+    - name: BDCR
+      description: Backup domain control register (RCC_BDCR)
+      byte_offset: 32
+      fieldset: BDCR
+    - name: CSR
+      description: Control/status register (RCC_CSR)
+      byte_offset: 36
+      fieldset: CSR
+    - name: CFGR2
+      description: Clock configuration register 2
+      byte_offset: 44
+      fieldset: CFGR2
+fieldset/AHBENR:
+  description: AHB Peripheral Clock enable register (RCC_AHBENR)
+  fields:
+    - name: DMA1EN
+      description: DMA1 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2EN
+      description: DMA2 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: SRAMEN
+      description: SRAM interface clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: FLASHEN
+      description: FLASH clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: CRCEN
+      description: CRC clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: FSMCEN
+      description: FSMC clock enable
+      bit_offset: 8
+      bit_size: 1
+fieldset/APB1ENR:
+  description: APB1 peripheral clock enable register (RCC_APB1ENR)
+  fields:
+    - name: TIM2EN
+      description: Timer 2 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: TIM3EN
+      description: Timer 3 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM4EN
+      description: Timer 4 clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TIM5EN
+      description: Timer 5 clock enable
+      bit_offset: 3
+      bit_size: 1
+    - name: TIM6EN
+      description: Timer 6 clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM7EN
+      description: Timer 7 clock enable
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM12EN
+      description: Timer 12 clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: TIM13EN
+      description: Timer 13 clock enable
+      bit_offset: 7
+      bit_size: 1
+    - name: TIM14EN
+      description: Timer 14 clock enable
+      bit_offset: 8
+      bit_size: 1
+    - name: WWDGEN
+      description: Window watchdog clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2EN
+      description: SPI 2 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: SPI3EN
+      description: SPI 3 clock enable
+      bit_offset: 15
+      bit_size: 1
+    - name: USART2EN
+      description: USART 2 clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: USART3EN
+      description: USART 3 clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: UART4EN
+      description: UART 4 clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: UART5EN
+      description: UART 5 clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C1EN
+      description: I2C 1 clock enable
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C2EN
+      description: I2C 2 clock enable
+      bit_offset: 22
+      bit_size: 1
+    - name: BKPEN
+      description: Backup interface clock enable
+      bit_offset: 27
+      bit_size: 1
+    - name: PWREN
+      description: Power interface clock enable
+      bit_offset: 28
+      bit_size: 1
+    - name: DACEN
+      description: DAC interface clock enable
+      bit_offset: 29
+      bit_size: 1
+    - name: CECEN
+      description: CEC clock enable
+      bit_offset: 30
+      bit_size: 1
+fieldset/APB1RSTR:
+  description: APB1 peripheral reset register (RCC_APB1RSTR)
+  fields:
+    - name: TIM2RST
+      description: Timer 2 reset
+      bit_offset: 0
+      bit_size: 1
+    - name: TIM3RST
+      description: Timer 3 reset
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM4RST
+      description: Timer 4 reset
+      bit_offset: 2
+      bit_size: 1
+    - name: TIM5RST
+      description: Timer 5 reset
+      bit_offset: 3
+      bit_size: 1
+    - name: TIM6RST
+      description: Timer 6 reset
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM7RST
+      description: Timer 7 reset
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM12RST
+      description: Timer 12 reset
+      bit_offset: 6
+      bit_size: 1
+    - name: TIM13RST
+      description: Timer 13 reset
+      bit_offset: 7
+      bit_size: 1
+    - name: TIM14RST
+      description: Timer 14 reset
+      bit_offset: 8
+      bit_size: 1
+    - name: WWDGRST
+      description: Window watchdog reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2RST
+      description: SPI2 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: SPI3RST
+      description: SPI3 reset
+      bit_offset: 15
+      bit_size: 1
+    - name: USART2RST
+      description: USART 2 reset
+      bit_offset: 17
+      bit_size: 1
+    - name: USART3RST
+      description: USART 3 reset
+      bit_offset: 18
+      bit_size: 1
+    - name: UART4RST
+      description: USART 4 reset
+      bit_offset: 19
+      bit_size: 1
+    - name: UART5RST
+      description: USART 5 reset
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C1RST
+      description: I2C1 reset
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C2RST
+      description: I2C2 reset
+      bit_offset: 22
+      bit_size: 1
+    - name: BKPRST
+      description: Backup interface reset
+      bit_offset: 27
+      bit_size: 1
+    - name: PWRRST
+      description: Power interface reset
+      bit_offset: 28
+      bit_size: 1
+    - name: DACRST
+      description: DAC interface reset
+      bit_offset: 29
+      bit_size: 1
+    - name: CECRST
+      description: CEC reset
+      bit_offset: 30
+      bit_size: 1
+fieldset/APB2ENR:
+  description: APB2 peripheral clock enable register (RCC_APB2ENR)
+  fields:
+    - name: AFIOEN
+      description: Alternate function I/O clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOAEN
+      description: I/O port A clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIOBEN
+      description: I/O port B clock enable
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOCEN
+      description: I/O port C clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIODEN
+      description: I/O port D clock enable
+      bit_offset: 5
+      bit_size: 1
+    - name: GPIOEEN
+      description: I/O port E clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: GPIOFEN
+      description: I/O port F clock enable
+      bit_offset: 7
+      bit_size: 1
+    - name: GPIOGEN
+      description: I/O port G clock enable
+      bit_offset: 8
+      bit_size: 1
+    - name: ADC1EN
+      description: ADC 1 interface clock enable
+      bit_offset: 9
+      bit_size: 1
+    - name: TIM1EN
+      description: TIM1 Timer clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1EN
+      description: SPI 1 clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1EN
+      description: USART1 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM15EN
+      description: TIM15 Timer clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TIM16EN
+      description: TIM16 Timer clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17EN
+      description: TIM17 Timer clock enable
+      bit_offset: 18
+      bit_size: 1
+fieldset/APB2RSTR:
+  description: APB2 peripheral reset register (RCC_APB2RSTR)
+  fields:
+    - name: AFIORST
+      description: Alternate function I/O reset
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOARST
+      description: IO port A reset
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIOBRST
+      description: IO port B reset
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOCRST
+      description: IO port C reset
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIODRST
+      description: IO port D reset
+      bit_offset: 5
+      bit_size: 1
+    - name: GPIOERST
+      description: IO port E reset
+      bit_offset: 6
+      bit_size: 1
+    - name: GPIOFRST
+      description: IO port F reset
+      bit_offset: 7
+      bit_size: 1
+    - name: GPIOGRST
+      description: IO port G reset
+      bit_offset: 8
+      bit_size: 1
+    - name: ADC1RST
+      description: ADC 1 interface reset
+      bit_offset: 9
+      bit_size: 1
+    - name: TIM1RST
+      description: TIM1 timer reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1RST
+      description: SPI 1 reset
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1RST
+      description: USART1 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM15RST
+      description: TIM15 timer reset
+      bit_offset: 16
+      bit_size: 1
+    - name: TIM16RST
+      description: TIM16 timer reset
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17RST
+      description: TIM17 timer reset
+      bit_offset: 18
+      bit_size: 1
+fieldset/BDCR:
+  description: Backup domain control register (RCC_BDCR)
+  fields:
+    - name: LSEON
+      description: External Low Speed oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDY
+      description: External Low Speed oscillator ready
+      bit_offset: 1
+      bit_size: 1
+    - name: LSEBYP
+      description: External Low Speed oscillator bypass
+      bit_offset: 2
+      bit_size: 1
+    - name: RTCSEL
+      description: RTC clock source selection
+      bit_offset: 8
+      bit_size: 2
+      enum: RTCSEL
+    - name: RTCEN
+      description: RTC clock enable
+      bit_offset: 15
+      bit_size: 1
+    - name: BDRST
+      description: Backup domain software reset
+      bit_offset: 16
+      bit_size: 1
+fieldset/CFGR:
+  description: Clock configuration register (RCC_CFGR)
+  fields:
+    - name: SW
+      description: System clock Switch
+      bit_offset: 0
+      bit_size: 2
+      enum: SW
+    - name: SWS
+      description: System Clock Switch Status
+      bit_offset: 2
+      bit_size: 2
+      enum_read: SWSR
+    - name: HPRE
+      description: AHB prescaler
+      bit_offset: 4
+      bit_size: 4
+      enum: HPRE
+    - name: PPRE1
+      description: APB Low speed prescaler (APB1)
+      bit_offset: 8
+      bit_size: 3
+      enum: PPRE1
+    - name: PPRE2
+      description: APB High speed prescaler (APB2)
+      bit_offset: 11
+      bit_size: 3
+      enum: PPRE1
+    - name: ADCPRE
+      description: ADC prescaler
+      bit_offset: 14
+      bit_size: 2
+      enum: ADCPRE
+    - name: PLLSRC
+      description: PLL entry clock source
+      bit_offset: 16
+      bit_size: 1
+      enum: PLLSRC
+    - name: PLLXTPRE
+      description: HSE divider for PLL entry
+      bit_offset: 17
+      bit_size: 1
+      enum: PLLXTPRE
+    - name: PLLMUL
+      description: PLL Multiplication Factor
+      bit_offset: 18
+      bit_size: 4
+      enum: PLLMUL
+    - name: MCO
+      description: Microcontroller clock output
+      bit_offset: 24
+      bit_size: 3
+      enum: MCO
+fieldset/CFGR2:
+  description: Clock configuration register 2
+  fields:
+    - name: PREDIV1
+      description: PREDIV1 division factor
+      bit_offset: 0
+      bit_size: 4
+      enum: PREDIV1
+fieldset/CIR:
+  description: Clock interrupt register (RCC_CIR)
+  fields:
+    - name: LSIRDYF
+      description: LSI Ready Interrupt flag
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDYF
+      description: LSE Ready Interrupt flag
+      bit_offset: 1
+      bit_size: 1
+    - name: HSIRDYF
+      description: HSI Ready Interrupt flag
+      bit_offset: 2
+      bit_size: 1
+    - name: HSERDYF
+      description: HSE Ready Interrupt flag
+      bit_offset: 3
+      bit_size: 1
+    - name: PLLRDYF
+      description: PLL Ready Interrupt flag
+      bit_offset: 4
+      bit_size: 1
+    - name: CSSF
+      description: Clock Security System Interrupt flag
+      bit_offset: 7
+      bit_size: 1
+    - name: LSIRDYIE
+      description: LSI Ready Interrupt Enable
+      bit_offset: 8
+      bit_size: 1
+    - name: LSERDYIE
+      description: LSE Ready Interrupt Enable
+      bit_offset: 9
+      bit_size: 1
+    - name: HSIRDYIE
+      description: HSI Ready Interrupt Enable
+      bit_offset: 10
+      bit_size: 1
+    - name: HSERDYIE
+      description: HSE Ready Interrupt Enable
+      bit_offset: 11
+      bit_size: 1
+    - name: PLLRDYIE
+      description: PLL Ready Interrupt Enable
+      bit_offset: 12
+      bit_size: 1
+    - name: LSIRDYC
+      description: LSI Ready Interrupt Clear
+      bit_offset: 16
+      bit_size: 1
+    - name: LSERDYC
+      description: LSE Ready Interrupt Clear
+      bit_offset: 17
+      bit_size: 1
+    - name: HSIRDYC
+      description: HSI Ready Interrupt Clear
+      bit_offset: 18
+      bit_size: 1
+    - name: HSERDYC
+      description: HSE Ready Interrupt Clear
+      bit_offset: 19
+      bit_size: 1
+    - name: PLLRDYC
+      description: PLL Ready Interrupt Clear
+      bit_offset: 20
+      bit_size: 1
+    - name: CSSC
+      description: Clock security system interrupt clear
+      bit_offset: 23
+      bit_size: 1
+fieldset/CR:
+  description: Clock control register
+  fields:
+    - name: HSION
+      description: Internal High Speed clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: HSIRDY
+      description: Internal High Speed clock ready flag
+      bit_offset: 1
+      bit_size: 1
+    - name: HSITRIM
+      description: Internal High Speed clock trimming
+      bit_offset: 3
+      bit_size: 5
+    - name: HSICAL
+      description: Internal High Speed clock Calibration
+      bit_offset: 8
+      bit_size: 8
+    - name: HSEON
+      description: External High Speed clock enable
+      bit_offset: 16
+      bit_size: 1
+    - name: HSERDY
+      description: External High Speed clock ready flag
+      bit_offset: 17
+      bit_size: 1
+    - name: HSEBYP
+      description: External High Speed clock Bypass
+      bit_offset: 18
+      bit_size: 1
+    - name: CSSON
+      description: Clock Security System enable
+      bit_offset: 19
+      bit_size: 1
+    - name: PLLON
+      description: PLL enable
+      bit_offset: 24
+      bit_size: 1
+    - name: PLLRDY
+      description: PLL clock ready flag
+      bit_offset: 25
+      bit_size: 1
+fieldset/CSR:
+  description: Control/status register (RCC_CSR)
+  fields:
+    - name: LSION
+      description: Internal low speed oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSIRDY
+      description: Internal low speed oscillator ready
+      bit_offset: 1
+      bit_size: 1
+    - name: RMVF
+      description: Remove reset flag
+      bit_offset: 24
+      bit_size: 1
+    - name: PINRSTF
+      description: PIN reset flag
+      bit_offset: 26
+      bit_size: 1
+    - name: PORRSTF
+      description: POR/PDR reset flag
+      bit_offset: 27
+      bit_size: 1
+    - name: SFTRSTF
+      description: Software reset flag
+      bit_offset: 28
+      bit_size: 1
+    - name: IWDGRSTF
+      description: Independent watchdog reset flag
+      bit_offset: 29
+      bit_size: 1
+    - name: WWDGRSTF
+      description: Window watchdog reset flag
+      bit_offset: 30
+      bit_size: 1
+    - name: LPWRRSTF
+      description: Low-power reset flag
+      bit_offset: 31
+      bit_size: 1
+enum/ADCPRE:
+  bit_size: 2
+  variants:
+    - name: Div2
+      description: PCLK2 divided by 2
+      value: 0
+    - name: Div4
+      description: PCLK2 divided by 4
+      value: 1
+    - name: Div6
+      description: PCLK2 divided by 6
+      value: 2
+    - name: Div8
+      description: PCLK2 divided by 8
+      value: 3
+enum/HPRE:
+  bit_size: 4
+  variants:
+    - name: Div1
+      description: SYSCLK not divided
+      value: 0
+    - name: Div2
+      description: SYSCLK divided by 2
+      value: 8
+    - name: Div4
+      description: SYSCLK divided by 4
+      value: 9
+    - name: Div8
+      description: SYSCLK divided by 8
+      value: 10
+    - name: Div16
+      description: SYSCLK divided by 16
+      value: 11
+    - name: Div64
+      description: SYSCLK divided by 64
+      value: 12
+    - name: Div128
+      description: SYSCLK divided by 128
+      value: 13
+    - name: Div256
+      description: SYSCLK divided by 256
+      value: 14
+    - name: Div512
+      description: SYSCLK divided by 512
+      value: 15
+enum/MCO:
+  bit_size: 3
+  variants:
+    - name: NoMCO
+      description: "MCO output disabled, no clock on MCO"
+      value: 0
+    - name: SYSCLK
+      description: System clock selected
+      value: 4
+    - name: HSI
+      description: HSI oscillator clock selected
+      value: 5
+    - name: HSE
+      description: HSE oscillator clock selected
+      value: 6
+    - name: PLL
+      description: PLL clock divided by 2 selected
+      value: 7
+enum/PLLMUL:
+  bit_size: 4
+  variants:
+    - name: Mul2
+      description: PLL input clock x2
+      value: 0
+    - name: Mul3
+      description: PLL input clock x3
+      value: 1
+    - name: Mul4
+      description: PLL input clock x4
+      value: 2
+    - name: Mul5
+      description: PLL input clock x5
+      value: 3
+    - name: Mul6
+      description: PLL input clock x6
+      value: 4
+    - name: Mul7
+      description: PLL input clock x7
+      value: 5
+    - name: Mul8
+      description: PLL input clock x8
+      value: 6
+    - name: Mul9
+      description: PLL input clock x9
+      value: 7
+    - name: Mul10
+      description: PLL input clock x10
+      value: 8
+    - name: Mul11
+      description: PLL input clock x11
+      value: 9
+    - name: Mul12
+      description: PLL input clock x12
+      value: 10
+    - name: Mul13
+      description: PLL input clock x13
+      value: 11
+    - name: Mul14
+      description: PLL input clock x14
+      value: 12
+    - name: Mul15
+      description: PLL input clock x15
+      value: 13
+    - name: Mul16
+      description: PLL input clock x16
+      value: 14
+    - name: Mul16x
+      description: PLL input clock x16
+      value: 15
+enum/PLLSRC:
+  bit_size: 1
+  variants:
+    - name: HSI_Div2
+      description: HSI divided by 2 selected as PLL input clock
+      value: 0
+    - name: HSE_Div_PREDIV
+      description: HSE divided by PREDIV selected as PLL input clock
+      value: 1
+enum/PLLXTPRE:
+  bit_size: 1
+  variants:
+    - name: Div1
+      description: HSE clock not divided
+      value: 0
+    - name: Div2
+      description: HSE clock divided by 2
+      value: 1
+enum/PPRE1:
+  bit_size: 3
+  variants:
+    - name: Div1
+      description: HCLK not divided
+      value: 0
+    - name: Div2
+      description: HCLK divided by 2
+      value: 4
+    - name: Div4
+      description: HCLK divided by 4
+      value: 5
+    - name: Div8
+      description: HCLK divided by 8
+      value: 6
+    - name: Div16
+      description: HCLK divided by 16
+      value: 7
+enum/PREDIV1:
+  bit_size: 4
+  variants:
+    - name: Div1
+      description: PREDIV input clock not divided
+      value: 0
+    - name: Div2
+      description: PREDIV input clock divided by 2
+      value: 1
+    - name: Div3
+      description: PREDIV input clock divided by 3
+      value: 2
+    - name: Div4
+      description: PREDIV input clock divided by 4
+      value: 3
+    - name: Div5
+      description: PREDIV input clock divided by 5
+      value: 4
+    - name: Div6
+      description: PREDIV input clock divided by 6
+      value: 5
+    - name: Div7
+      description: PREDIV input clock divided by 7
+      value: 6
+    - name: Div8
+      description: PREDIV input clock divided by 8
+      value: 7
+    - name: Div9
+      description: PREDIV input clock divided by 9
+      value: 8
+    - name: Div10
+      description: PREDIV input clock divided by 10
+      value: 9
+    - name: Div11
+      description: PREDIV input clock divided by 11
+      value: 10
+    - name: Div12
+      description: PREDIV input clock divided by 12
+      value: 11
+    - name: Div13
+      description: PREDIV input clock divided by 13
+      value: 12
+    - name: Div14
+      description: PREDIV input clock divided by 14
+      value: 13
+    - name: Div15
+      description: PREDIV input clock divided by 15
+      value: 14
+    - name: Div16
+      description: PREDIV input clock divided by 16
+      value: 15
+enum/RTCSEL:
+  bit_size: 2
+  variants:
+    - name: NoClock
+      description: No clock
+      value: 0
+    - name: LSE
+      description: LSE oscillator clock used as RTC clock
+      value: 1
+    - name: LSI
+      description: LSI oscillator clock used as RTC clock
+      value: 2
+    - name: HSE
+      description: HSE oscillator clock divided by a prescaler used as RTC clock
+      value: 3
+enum/SW:
+  bit_size: 2
+  variants:
+    - name: HSI
+      description: HSI selected as system clock
+      value: 0
+    - name: HSE
+      description: HSE selected as system clock
+      value: 1
+    - name: PLL
+      description: PLL selected as system clock
+      value: 2
+enum/SWSR:
+  bit_size: 2
+  variants:
+    - name: HSI
+      description: HSI oscillator used as system clock
+      value: 0
+    - name: HSE
+      description: HSE oscillator used as system clock
+      value: 1
+    - name: PLL
+      description: PLL used as system clock
+      value: 2
diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml
index ff4bbf3..2512e2d 100644
--- a/data/registers/rcc_f1cl.yaml
+++ b/data/registers/rcc_f1cl.yaml
@@ -73,14 +73,6 @@ fieldset/AHBENR:
       description: CRC clock enable
       bit_offset: 6
       bit_size: 1
-    - name: FSMCEN
-      description: FSMC clock enable
-      bit_offset: 8
-      bit_size: 1
-    - name: SDIOEN
-      description: SDIO clock enable
-      bit_offset: 10
-      bit_size: 1
     - name: USB_OTG_FSEN
       description: USB OTG FS clock enable
       bit_offset: 12
@@ -135,18 +127,6 @@ fieldset/APB1ENR:
       description: Timer 7 clock enable
       bit_offset: 5
       bit_size: 1
-    - name: TIM12EN
-      description: Timer 12 clock enable
-      bit_offset: 6
-      bit_size: 1
-    - name: TIM13EN
-      description: Timer 13 clock enable
-      bit_offset: 7
-      bit_size: 1
-    - name: TIM14EN
-      description: Timer 14 clock enable
-      bit_offset: 8
-      bit_size: 1
     - name: WWDGEN
       description: Window watchdog clock enable
       bit_offset: 11
@@ -183,18 +163,10 @@ fieldset/APB1ENR:
       description: I2C 2 clock enable
       bit_offset: 22
       bit_size: 1
-    - name: USBEN
-      description: USB clock enable
-      bit_offset: 23
-      bit_size: 1
     - name: CAN1EN
       description: CAN1 clock enable
       bit_offset: 25
       bit_size: 1
-    - name: CANEN
-      description: CAN clock enable
-      bit_offset: 25
-      bit_size: 1
     - name: CAN2EN
       description: CAN2 clock enable
       bit_offset: 26
@@ -211,10 +183,6 @@ fieldset/APB1ENR:
       description: DAC interface clock enable
       bit_offset: 29
       bit_size: 1
-    - name: CECEN
-      description: CEC clock enable
-      bit_offset: 30
-      bit_size: 1
 fieldset/APB1RSTR:
   description: APB1 peripheral reset register (RCC_APB1RSTR)
   fields:
@@ -242,18 +210,6 @@ fieldset/APB1RSTR:
       description: Timer 7 reset
       bit_offset: 5
       bit_size: 1
-    - name: TIM12RST
-      description: Timer 12 reset
-      bit_offset: 6
-      bit_size: 1
-    - name: TIM13RST
-      description: Timer 13 reset
-      bit_offset: 7
-      bit_size: 1
-    - name: TIM14RST
-      description: Timer 14 reset
-      bit_offset: 8
-      bit_size: 1
     - name: WWDGRST
       description: Window watchdog reset
       bit_offset: 11
@@ -290,18 +246,10 @@ fieldset/APB1RSTR:
       description: I2C2 reset
       bit_offset: 22
       bit_size: 1
-    - name: USBRST
-      description: USB reset
-      bit_offset: 23
-      bit_size: 1
     - name: CAN1RST
       description: CAN1 reset
       bit_offset: 25
       bit_size: 1
-    - name: CANRST
-      description: CAN reset
-      bit_offset: 25
-      bit_size: 1
     - name: CAN2RST
       description: CAN2 reset
       bit_offset: 26
@@ -318,10 +266,6 @@ fieldset/APB1RSTR:
       description: DAC interface reset
       bit_offset: 29
       bit_size: 1
-    - name: CECRST
-      description: CEC reset
-      bit_offset: 30
-      bit_size: 1
 fieldset/APB2ENR:
   description: APB2 peripheral clock enable register (RCC_APB2ENR)
   fields:
@@ -349,14 +293,6 @@ fieldset/APB2ENR:
       description: I/O port E clock enable
       bit_offset: 6
       bit_size: 1
-    - name: GPIOFEN
-      description: I/O port F clock enable
-      bit_offset: 7
-      bit_size: 1
-    - name: GPIOGEN
-      description: I/O port G clock enable
-      bit_offset: 8
-      bit_size: 1
     - name: ADC1EN
       description: ADC 1 interface clock enable
       bit_offset: 9
@@ -373,42 +309,10 @@ fieldset/APB2ENR:
       description: SPI 1 clock enable
       bit_offset: 12
       bit_size: 1
-    - name: TIM8EN
-      description: TIM8 Timer clock enable
-      bit_offset: 13
-      bit_size: 1
     - name: USART1EN
       description: USART1 clock enable
       bit_offset: 14
       bit_size: 1
-    - name: ADC3EN
-      description: ADC3 interface clock enable
-      bit_offset: 15
-      bit_size: 1
-    - name: TIM15EN
-      description: TIM15 Timer clock enable
-      bit_offset: 16
-      bit_size: 1
-    - name: TIM16EN
-      description: TIM16 Timer clock enable
-      bit_offset: 17
-      bit_size: 1
-    - name: TIM17EN
-      description: TIM17 Timer clock enable
-      bit_offset: 18
-      bit_size: 1
-    - name: TIM9EN
-      description: TIM9 Timer clock enable
-      bit_offset: 19
-      bit_size: 1
-    - name: TIM10EN
-      description: TIM10 Timer clock enable
-      bit_offset: 20
-      bit_size: 1
-    - name: TIM11EN
-      description: TIM11 Timer clock enable
-      bit_offset: 21
-      bit_size: 1
 fieldset/APB2RSTR:
   description: APB2 peripheral reset register (RCC_APB2RSTR)
   fields:
@@ -436,14 +340,6 @@ fieldset/APB2RSTR:
       description: IO port E reset
       bit_offset: 6
       bit_size: 1
-    - name: GPIOFRST
-      description: IO port F reset
-      bit_offset: 7
-      bit_size: 1
-    - name: GPIOGRST
-      description: IO port G reset
-      bit_offset: 8
-      bit_size: 1
     - name: ADC1RST
       description: ADC 1 interface reset
       bit_offset: 9
@@ -460,42 +356,10 @@ fieldset/APB2RSTR:
       description: SPI 1 reset
       bit_offset: 12
       bit_size: 1
-    - name: TIM8RST
-      description: TIM8 timer reset
-      bit_offset: 13
-      bit_size: 1
     - name: USART1RST
       description: USART1 reset
       bit_offset: 14
       bit_size: 1
-    - name: ADC3RST
-      description: ADC 3 interface reset
-      bit_offset: 15
-      bit_size: 1
-    - name: TIM15RST
-      description: TIM15 timer reset
-      bit_offset: 16
-      bit_size: 1
-    - name: TIM16RST
-      description: TIM16 timer reset
-      bit_offset: 17
-      bit_size: 1
-    - name: TIM17RST
-      description: TIM17 timer reset
-      bit_offset: 18
-      bit_size: 1
-    - name: TIM9RST
-      description: TIM9 timer reset
-      bit_offset: 19
-      bit_size: 1
-    - name: TIM10RST
-      description: TIM10 timer reset
-      bit_offset: 20
-      bit_size: 1
-    - name: TIM11RST
-      description: TIM11 timer reset
-      bit_offset: 21
-      bit_size: 1
 fieldset/BDCR:
   description: Backup domain control register (RCC_BDCR)
   fields:
@@ -525,7 +389,7 @@ fieldset/BDCR:
       bit_offset: 16
       bit_size: 1
 fieldset/CFGR:
-  description: Clock configuration register (RCC_3FGR)
+  description: Clock configuration register (RCC_CFGR)
   fields:
     - name: SW
       description: System clock Switch
@@ -572,11 +436,6 @@ fieldset/CFGR:
       bit_offset: 18
       bit_size: 4
       enum: PLLMUL
-    - name: OTGFSPRE
-      description: USB OTG FS prescaler
-      bit_offset: 22
-      bit_size: 1
-      enum: OTGFSPRE
     - name: USBPRE
       description: USB prescaler
       bit_offset: 22
@@ -828,10 +687,10 @@ enum/ADCPRE:
       description: PCLK2 divided by 4
       value: 1
     - name: Div6
-      description: PCLK2 divided by 8
+      description: PCLK2 divided by 6
       value: 2
     - name: Div8
-      description: PCLK2 divided by 16
+      description: PCLK2 divided by 8
       value: 3
 enum/HPRE:
   bit_size: 4
@@ -902,15 +761,6 @@ enum/MCO:
     - name: PLL3
       description: PLL3 clock selected
       value: 11
-enum/OTGFSPRE:
-  bit_size: 1
-  variants:
-    - name: DIV1_5
-      description: PLL clock is divided by 1.5
-      value: 0
-    - name: DIV1
-      description: PLL clock is not divided
-      value: 1
 enum/PLL2MUL:
   bit_size: 4
   variants:
@@ -944,12 +794,6 @@ enum/PLL2MUL:
 enum/PLLMUL:
   bit_size: 4
   variants:
-    - name: Mul2
-      description: PLL input clock x2
-      value: 0
-    - name: Mul3
-      description: PLL input clock x3
-      value: 1
     - name: Mul4
       description: PLL input clock x4
       value: 2
@@ -968,30 +812,9 @@ enum/PLLMUL:
     - name: Mul9
       description: PLL input clock x9
       value: 7
-    - name: Mul10
-      description: PLL input clock x10
-      value: 8
-    - name: Mul11
-      description: PLL input clock x11
-      value: 9
-    - name: Mul12
-      description: PLL input clock x12
-      value: 10
-    - name: Mul13
-      description: PLL input clock x13
-      value: 11
-    - name: Mul14
-      description: PLL input clock x14
-      value: 12
-    - name: Mul15
-      description: PLL input clock x15
+    - name: Mul6_5
+      description: PLL input clock x6.5
       value: 13
-    - name: Mul16
-      description: PLL input clock x16
-      value: 14
-    - name: Mul16x
-      description: PLL input clock x16
-      value: 15
 enum/PLLSRC:
   bit_size: 1
   variants:
diff --git a/stm32data/__main__.py b/stm32data/__main__.py
index 76f8fa9..fb74191 100755
--- a/stm32data/__main__.py
+++ b/stm32data/__main__.py
@@ -177,7 +177,8 @@ perimap = [
     ('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')),
 
     ('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')),
-    ('STM32F10[0123].*:RCC:.*', ('rcc', 'f1', 'RCC')),
+    ('STM32F100.*:RCC:.*', ('rcc', 'f100', 'RCC')),
+    ('STM32F10[123].*:RCC:.*', ('rcc', 'f1', 'RCC')),
     ('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')),
     ('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')),
     ('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')),
@@ -1268,7 +1269,7 @@ def parse_rcc_regs():
                                 'field': field['name'],
                             }
                         }
-                        if rstr := y[key.replace('ENR', 'RSTR')]:
+                        if rstr := y.get(key.replace('ENR', 'RSTR')):
                             if field := next(filter(lambda f: f['name'] == f'{peri}RST', rstr['fields']), None):
                                 res['reset'] = {
                                     'register': reg.replace('ENR', 'RSTR'),