From 902b9a6986335e4d28e759ec057c23ea35a360d2 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 31 Aug 2021 14:34:54 +0200 Subject: [PATCH 1/2] Add PWR peripheral for STM32WL5 --- data/registers/pwr_wl5.yaml | 1112 +++++++++++++++++++++++++++++++++++ parse.py | 1 + 2 files changed, 1113 insertions(+) create mode 100644 data/registers/pwr_wl5.yaml diff --git a/data/registers/pwr_wl5.yaml b/data/registers/pwr_wl5.yaml new file mode 100644 index 0000000..a386b43 --- /dev/null +++ b/data/registers/pwr_wl5.yaml @@ -0,0 +1,1112 @@ +--- +block/PWR: + description: Power control + items: + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: CR5 + description: Power control register 5 + byte_offset: 28 + fieldset: CR5 + - name: PUCRA + description: Power Port A pull-up control register + byte_offset: 32 + fieldset: PUCRA + - name: PDCRA + description: Power Port A pull-down control register + byte_offset: 36 + fieldset: PDCRA + - name: PUCRB + description: Power Port B pull-up control register + byte_offset: 40 + fieldset: PUCRB + - name: PDCRB + description: Power Port B pull-down control register + byte_offset: 44 + fieldset: PDCRB + - name: PUCRC + description: Power Port C pull-up control register + byte_offset: 48 + fieldset: PUCRC + - name: PDCRC + description: Power Port C pull-down control register + byte_offset: 52 + fieldset: PDCRC + - name: PUCRH + description: Power Port H pull-up control register + byte_offset: 88 + fieldset: PUCRH + - name: PDCRH + description: Power Port H pull-down control register + byte_offset: 92 + fieldset: PDCRH + - name: C2CR1 + description: "Power CPU2 control register 1 [dual core device only]" + byte_offset: 128 + fieldset: C2CR1 + - name: C2CR3 + description: "Power CPU2 control register 3 [dual core device only]" + byte_offset: 132 + fieldset: C2CR3 + - name: EXTSCR + description: Power extended status and status clear register + byte_offset: 136 + fieldset: EXTSCR + - name: SECCFGR + description: "Power security configuration register [dual core device only]" + byte_offset: 140 + fieldset: SECCFGR + - name: SUBGHZSPICR + description: Power SPI3 control register + byte_offset: 144 + fieldset: SUBGHZSPICR + - name: RSSCMDR + description: "RSS Command register [dual core device only]" + byte_offset: 152 + fieldset: RSSCMDR +fieldset/C2CR1: + description: "Power CPU2 control register 1 [dual core device only]" + fields: + - name: LPMS + description: Low-power mode selection for CPU2 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash memory power down mode during LPRun for CPU2 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash memory power down mode during LPSleep for CPU2 + bit_offset: 5 + bit_size: 1 +fieldset/C2CR3: + description: "Power CPU2 control register 3 [dual core device only]" + fields: + - name: EWUP + description: Enable Wakeup pin WKUP1 for CPU2 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: EWPVD + description: Enable wakeup PVD for CPU2 + bit_offset: 8 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration for CPU2 + bit_offset: 10 + bit_size: 1 + - name: EWRFBUSY + description: EWRFBUSY + bit_offset: 11 + bit_size: 1 + - name: EWRFIRQ + description: akeup for CPU2 + bit_offset: 13 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU2 + bit_offset: 15 + bit_size: 1 +fieldset/CR1: + description: Power control register 1 + fields: + - name: LPMS + description: Low-power mode selection for CPU1 + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: SUBGHZSPINSSSEL + description: sub-GHz SPI NSS source select + bit_offset: 3 + bit_size: 1 + enum: SUBGHZSPINSSSEL + - name: FPDR + description: Flash memory power down mode during LPRun for CPU1 + bit_offset: 4 + bit_size: 1 + enum: FPDR + - name: FPDS + description: Flash memory power down mode during LPSleep for CPU1 + bit_offset: 5 + bit_size: 1 + enum: FPDS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + enum: DBP + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 + enum: LPR +fieldset/CR2: + description: Power control register 2 + fields: + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + enum: PVDE + - name: PLS + description: Power voltage detector level selection. + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: PVME + description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" + bit_offset: 6 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: PVME +fieldset/CR3: + description: Power control register 3 + fields: + - name: EWUP + description: Enable Wakeup pin WKUP1 for CPU1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: EWUP + - name: EULPEN + description: Ultra-low-power enable + bit_offset: 7 + bit_size: 1 + enum: EULPEN + - name: EWPVD + description: Enable wakeup PVD for CPU1 + bit_offset: 8 + bit_size: 1 + enum: EWPVD + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 9 + bit_size: 1 + enum: RRS + - name: APC + description: Apply pull-up and pull-down configuration from CPU1 + bit_offset: 10 + bit_size: 1 + enum: APC + - name: EWRFBUSY + description: Enable Radio BUSY Wakeup from Standby for CPU1 + bit_offset: 11 + bit_size: 1 + enum: EWRFBUSY + - name: EWRFIRQ + description: akeup for CPU1 + bit_offset: 13 + bit_size: 1 + enum: EWRFIRQ + - name: EC2H + description: nable CPU2 Hold interrupt for CPU1 + bit_offset: 14 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU1 + bit_offset: 15 + bit_size: 1 + enum: EIWUL +fieldset/CR4: + description: Power control register 4 + fields: + - name: WP + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: WP + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + enum: VBE + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + enum: VBRS + - name: WRFBUSYP + description: Wakeup Radio BUSY polarity + bit_offset: 11 + bit_size: 1 + enum: WRFBUSYP + - name: C2BOOT + description: oot CPU2 after reset or wakeup from Stop or Standby modes. + bit_offset: 15 + bit_size: 1 +fieldset/CR5: + description: Power control register 5 + fields: + - name: RFEOLEN + description: Enable Radio End Of Life detector enabled + bit_offset: 14 + bit_size: 1 + enum: RFEOLEN + - name: SMPSEN + description: Enable SMPS Step Down converter SMPS mode enabled. + bit_offset: 15 + bit_size: 1 + enum: SMPSEN +fieldset/EXTSCR: + description: Power extended status and status clear register + fields: + - name: C1CSSF + description: Clear CPU1 Stop Standby flags + bit_offset: 0 + bit_size: 1 + enum_write: CCSSFW + - name: C2CSSF + description: lear CPU2 Stop Standby flags + bit_offset: 1 + bit_size: 1 + - name: C1SBF + description: System Standby flag for CPU1. (no core states retained) + bit_offset: 8 + bit_size: 1 + enum: CSBF + - name: C1STOP2F + description: System Stop2 flag for CPU1. (partial core states retained) + bit_offset: 9 + bit_size: 1 + enum: CSTOPF + - name: C1STOPF + description: "System Stop0, 1 flag for CPU1. (All core states retained)" + bit_offset: 10 + bit_size: 1 + enum: CSTOPF + - name: C2SBF + description: ystem Standby flag for CPU2. (no core states retained) + bit_offset: 11 + bit_size: 1 + - name: C2STOP2F + description: ystem Stop2 flag for CPU2. (partial core states retained) + bit_offset: 12 + bit_size: 1 + - name: C2STOPF + description: "ystem Stop0, 1 flag for CPU2. (All core states retained)" + bit_offset: 13 + bit_size: 1 + - name: C1DS + description: CPU1 deepsleep mode + bit_offset: 14 + bit_size: 1 + enum: CDS + - name: C2DS + description: PU2 deepsleep mode + bit_offset: 15 + bit_size: 1 +fieldset/PDCRA: + description: Power Port A pull-down control register + fields: + - name: PD + description: PD0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: PDCRA_PD +fieldset/PDCRB: + description: Power Port B pull-down control register + fields: + - name: PD + description: PD0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: PDCRB_PD +fieldset/PDCRC: + description: Power Port C pull-down control register + fields: + - name: PD + description: PD0 + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 13 + - 14 + - 15 + enum: PD +fieldset/PDCRH: + description: Power Port H pull-down control register + fields: + - name: PD + description: pull-down + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: PD +fieldset/PUCRA: + description: Power Port A pull-up control register + fields: + - name: PU + description: PU0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: PUCRA_PU +fieldset/PUCRB: + description: Power Port B pull-up control register + fields: + - name: PU + description: PU0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: PUCRB_PU +fieldset/PUCRC: + description: Power Port C pull-up control register + fields: + - name: PU + description: PU0 + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 13 + - 14 + - 15 + enum: PU +fieldset/PUCRH: + description: Power Port H pull-up control register + fields: + - name: PU + description: pull-up + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: PU +fieldset/RSSCMDR: + description: "RSS Command register [dual core device only]" + fields: + - name: RSSCMD + description: RSS command + bit_offset: 0 + bit_size: 8 +fieldset/SCR: + description: Power status clear register + fields: + - name: CWUF + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + enum_write: CWUFW + - name: CWPVDF + description: Clear wakeup PVD interrupt flag + bit_offset: 8 + bit_size: 1 + enum_write: CWPVDFW + - name: CWRFBUSYF + description: Clear wakeup Radio BUSY flag + bit_offset: 11 + bit_size: 1 + enum_write: CWRFBUSYFW + - name: CC2HF + description: lear CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 +fieldset/SECCFGR: + description: "Power security configuration register [dual core device only]" + fields: + - name: C2EWILA + description: wakeup on CPU2 illegal access interrupt enable + bit_offset: 15 + bit_size: 1 +fieldset/SR1: + description: Power status register 1 + fields: + - name: WUF + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: WUF + - name: WPVDF + description: Wakeup PVD flag + bit_offset: 8 + bit_size: 1 + enum: WPVDF + - name: WRFBUSYF + description: Radio BUSY wakeup flag + bit_offset: 11 + bit_size: 1 + enum: WRFBUSYF + - name: C2HF + description: PU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 + - name: WUFI + description: Internal wakeup interrupt flag + bit_offset: 15 + bit_size: 1 + enum: WUFI +fieldset/SR2: + description: Power status register 2 + fields: + - name: C2BOOTS + description: PU2 boot/wakeup request source information + bit_offset: 0 + bit_size: 1 + - name: RFBUSYS + description: Radio BUSY signal status + bit_offset: 1 + bit_size: 1 + enum: RFBUSYS + - name: RFBUSYMS + description: Radio BUSY masked signal status + bit_offset: 2 + bit_size: 1 + enum: RFBUSYMS + - name: SMPSRDY + description: SMPS ready flag + bit_offset: 3 + bit_size: 1 + enum: SMPSRDY + - name: LDORDY + description: LDO ready flag + bit_offset: 4 + bit_size: 1 + enum: LDORDY + - name: RFEOLF + description: Radio end of life flag + bit_offset: 5 + bit_size: 1 + enum: RFEOLF + - name: REGMRS + description: regulator2 low power flag + bit_offset: 6 + bit_size: 1 + enum: REGMRS + - name: FLASHRDY + description: Flash ready + bit_offset: 7 + bit_size: 1 + enum: FLASHRDY + - name: REGLPS + description: regulator1 started + bit_offset: 8 + bit_size: 1 + enum: REGLPS + - name: REGLPF + description: regulator1 low power flag + bit_offset: 9 + bit_size: 1 + enum: REGLPF + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + enum: VOSF + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + enum: PVDO + - name: PVMO + description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" + bit_offset: 14 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: PVMO +fieldset/SUBGHZSPICR: + description: Power SPI3 control register + fields: + - name: NSS + description: sub-GHz SPI NSS control + bit_offset: 15 + bit_size: 1 + enum: NSS +enum/APC: + bit_size: 1 + variants: + - name: Disabled + description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied + value: 0 + - name: Enabled + description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os + value: 1 +enum/CCSSFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the C1STOPF and C1SBF bits + value: 1 +enum/CDS: + bit_size: 1 + variants: + - name: RunningOrSleep + description: CPU is running or in sleep + value: 0 + - name: DeepSleep + description: CPU is in Deep-Sleep + value: 1 +enum/CSBF: + bit_size: 1 + variants: + - name: NoStandby + description: System has not been in Standby mode + value: 0 + - name: Standby + description: System has been in Standby mode + value: 1 +enum/CSTOPF: + bit_size: 1 + variants: + - name: NoStop + description: System has not been in Stop 2 mode + value: 0 + - name: Stop + description: System has been in Stop 2 mode + value: 1 +enum/CWPVDFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0. + value: 1 +enum/CWRFBUSYFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0. + value: 1 +enum/CWUFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0. + value: 1 +enum/DBP: + bit_size: 1 + variants: + - name: Disabled + description: Access to RTC and backup registers disabled + value: 0 + - name: Enabled + description: Access to RTC and backup registers enabled + value: 1 +enum/EIWUL: + bit_size: 1 + variants: + - name: Disabled + description: Internal wakeup line interrupt to CPU disabled + value: 0 + - name: Enabled + description: Internal wakeup line interrupt to CPU enabled + value: 1 +enum/EULPEN: + bit_size: 1 + variants: + - name: Disabled + description: Disable (the supply voltage is monitored continuously) + value: 0 + - name: Enabled + description: "Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically" + value: 1 +enum/EWPVD: + bit_size: 1 + variants: + - name: Disabled + description: PVD not enabled by the sub-GHz radio active state + value: 0 + - name: Enabled + description: PVD enabled while the sub-GHz radio is active + value: 1 +enum/EWRFBUSY: + bit_size: 1 + variants: + - name: Disabled + description: Radio Busy is disabled and does not trigger a wakeup from Standby event to CPUwhen a rising or a falling edge occurs + value: 0 + - name: Enabled + description: Radio Busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4 + value: 1 +enum/EWRFIRQ: + bit_size: 1 + variants: + - name: Disabled + description: "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU." + value: 0 + - name: Enabled + description: "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU." + value: 1 +enum/EWUP: + bit_size: 1 + variants: + - name: Disabled + description: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode + value: 0 + - name: Enabled + description: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode) + value: 1 +enum/FLASHRDY: + bit_size: 1 + variants: + - name: NotReady + description: Flash memory not ready to be accessed + value: 0 + - name: Ready + description: Flash memory ready to be accessed + value: 1 +enum/FPDR: + bit_size: 1 + variants: + - name: Idle + description: Flash memory in Idle mode when system is in LPRun mode + value: 0 + - name: PowerDown + description: Flash memory in Power-down mode when system is in LPRun mode + value: 1 +enum/FPDS: + bit_size: 1 + variants: + - name: Idle + description: Flash memory in Idle mode when system is in LPSleep mode + value: 0 + - name: PowerDown + description: Flash memory in Power-down mode when system is in LPSleep mode + value: 1 +enum/LDORDY: + bit_size: 1 + variants: + - name: NotReady + description: LDO not ready or off + value: 0 + - name: Ready + description: LDO ready + value: 1 +enum/LPMS: + bit_size: 3 + variants: + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Standby + description: Standby mode + value: 3 + - name: Shutdown + description: Shutdown mode + value: 4 +enum/LPR: + bit_size: 1 + variants: + - name: MainMode + description: Voltage regulator in Main mode in Low-power run mode + value: 0 + - name: LowPowerMode + description: Voltage regulator in low-power mode in Low-power run mode + value: 1 +enum/NSS: + bit_size: 1 + variants: + - name: Low + description: Sub-GHz SPI NSS signal at level low + value: 0 + - name: High + description: Sub-GHz SPI NSS signal is at level high + value: 1 +enum/PD: + bit_size: 1 + variants: + - name: Disabled + description: "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 1 +enum/PDCRA_PD: + bit_size: 1 + variants: + - name: Disabled + description: "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 1 +enum/PDCRB_PD: + bit_size: 1 + variants: + - name: Disabled + description: "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 1 +enum/PDCRC_PD: + bit_size: 1 + variants: + - name: Disabled + description: "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: V2_0 + description: 2.0V + value: 0 + - name: V2_2 + description: 2.2V + value: 1 + - name: V2_4 + description: 2.4V + value: 2 + - name: V2_5 + description: 2.5V + value: 3 + - name: V2_6 + description: 2.6V + value: 4 + - name: V2_8 + description: 2.8V + value: 5 + - name: V2_9 + description: 2.9V + value: 6 + - name: External + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 +enum/PU: + bit_size: 1 + variants: + - name: Disabled + description: "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set" + value: 1 +enum/PUCRA_PU: + bit_size: 1 + variants: + - name: Disabled + description: "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set" + value: 1 +enum/PUCRB_PU: + bit_size: 1 + variants: + - name: Disabled + description: "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set" + value: 1 +enum/PUCRC_PU: + bit_size: 1 + variants: + - name: Disabled + description: "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" + value: 0 + - name: Enabled + description: "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set" + value: 1 +enum/PVDE: + bit_size: 1 + variants: + - name: Disabled + description: PVD Disabled + value: 0 + - name: Enabled + description: PVD Enabled + value: 1 +enum/PVDO: + bit_size: 1 + variants: + - name: Above + description: VDD or voltage level on PVD_IN above the selected PVD threshold + value: 0 + - name: Below + description: VDD or voltage level on PVD_IN below the selected PVD threshold + value: 1 +enum/PVME: + bit_size: 1 + variants: + - name: Disabled + description: PVM3 (VDDA monitoring versus 1.62 V threshold) disable + value: 0 + - name: Enabled + description: PVM3 (VDDA monitoring versus 1.62 V threshold) enable + value: 1 +enum/PVMO: + bit_size: 1 + variants: + - name: Above + description: VDDA voltage above PVM3 threshold (around 1.62 V) + value: 0 + - name: Below + description: VDDA voltage below PVM3 threshold (around 1.62 V) + value: 1 +enum/REGLPF: + bit_size: 1 + variants: + - name: Main + description: Main regulator (MR) ready and used + value: 0 + - name: LowPower + description: Low-power regulator (LPR) used + value: 1 +enum/REGLPS: + bit_size: 1 + variants: + - name: NotReady + description: LPR not ready + value: 0 + - name: Ready + description: LPR ready + value: 1 +enum/REGMRS: + bit_size: 1 + variants: + - name: V_DD + description: Main regulator supplied directly from VDD + value: 0 + - name: LDO_SMPS + description: Main regulator supplied through LDO or SMPS + value: 1 +enum/RFBUSYMS: + bit_size: 1 + variants: + - name: NotBusy + description: radio busy masked signal low (not busy) + value: 0 + - name: Busy + description: radio busy masked signal high (busy) + value: 1 +enum/RFBUSYS: + bit_size: 1 + variants: + - name: NotBusy + description: radio busy signal low (not busy) + value: 0 + - name: Busy + description: radio busy signal high (busy) + value: 1 +enum/RFEOLEN: + bit_size: 1 + variants: + - name: Disabled + description: Radio end-of-life detector disabled + value: 0 + - name: Enabled + description: Radio end-of-life detector enabled + value: 1 +enum/RFEOLF: + bit_size: 1 + variants: + - name: Above + description: Supply voltage above radio end-of-life operating low level + value: 0 + - name: Below + description: Supply voltage below radio end-of-life operating low level + value: 1 +enum/RRS: + bit_size: 1 + variants: + - name: PowerOff + description: SRAM2 powered off in Standby mode (SRAM2 content lost) + value: 0 + - name: OnLPR + description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + value: 1 +enum/SMPSEN: + bit_size: 1 + variants: + - name: Disabled + description: SMPS step-down converter SMPS mode disabled (LDO mode enabled) + value: 0 + - name: Enabled + description: SMPS step-down converter SMPS mode enabled + value: 1 +enum/SMPSRDY: + bit_size: 1 + variants: + - name: NotReady + description: SMPS step-down converter not ready or off + value: 0 + - name: Ready + description: SMPS step-down converter ready + value: 1 +enum/SUBGHZSPINSSSEL: + bit_size: 1 + variants: + - name: SUBGHZSPICR + description: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled) + value: 0 + - name: LPTIM3 + description: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled) + value: 1 +enum/VBE: + bit_size: 1 + variants: + - name: Disabled + description: VBAT battery charging disabled + value: 0 + - name: Enabled + description: VBAT battery charging enabled + value: 1 +enum/VBRS: + bit_size: 1 + variants: + - name: R5k + description: VBAT charging through a 5 kΩ resistor + value: 0 + - name: R1_5k + description: VBAT charging through a 1.5 kΩ resistor + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: V1_2 + description: 1.2 V (range 1) + value: 1 + - name: V1_0 + description: 1.0 V (range 2) + value: 2 +enum/VOSF: + bit_size: 1 + variants: + - name: Ready + description: Regulator ready in the selected voltage range + value: 0 + - name: Change + description: Regulator output voltage changed to the required voltage level + value: 1 +enum/WP: + bit_size: 1 + variants: + - name: RisingEdge + description: Detection on high level (rising edge) + value: 0 + - name: FallingEdge + description: Detection on low level (falling edge) + value: 1 +enum/WPVDF: + bit_size: 1 + variants: + - name: Clear + description: No wakeup event detected on PVD + value: 0 + - name: Wakeup + description: Wakeup event detected on PVD + value: 1 +enum/WRFBUSYF: + bit_size: 1 + variants: + - name: Clear + description: No wakeup event detected on radio busy + value: 0 + - name: Wakeup + description: Wakeup event detected on radio busy + value: 1 +enum/WRFBUSYP: + bit_size: 1 + variants: + - name: RisingEdge + description: Detection on high level (rising edge) + value: 0 + - name: FallingEdge + description: Detection on low level (falling edge) + value: 1 +enum/WUF: + bit_size: 1 + variants: + - name: Clear + description: No wakeup event detected on WKUP3 + value: 0 + - name: Wakeup + description: Wakeup event detected on WKUP3 + value: 1 +enum/WUFI: + bit_size: 1 + variants: + - name: Clear + description: All internal wakeup sources are cleared + value: 0 + - name: Wakeup + description: wakeup is detected on the internal wakeup line + value: 1 diff --git a/parse.py b/parse.py index 440dd40..4454769 100755 --- a/parse.py +++ b/parse.py @@ -387,6 +387,7 @@ perimap = [ ('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'), ('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'), + ('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), ('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'), ('.*:STM32F4_flash_v1_0', 'flash_f4/FLASH'), From 201510407c3bd6debd2329bb9c8e3b79b83c75f6 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 31 Aug 2021 14:43:02 +0200 Subject: [PATCH 2/2] Handle SUBGHZSPI peripheral so it is recognized as an SPI peripheral --- parse.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/parse.py b/parse.py index 4454769..e890c7e 100755 --- a/parse.py +++ b/parse.py @@ -714,6 +714,11 @@ def parse_chips(): signal_name = parts[1] if signal_name.startswith("EXTI"): continue + if peri_name.startswith("DEBUG") and signal_name.startswith("SUBGHZSPI"): + parts = signal_name.split('-', 1) + if len(parts) == 2: + peri_name = parts[0] + signal_name = removesuffix(parts[1], "OUT") if not peri_name in pins: pins[peri_name] = [] entry = OrderedDict({ @@ -1057,6 +1062,11 @@ def parse_gpio_af(): afs = {} for signal in children(pin, 'PinSignal'): func = signal['@Name'] + if func.startswith("DEBUG_SUBGHZSPI"): + func = removeprefix(func, "DEBUG_") + parts = func.split('-', 2) + if len(parts) > 1: + func = parts[0] + '_' + removesuffix(parts[1], "OUT") afn = signal['SpecificParameter']['PossibleValue'].split('_')[1] afn = int(removeprefix(afn, 'AF')) afs[func] = afn