From 93a943cf3a10fbff8a18734cb3f99a5a8277f6e4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 18:33:51 +0800 Subject: [PATCH] apply transform --- data/registers/saes_v1a.yaml | 249 +++-------------------------------- transforms/SAES.yaml | 19 +++ 2 files changed, 38 insertions(+), 230 deletions(-) create mode 100644 transforms/SAES.yaml diff --git a/data/registers/saes_v1a.yaml b/data/registers/saes_v1a.yaml index d1bae76..8c3a3bd 100644 --- a/data/registers/saes_v1a.yaml +++ b/data/registers/saes_v1a.yaml @@ -12,91 +12,34 @@ block/SAES: - name: DINR description: SAES data input register. byte_offset: 8 - fieldset: DINR - name: DOUTR description: SAES data output register. byte_offset: 12 - fieldset: DOUTR - - name: KEYR0 + - name: KEYR description: SAES key register 0. + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: SAES key register 1. - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: SAES key register 2. - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: SAES key register 3. - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 + - name: IVR description: SAES initialization vector register 0. + array: + len: 4 + stride: 4 byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: SAES initialization vector register 1. - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: SAES initialization vector register 2. - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: SAES initialization vector register 3. - byte_offset: 44 - fieldset: IVR3 - - name: KEYR4 - description: SAES key register 4. - byte_offset: 48 - fieldset: KEYR4 - - name: KEYR5 - description: SAES key register 5. - byte_offset: 52 - fieldset: KEYR5 - - name: KEYR6 - description: SAES key register 6. - byte_offset: 56 - fieldset: KEYR6 - - name: KEYR7 - description: SAES key register 7. - byte_offset: 60 - fieldset: KEYR7 - - name: SUSP0R + - name: SUSPR description: SAES suspend registers. + array: + len: 8 + stride: 4 byte_offset: 64 - fieldset: SUSP0R - - name: SUSP1R - description: SAES suspend registers. - byte_offset: 68 - fieldset: SUSP1R - - name: SUSP2R - description: SAES suspend registers. - byte_offset: 72 - fieldset: SUSP2R - - name: SUSP3R - description: SAES suspend registers. - byte_offset: 76 - fieldset: SUSP3R - - name: SUSP4R - description: SAES suspend registers. - byte_offset: 80 - fieldset: SUSP4R - - name: SUSP5R - description: SAES suspend registers. - byte_offset: 84 - fieldset: SUSP5R - - name: SUSP6R - description: SAES suspend registers. - byte_offset: 88 - fieldset: SUSP6R - - name: SUSP7R - description: SAES suspend registers. - byte_offset: 92 - fieldset: SUSP7R - name: IER description: SAES interrupt enable register. byte_offset: 768 @@ -172,20 +115,6 @@ fieldset/CR: description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. bit_offset: 31 bit_size: 1 -fieldset/DINR: - description: SAES data input register. - fields: - - name: DIN - description: 'Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the SAES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the SAES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (SAES_KEYRx registers used for input if KEYSEL=0) - Mode 3 (decryption): ciphertext The data swap operation is described in on page 1149.' - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: SAES data output register. - fields: - - name: DOUT - description: 'Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the SAES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the SAES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used - Mode 3 (decryption): plaintext The data swap operation is described in on page 1149.' - bit_offset: 0 - bit_size: 32 fieldset/ICR: description: SAES interrupt clear register. fields: @@ -243,90 +172,6 @@ fieldset/ISR: description: RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. bit_offset: 3 bit_size: 1 -fieldset/IVR0: - description: SAES initialization vector register 0. - fields: - - name: IVI - description: Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The SAES_IVRx registers may be written only when the SAES peripheral is disabled. - bit_offset: 0 - bit_size: 32 -fieldset/IVR1: - description: SAES initialization vector register 1. - fields: - - name: IVI - description: Initialization vector input, bits [63:32] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: SAES initialization vector register 2. - fields: - - name: IVI - description: Initialization vector input, bits [95:64] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: SAES initialization vector register 3. - fields: - - name: IVI - description: Initialization vector input, bits [127:96] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: SAES key register 0. - fields: - - name: KEY - description: 'Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. The SAES_KEYRx registers may be written only when KEYSIZE value is correct and when the SAES peripheral is disabled (EN bit of the SAES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the SAES_SR register. Note that, if KEYSEL is different from 0 and KEYVALID = 0, the key is directly loaded to SAES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details.' - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: SAES key register 1. - fields: - - name: KEY - description: Cryptographic key, bits [63:32] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: SAES key register 2. - fields: - - name: KEY - description: Cryptographic key, bits [95:64] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: SAES key register 3. - fields: - - name: KEY - description: Cryptographic key, bits [127:96] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR4: - description: SAES key register 4. - fields: - - name: KEY - description: Cryptographic key, bits [159:128] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR5: - description: SAES key register 5. - fields: - - name: KEY - description: Cryptographic key, bits [191:160] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR6: - description: SAES key register 6. - fields: - - name: KEY - description: Cryptographic key, bits [223:192] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR7: - description: SAES key register 7. - fields: - - name: KEY - description: Cryptographic key, bits [255:224] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 fieldset/SR: description: SAES status register. fields: @@ -350,59 +195,3 @@ fieldset/SR: description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. bit_offset: 7 bit_size: 1 -fieldset/SUSP0R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP1R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP2R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP3R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP4R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP5R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP6R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP7R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 diff --git a/transforms/SAES.yaml b/transforms/SAES.yaml new file mode 100644 index 0000000..3739152 --- /dev/null +++ b/transforms/SAES.yaml @@ -0,0 +1,19 @@ +transforms: + - !DeleteFieldsets + from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$ + + - !MakeRegisterArray + blocks: SAES + from: ^(IVR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: SAES + allow_cursed: true + from: ^(KEYR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: SAES + from: ^(SUSP)\d(R)$ + to: $1$2