From 9e680c8d698e4e709cf9cc43e9fef1860e030fb4 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Thu, 14 Dec 2023 21:09:00 +0800
Subject: [PATCH] no need TIM CR1 ARPE enum, just a enable/disable field

---
 data/registers/timer_v1.yaml | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml
index e013ed1..fa3f10c 100644
--- a/data/registers/timer_v1.yaml
+++ b/data/registers/timer_v1.yaml
@@ -358,7 +358,6 @@ fieldset/CR1_BASIC:
     description: Auto-reload preload enable
     bit_offset: 7
     bit_size: 1
-    enum: ARPE
 fieldset/CR1_GP:
   extends: CR1_BASIC
   description: control register 1
@@ -645,15 +644,6 @@ fieldset/SR_GP:
     array:
       len: 4
       stride: 1
-enum/ARPE:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: TIMx_APRR register is not buffered
-    value: 0
-  - name: Enabled
-    description: TIMx_APRR register is buffered
-    value: 1
 enum/CCDS:
   bit_size: 1
   variants: