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Remove some useless enums.

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Apply better variant names to some enums.
This commit is contained in:
Bob McWhirter 2021-11-11 14:09:49 -05:00
parent 117e3f3f4b
commit 91c77958bd
1 changed files with 11 additions and 106 deletions
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117
data/registers/rcc_u5.yaml
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@ -1576,27 +1576,22 @@ fieldset/CFGR2:
description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1." description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1."
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: AHBDIS
- name: AHB2DIS1 - name: AHB2DIS1
description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3." description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3."
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum: AHBDIS
- name: AHB2DIS2 - name: AHB2DIS2
description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off." description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off."
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
enum: AHBDIS
- name: APB1DIS - name: APB1DIS
description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG." description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG."
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
enum: APBDIS
- name: APB2DIS - name: APB2DIS
description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off." description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off."
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
enum: APBDIS
fieldset/CFGR3: fieldset/CFGR3:
description: "RCC clock configuration register 3 " description: "RCC clock configuration register 3 "
fields: fields:
@ -1609,12 +1604,10 @@ fieldset/CFGR3:
description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4." description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4."
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: AHBDIS
- name: APB3DIS - name: APB3DIS
description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off." description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off."
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum: APBDIS
fieldset/CICR: fieldset/CICR:
description: "RCC clock interrupt clear register " description: "RCC clock interrupt clear register "
fields: fields:
@ -1900,37 +1893,30 @@ fieldset/CSR:
description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
enum: OBLRSTF
- name: PINRSTF - name: PINRSTF
description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
enum: PINRSTF
- name: BORRSTF - name: BORRSTF
description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
enum: BORRSTF
- name: SFTRSTF - name: SFTRSTF
description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
enum: SFTRSTF
- name: IWDGRSTF - name: IWDGRSTF
description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
enum: IWDGRSTF
- name: WWDGRSTF - name: WWDGRSTF
description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
enum: WWDGRSTF
- name: LPWRRSTF - name: LPWRRSTF
description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit." description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit."
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
enum: LPWRRSTF
fieldset/ICSCR1: fieldset/ICSCR1:
description: "RCC internal clock sources calibration register 1 " description: "RCC internal clock sources calibration register 1 "
fields: fields:
@ -2338,69 +2324,42 @@ fieldset/SRDAMR:
enum/ADCDACSEL: enum/ADCDACSEL:
bit_size: 3 bit_size: 3
variants: variants:
- name: B_0x0 - name: HCLK
description: HCLK clock selected description: HCLK clock selected
value: 0 value: 0
- name: B_0x1 - name: SYSCLK
description: SYSCLK selected description: SYSCLK selected
value: 1 value: 1
- name: B_0x2 - name: PLL2_R
description: PLL2 R (pll2_r_ck) selected description: PLL2 R (pll2_r_ck) selected
value: 2 value: 2
- name: B_0x3 - name: HSE
description: HSE clock selected description: HSE clock selected
value: 3 value: 3
- name: B_0x4 - name: HSI16
description: HSI16 clock selected description: HSI16 clock selected
value: 4 value: 4
- name: B_0x5 - name: MSI_K
description: MSIK clock selected description: MSIK clock selected
value: 5 value: 5
enum/ADFSEL: enum/ADFSEL:
bit_size: 3 bit_size: 3
variants: variants:
- name: B_0x0 - name: HCLK
description: HCLK selected description: HCLK selected
value: 0 value: 0
- name: B_0x1 - name: PLL1_P
description: PLL1 P (pll1_p_ck) selected description: PLL1 P (pll1_p_ck) selected
value: 1 value: 1
- name: B_0x2 - name: PLL3_Q
description: PLL3 Q (pll3_q_ck) selected description: PLL3 Q (pll3_q_ck) selected
value: 2 value: 2
- name: B_0x3 - name: AUDIOCLK
description: input pin AUDIOCLK selected description: input pin AUDIOCLK selected
value: 3 value: 3
- name: B_0x4 - name: MSIK
description: MSIK clock selected description: MSIK clock selected
value: 4 value: 4
enum/AHBDIS:
bit_size: 1
variants:
- name: B_0x0
description: "AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"
value: 0
- name: B_0x1
description: AHB2_2 clock disabled
value: 1
enum/APBDIS:
bit_size: 1
variants:
- name: B_0x0
description: "APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"
value: 0
- name: B_0x1
description: APB2 clock disabled
value: 1
enum/BORRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No BOR occurred
value: 0
- name: B_0x1
description: BOR occurred
value: 1
enum/CSSF: enum/CSSF:
bit_size: 1 bit_size: 1
variants: variants:
@ -2545,15 +2504,6 @@ enum/ICSEL:
- name: B_0x3 - name: B_0x3
description: MSIK selected description: MSIK selected
value: 3 value: 3
enum/IWDGRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No independent watchdog reset occurred
value: 0
- name: B_0x1
description: Independent watchdog reset occurred
value: 1
enum/LPTIMSEL: enum/LPTIMSEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -2587,15 +2537,6 @@ enum/LPUARTSEL:
- name: MSIK - name: MSIK
description: MSIK selected description: MSIK selected
value: 4 value: 4
enum/LPWRRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No illegal low-power mode reset occurred
value: 0
- name: B_0x1
description: Illegal low-power mode reset occurred
value: 1
enum/LSCOSEL: enum/LSCOSEL:
bit_size: 1 bit_size: 1
variants: variants:
@ -2956,15 +2897,6 @@ enum/NSPRIV:
- name: B_0x1 - name: B_0x1
description: Read and write to RCC non-secure functions can be done by privileged access only. description: Read and write to RCC non-secure functions can be done by privileged access only.
value: 1 value: 1
enum/OBLRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No reset from option byte loading occurred
value: 0
- name: B_0x1
description: Reset from option byte loading occurred
value: 1
enum/OCTOSPISEL: enum/OCTOSPISEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -2980,15 +2912,6 @@ enum/OCTOSPISEL:
- name: PLL2_Q - name: PLL2_Q
description: "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz" description: "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz"
value: 3 value: 3
enum/PINRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No reset from NRST pin occurred
value: 0
- name: B_0x1
description: Reset from NRST pin occurred
value: 1
enum/PLLM: enum/PLLM:
bit_size: 4 bit_size: 4
variants: variants:
@ -3199,15 +3122,6 @@ enum/SDMMCSEL:
- name: B_0x1 - name: B_0x1
description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) " description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) "
value: 1 value: 1
enum/SFTRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No software reset occurred
value: 0
- name: B_0x1
description: Software reset occurred
value: 1
enum/SHSIRDY: enum/SHSIRDY:
bit_size: 1 bit_size: 1
variants: variants:
@ -3349,15 +3263,6 @@ enum/USARTSEL:
- name: LSE - name: LSE
description: LSE selected description: LSE selected
value: 3 value: 3
enum/WWDGRSTF:
bit_size: 1
variants:
- name: B_0x0
description: No window watchdog reset occurred
value: 0
- name: B_0x1
description: Window watchdog reset occurred
value: 1
enum/SECURITY: enum/SECURITY:
bit_size: 1 bit_size: 1
variants: variants: