Add STM32WL5x exti block

data/registers/exti_wl5x.yaml

@@ -0,0 +1,174 @@
+---
+block/EXTI:
+  description: External interrupt/event controller
+  items:
+    - name: RTSR
+      description: rising trigger selection register
+      byte_offset: 0
+      fieldset: RTSR
+      array:
+        len: 2
+        stride: 32
+    - name: FTSR
+      description: falling trigger selection register
+      byte_offset: 4
+      fieldset: FTSR
+      array:
+        len: 2
+        stride: 32
+    - name: SWIER
+      description: software interrupt event register
+      byte_offset: 8
+      fieldset: SWIER
+      array:
+        len: 2
+        stride: 32
+    - name: PR
+      description: EXTI pending register
+      byte_offset: 12
+      fieldset: PR
+      array:
+        len: 2
+        stride: 32
+    - name: CPU
+      description: CPU specific registers
+      byte_offset: 128
+      block: CPU_MASK
+      array:
+        len: 2
+        stride: 64
+block/CPU_MASK:
+  description: CPU-specific mask registers
+  items:
+    - name: IMR
+      description: CPUm wakeup with interrupt mask register
+      byte_offset: 0
+      fieldset: C1IMR
+      array:
+        len: 2
+        stride: 16
+    - name: EMR
+      description: CPUm wakeup with event mask register
+      byte_offset: 4
+      fieldset: C1EMR
+      array:
+        len: 2
+        stride: 16
+fieldset/C1EMR:
+  description: CPUm wakeup with event mask register
+  fields:
+    - name: EM
+      description: CPU(m) Wakeup with event generation Mask on Event input
+      bit_offset: 0
+      bit_size: 16
+      array:
+        len: 32
+        stride: 1
+fieldset/C1IMR:
+  description: CPUm wakeup with interrupt mask register
+  fields:
+    - name: IM
+      description: CPU(m) wakeup with interrupt Mask on Event input
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+      enum: MR
+fieldset/FTSR:
+  description: falling trigger selection register
+  fields:
+    - name: FT
+      description: Falling trigger event configuration bit of Configurable Event input
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+      enum: FT
+fieldset/PR:
+  description: EXTI pending register
+  fields:
+    - name: PIF
+      description: Configurable event inputs Pending bit
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+      enum_read: PRR
+      enum_write: PRW
+fieldset/RTSR:
+  description: rising trigger selection register
+  fields:
+    - name: RT
+      description: Rising trigger event configuration bit of Configurable Event input
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+      enum: RT
+fieldset/SWIER:
+  description: software interrupt event register
+  fields:
+    - name: SWI
+      description: Software interrupt on event
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+fieldset/VERR:
+  description: EXTI IP Version register
+  fields:
+    - name: MINREV
+      description: Minor Revision number
+      bit_offset: 0
+      bit_size: 4
+    - name: MAJREV
+      description: Major Revision number
+      bit_offset: 4
+      bit_size: 4
+enum/FT:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Falling edge trigger is disabled
+      value: 0
+    - name: Enabled
+      description: Falling edge trigger is enabled
+      value: 1
+enum/RT:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Falling edge trigger is disabled
+      value: 0
+    - name: Enabled
+      description: Falling edge trigger is enabled
+      value: 1
+enum/MR:
+  bit_size: 1
+  variants:
+    - name: Masked
+      description: Interrupt request line is masked
+      value: 0
+    - name: Unmasked
+      description: Interrupt request line is unmasked
+      value: 1
+enum/PRR:
+  bit_size: 1
+  variants:
+    - name: NotPending
+      description: No trigger request occurred
+      value: 0
+    - name: Pending
+      description: Selected trigger request occurred
+      value: 1
+enum/PRW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clears pending bit
+      value: 1

parse.py

@@ -885,6 +885,8 @@ def parse_chips():
             if addr := defines.get('EXTI_BASE'):
                 if chip_name.startswith("STM32WB55"):
                     block = 'exti_wb55/EXTI'
+                elif chip_name.startswith("STM32WL5"):
+                    block = 'exti_wl5x/EXTI'
                 elif chip_name.startswith("STM32H7"):
                     block = 'exti_h7/EXTI'
                 else: