From 90ff5316ebb3528fbc416cd29e23ef11c3d62026 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Mon, 20 Nov 2023 13:53:39 +0000
Subject: [PATCH] rcc: fix FDCAN: multiple FDCANs share the same RCC fields

the RCC fields are named either FDCAN or FDCAN12
---
 stm32-data-gen/src/rcc.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 7acb049..5cf80d8 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -322,6 +322,11 @@ impl PeripheralToClock {
         if peri_name.starts_with("ADC") && !peri_name.contains("COMMON") {
             return self.match_adc_peri_clock(clocks, peri_name);
         }
+        if regex!("^FDCAN[0-9]*$").is_match(peri_name) {
+            return [peri_name, "FDCAN12", "FDCAN"]
+                .into_iter()
+                .find_map(|name| clocks.get(name));
+        }
         if let Some(res) = clocks.get(peri_name) {
             Some(res)
         } else if let Some(peri_name) = peri_name.strip_suffix('1') {