diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index f9fdcc3..b0fb55d 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -843,9 +843,9 @@ enum/SWS: enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 + - name: Div1_5 description: PLL clock is divided by 1.5 value: 0 - - name: DIV1 + - name: Div1 description: PLL clock is not divided value: 1 diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index dbaf3a6..95a654e 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -952,9 +952,9 @@ enum/SWS: enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 + - name: Div1_5 description: PLL clock is divided by 1.5 value: 0 - - name: DIV1 + - name: Div1 description: PLL clock is not divided value: 1 diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index cbe8c42..7337227 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -1286,9 +1286,9 @@ enum/USARTSW: enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 + - name: Div1_5 description: PLL clock is divided by 1.5 value: 0 - - name: DIV1 + - name: Div1 description: PLL clock is not divided value: 1 diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml index 9d2c291..e8e9c28 100644 --- a/data/registers/rcc_f3_v2.yaml +++ b/data/registers/rcc_f3_v2.yaml @@ -1262,9 +1262,9 @@ enum/USARTSW: enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 + - name: Div1_5 description: PLL clock is divided by 1.5 value: 0 - - name: DIV1 + - name: Div1 description: PLL clock is not divided value: 1 diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index d951e14..41ee10e 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -2463,7 +2463,7 @@ enum/RNGSEL: enum/RTCSEL: bit_size: 2 variants: - - name: None + - name: NoClock description: no clock (default after Backup domain reset) value: 0 - name: LSE diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 21542a0..0fcf371 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -1631,7 +1631,7 @@ enum/RNGSEL: enum/RTCSEL: bit_size: 2 variants: - - name: None + - name: NoClock description: no clock (default after Backup domain reset) value: 0 - name: LSE diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index bd4b462..7768b0d 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2562,19 +2562,19 @@ enum/DACSEL: enum/DPRE: bit_size: 3 variants: - - name: NONE + - name: Div1 description: DCLK not divided value: 0 - - name: DIV2 + - name: Div2 description: DCLK divided by 2 value: 4 - - name: DIV4 + - name: Div4 description: DCLK divided by 4 value: 5 - - name: DIV8 + - name: Div8 description: DCLK divided by 8 value: 6 - - name: DIV16 + - name: Div16 description: DCLK divided by 16 value: 7 enum/DSISEL: @@ -2601,31 +2601,31 @@ enum/FDCANSEL: enum/HPRE: bit_size: 4 variants: - - name: NONE + - name: Div1 description: SYSCLK not divided value: 0 - - name: DIV2 + - name: Div2 description: SYSCLK divided by 2 value: 8 - - name: DIV4 + - name: Div4 description: SYSCLK divided by 4 value: 9 - - name: DIV8 + - name: Div8 description: SYSCLK divided by 8 value: 10 - - name: DIV16 + - name: Div16 description: SYSCLK divided by 16 value: 11 - - name: DIV64 + - name: Div64 description: SYSCLK divided by 64 value: 12 - - name: DIV128 + - name: Div128 description: SYSCLK divided by 128 value: 13 - - name: DIV256 + - name: Div256 description: SYSCLK divided by 256 value: 14 - - name: DIV512 + - name: Div512 description: SYSCLK divided by 512 value: 15 enum/HSEEXT: @@ -2742,10 +2742,10 @@ enum/LSEDRV: enum/LSIPREDIV: bit_size: 1 variants: - - name: NONE + - name: Div1 description: LSI not divided value: 0 - - name: DIV_128 + - name: Div128 description: LSI divided by 128 value: 1 enum/LTDCSEL: @@ -2760,19 +2760,19 @@ enum/LTDCSEL: enum/MCOPRE: bit_size: 3 variants: - - name: NONE + - name: Div1 description: MCO divided by 1 value: 0 - - name: DIV2 + - name: Div2 description: MCO divided by 2 value: 1 - - name: DIV4 + - name: Div4 description: MCO divided by 4 value: 2 - - name: DIV8 + - name: Div8 description: MCO divided by 8 value: 3 - - name: DIV16 + - name: Div16 description: MCO divided by 16 value: 4 enum/MCOSEL: @@ -2967,13 +2967,13 @@ enum/PLLM: - name: BYPASS description: division by 1 (bypass) value: 0 - - name: DIV2 + - name: Div2 description: division by 2 value: 1 - - name: DIV3 + - name: Div3 description: division by 3 value: 2 - - name: DIV16 + - name: Div16 description: division by 16 value: 15 enum/PLLMBOOST: @@ -2982,28 +2982,28 @@ enum/PLLMBOOST: - name: BYPASS description: division by 1 (bypass) value: 0 - - name: DIV2 + - name: Div2 description: division by 2 value: 1 - - name: DIV4 + - name: Div4 description: division by 4 value: 2 - - name: DIV6 + - name: Div6 description: division by 6 value: 3 - - name: DIV8 + - name: Div8 description: division by 8 value: 4 - - name: DIV10 + - name: Div10 description: division by 10 value: 5 - - name: DIV12 + - name: Div12 description: division by 12 value: 6 - - name: DIV14 + - name: Div14 description: division by 14 value: 7 - - name: DIV16 + - name: Div16 description: division by 16 value: 8 enum/PLLRGE: @@ -3033,19 +3033,19 @@ enum/PLLSRC: enum/PPRE: bit_size: 3 variants: - - name: NONE + - name: Div1 description: HCLK not divided value: 0 - - name: DIV2 + - name: Div2 description: HCLK divided by 2 value: 4 - - name: DIV4 + - name: Div4 description: HCLK divided by 4 value: 5 - - name: DIV8 + - name: Div8 description: HCLK divided by 8 value: 6 - - name: DIV16 + - name: Div16 description: HCLK divided by 16 value: 7 enum/PRIV: @@ -3072,7 +3072,7 @@ enum/RNGSEL: enum/RTCSEL: bit_size: 2 variants: - - name: NONE + - name: NoClock description: No clock selected value: 0 - name: LSE @@ -3174,7 +3174,7 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 2 - - name: PLL1R + - name: PLL1_R description: PLL pll1_r_ck selected as system clock value: 3 enum/SYSTICKSEL: diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index b0f07d2..f311360 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -735,6 +735,7 @@ fieldset/BDCR: description: RTC clock source selection bit_offset: 8 bit_size: 2 + enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 15 @@ -1635,3 +1636,18 @@ fieldset/SMPSCR: description: Step Down converter clock switch status bit_offset: 8 bit_size: 2 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index fd8006e..5acb71c 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -685,6 +685,7 @@ fieldset/BDCR: description: RTC clock source selection bit_offset: 8 bit_size: 2 + enum: RTCSEL - name: LSESYSRDY description: LSE system clock ready bit_offset: 11 @@ -1434,3 +1435,18 @@ enum/ADCSEL: - name: SYSCLK description: SYSCLK used as ADC clock source value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index bbe6b99..ffdd52e 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -621,6 +621,7 @@ fieldset/BDCR: description: RTC clock source selection bit_offset: 8 bit_size: 2 + enum: RTCSEL - name: LSESYSRDY description: LSE system clock ready bit_offset: 11 @@ -1056,3 +1057,18 @@ enum/ADCSEL: - name: SYSCLK description: SYSCLK used as ADC clock source value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3