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Merge pull request #105 from embassy-rs/cleanups

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Expanded RCC, cleanups
This commit is contained in:
Dario Nieuwenhuis 2021-11-29 17:08:13 +01:00 committed by GitHub
commit 8f150ead7f
3 changed files with 560 additions and 258 deletions
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445
data/registers/rcc_f3.yaml
View File

@ -61,6 +61,10 @@ fieldset/AHBENR:
description: DMA1 clock enable
bit_offset: 0
bit_size: 1
- name: DMA2EN
description: DMA2 clock enable
bit_offset: 1
bit_size: 1
- name: SRAMEN
description: SRAM interface clock enable
bit_offset: 2
@ -69,10 +73,18 @@ fieldset/AHBENR:
description: FLITF clock enable
bit_offset: 4
bit_size: 1
- name: FMCEN
description: FMC clock enable
bit_offset: 5
bit_size: 1
- name: CRCEN
description: CRC clock enable
bit_offset: 6
bit_size: 1
- name: GPIOHEN
description: IO port H clock enable
bit_offset: 16
bit_size: 1
- name: GPIOAEN
description: I/O port A clock enable
bit_offset: 17
@ -89,14 +101,26 @@ fieldset/AHBENR:
description: I/O port D clock enable
bit_offset: 20
bit_size: 1
- name: GPIOEEN
description: I/O port E clock enable
bit_offset: 21
bit_size: 1
- name: GPIOFEN
description: I/O port F clock enable
bit_offset: 22
bit_size: 1
- name: GPIOGEN
description: IO port G clock enable
bit_offset: 23
bit_size: 1
- name: TSCEN
description: Touch sensing controller clock enable
bit_offset: 24
bit_size: 1
- name: ADC1EN
description: ADC 1
bit_offset: 28
bit_size: 1
- name: ADC12EN
description: ADC1 and ADC2 clock enable
bit_offset: 28
@ -108,6 +132,14 @@ fieldset/AHBENR:
fieldset/AHBRSTR:
description: AHB peripheral reset register
fields:
- name: FMCRST
description: FMC reset
bit_offset: 5
bit_size: 1
- name: GPIOHRST
description: IO port H reset
bit_offset: 16
bit_size: 1
- name: GPIOARST
description: I/O port A reset
bit_offset: 17
@ -124,18 +156,34 @@ fieldset/AHBRSTR:
description: I/O port D reset
bit_offset: 20
bit_size: 1
- name: GPIOERST
description: I/O port E reset
bit_offset: 21
bit_size: 1
- name: GPIOFRST
description: I/O port F reset
bit_offset: 22
bit_size: 1
- name: GPIOGRST
description: IO port G reset
bit_offset: 23
bit_size: 1
- name: TSCRST
description: Touch sensing controller reset
bit_offset: 24
bit_size: 1
- name: ADC1RST
description: ADC1 reset
bit_offset: 28
bit_size: 1
- name: ADC12RST
description: ADC1 and ADC2 reset
bit_offset: 28
bit_size: 1
- name: ADC34RST
description: ADC3 and ADC4 reset
bit_offset: 29
bit_size: 1
fieldset/APB1ENR:
description: APB1 peripheral clock enable register (RCC_APB1ENR)
fields:
@ -147,6 +195,14 @@ fieldset/APB1ENR:
description: Timer 3 clock enable
bit_offset: 1
bit_size: 1
- name: TIM4EN
description: Timer 4 clock enable
bit_offset: 2
bit_size: 1
- name: TIM5EN
description: Timer 5 clock enable
bit_offset: 3
bit_size: 1
- name: TIM6EN
description: Timer 6 clock enable
bit_offset: 4
@ -155,22 +211,62 @@ fieldset/APB1ENR:
description: Timer 7 clock enable
bit_offset: 5
bit_size: 1
- name: TIM12EN
description: Timer 12 clock enable
bit_offset: 6
bit_size: 1
- name: TIM13EN
description: Timer 13 clock enable
bit_offset: 7
bit_size: 1
- name: TIM14EN
description: Timer 14 clock enable
bit_offset: 8
bit_size: 1
- name: TIM18EN
description: Timer 18 clock enable
bit_offset: 9
bit_size: 1
- name: WWDGEN
description: Window watchdog clock enable
bit_offset: 11
bit_size: 1
- name: SPI2EN
description: SPI 2 clock enable
bit_offset: 14
bit_size: 1
- name: SPI3EN
description: SPI 3 clock enable
bit_offset: 15
bit_size: 1
- name: USART2EN
description: USART 2 clock enable
bit_offset: 17
bit_size: 1
- name: USART3EN
description: USART3 clock enable
description: USART 3 clock enable
bit_offset: 18
bit_size: 1
- name: UART4EN
description: UART4 clock enable
bit_offset: 19
bit_size: 1
- name: UART5EN
description: UART5 clock enable
bit_offset: 20
bit_size: 1
- name: I2C1EN
description: I2C 1 clock enable
bit_offset: 21
bit_size: 1
- name: I2C2EN
description: I2C 2 clock enable
bit_offset: 22
bit_size: 1
- name: USBEN
description: USB clock enable
bit_offset: 23
bit_size: 1
- name: CANEN
description: CAN clock enable
bit_offset: 25
@ -187,6 +283,14 @@ fieldset/APB1ENR:
description: DAC interface clock enable
bit_offset: 29
bit_size: 1
- name: I2C3EN
description: I2C3 clock enable
bit_offset: 30
bit_size: 1
- name: CECEN
description: HDMI CEC interface clock enable
bit_offset: 30
bit_size: 1
fieldset/APB1RSTR:
description: APB1 peripheral reset register (RCC_APB1RSTR)
fields:
@ -198,6 +302,14 @@ fieldset/APB1RSTR:
description: Timer 3 reset
bit_offset: 1
bit_size: 1
- name: TIM4RST
description: Timer 14 reset
bit_offset: 2
bit_size: 1
- name: TIM5RST
description: Timer 5 reset
bit_offset: 3
bit_size: 1
- name: TIM6RST
description: Timer 6 reset
bit_offset: 4
@ -206,10 +318,34 @@ fieldset/APB1RSTR:
description: Timer 7 reset
bit_offset: 5
bit_size: 1
- name: TIM12RST
description: Timer 12 reset
bit_offset: 6
bit_size: 1
- name: TIM13RST
description: Timer 13 reset
bit_offset: 7
bit_size: 1
- name: TIM14RST
description: Timer 14 reset
bit_offset: 8
bit_size: 1
- name: TIM18RST
description: Timer 18 reset
bit_offset: 9
bit_size: 1
- name: WWDGRST
description: Window watchdog reset
bit_offset: 11
bit_size: 1
- name: SPI2RST
description: SPI2 reset
bit_offset: 14
bit_size: 1
- name: SPI3RST
description: SPI3 reset
bit_offset: 15
bit_size: 1
- name: USART2RST
description: USART 2 reset
bit_offset: 17
@ -218,10 +354,26 @@ fieldset/APB1RSTR:
description: USART3 reset
bit_offset: 18
bit_size: 1
- name: UART4RST
description: UART 4 reset
bit_offset: 19
bit_size: 1
- name: UART5RST
description: UART 5 reset
bit_offset: 20
bit_size: 1
- name: I2C1RST
description: I2C1 reset
bit_offset: 21
bit_size: 1
- name: I2C2RST
description: I2C2 reset
bit_offset: 22
bit_size: 1
- name: USBRST
description: USB reset
bit_offset: 23
bit_size: 1
- name: CANRST
description: CAN reset
bit_offset: 25
@ -238,6 +390,14 @@ fieldset/APB1RSTR:
description: DAC interface reset
bit_offset: 29
bit_size: 1
- name: I2C3RST
description: I2C3 reset
bit_offset: 30
bit_size: 1
- name: CECRST
description: HDMI CEC reset
bit_offset: 30
bit_size: 1
fieldset/APB2ENR:
description: APB2 peripheral clock enable register (RCC_APB2ENR)
fields:
@ -245,6 +405,10 @@ fieldset/APB2ENR:
description: SYSCFG clock enable
bit_offset: 0
bit_size: 1
- name: ADCEN
description: ADC 1 interface clock enable
bit_offset: 9
bit_size: 1
- name: TIM1EN
description: TIM1 Timer clock enable
bit_offset: 11
@ -253,10 +417,18 @@ fieldset/APB2ENR:
description: SPI 1 clock enable
bit_offset: 12
bit_size: 1
- name: TIM8EN
description: TIM8 Timer clock enable
bit_offset: 13
bit_size: 1
- name: USART1EN
description: USART1 clock enable
bit_offset: 14
bit_size: 1
- name: SPI4EN
description: SPI4 clock enable
bit_offset: 15
bit_size: 1
- name: TIM15EN
description: TIM15 timer clock enable
bit_offset: 16
@ -269,6 +441,30 @@ fieldset/APB2ENR:
description: TIM17 timer clock enable
bit_offset: 18
bit_size: 1
- name: TIM19EN
description: TIM19 timer clock enable
bit_offset: 19
bit_size: 1
- name: TIM20EN
description: TIM20 timer clock enable
bit_offset: 20
bit_size: 1
- name: DBGMCUEN
description: MCU debug module clock enable
bit_offset: 22
bit_size: 1
- name: SDADC1EN
description: SDADC1 (Sigma Delta ADC 1) clock enable
bit_offset: 24
bit_size: 1
- name: SDADC2EN
description: SDADC2 (Sigma Delta ADC 2) clock enable
bit_offset: 25
bit_size: 1
- name: SDADC3EN
description: SDADC3 (Sigma Delta ADC 3) clock enable
bit_offset: 26
bit_size: 1
- name: HRTIM1EN
description: High Resolution Timer 1 clock enable
bit_offset: 29
@ -280,6 +476,10 @@ fieldset/APB2RSTR:
description: SYSCFG and COMP reset
bit_offset: 0
bit_size: 1
- name: ADCRST
description: ADC interface reset
bit_offset: 9
bit_size: 1
- name: TIM1RST
description: TIM1 timer reset
bit_offset: 11
@ -288,10 +488,18 @@ fieldset/APB2RSTR:
description: SPI 1 reset
bit_offset: 12
bit_size: 1
- name: TIM8RST
description: TIM8 timer reset
bit_offset: 13
bit_size: 1
- name: USART1RST
description: USART1 reset
bit_offset: 14
bit_size: 1
- name: SPI4RST
description: SPI4 reset
bit_offset: 15
bit_size: 1
- name: TIM15RST
description: TIM15 timer reset
bit_offset: 16
@ -304,6 +512,26 @@ fieldset/APB2RSTR:
description: TIM17 timer reset
bit_offset: 18
bit_size: 1
- name: TIM19RST
description: TIM19 timer reset
bit_offset: 19
bit_size: 1
- name: TIM20RST
description: TIM20 timer reset
bit_offset: 20
bit_size: 1
- name: SDADC1RST
description: SDADC1 (Sigma delta ADC 1) reset
bit_offset: 24
bit_size: 1
- name: SDADC2RST
description: SDADC2 (Sigma delta ADC 2) reset
bit_offset: 25
bit_size: 1
- name: SDADC3RST
description: SDADC3 (Sigma delta ADC 3) reset
bit_offset: 26
bit_size: 1
- name: HRTIM1RST
description: High Resolution Timer1 reset
bit_offset: 29
@ -371,6 +599,16 @@ fieldset/CFGR:
bit_offset: 11
bit_size: 3
enum: PPRE
- name: ADCPRE
description: ADC prescaler
bit_offset: 14
bit_size: 2
enum: ADCPRE
- name: PLLSRC
description: PLL entry clock source
bit_offset: 15
bit_size: 2
enum: PLLSRC
- name: PLLSRC
description: PLL entry clock source
bit_offset: 16
@ -386,11 +624,26 @@ fieldset/CFGR:
bit_offset: 18
bit_size: 4
enum: PLLMUL
- name: USBPRE
description: USB prescaler
bit_offset: 22
bit_size: 1
enum: USBPRE
- name: I2SSRC
description: I2S external clock source selection
bit_offset: 23
bit_size: 1
enum: ISSRC
- name: MCO
description: Microcontroller clock output
bit_offset: 24
bit_size: 3
enum: MCO
- name: SDPRE
description: SDADC prescaler
bit_offset: 27
bit_size: 5
enum: SDPRE
- name: MCOPRE
description: Microcontroller Clock Output Prescaler
bit_offset: 28
@ -409,11 +662,21 @@ fieldset/CFGR2:
bit_offset: 0
bit_size: 4
enum: PREDIV
- name: ADC1PRES
description: ADC1 prescaler
bit_offset: 4
bit_size: 5
enum: ADCPRES
- name: ADC12PRES
description: ADC1 and ADC2 prescaler
bit_offset: 4
bit_size: 5
enum: ADCPRES
- name: ADC34PRES
description: ADC3 and ADC4 prescaler
bit_offset: 9
bit_size: 5
enum: ADCPRES
fieldset/CFGR3:
description: Clock configuration register 3
fields:
@ -427,11 +690,81 @@ fieldset/CFGR3:
bit_offset: 4
bit_size: 1
enum: ICSW
- name: I2C2SW
description: I2C2 clock source selection
bit_offset: 5
bit_size: 1
enum: ICSW
- name: I2C3SW
description: I2C3 clock source selection
bit_offset: 6
bit_size: 1
enum: ICSW
- name: CECSW
description: HDMI CEC clock source selection
bit_offset: 6
bit_size: 1
enum: CECSW
- name: TIM1SW
description: Timer1 clock source selection
bit_offset: 8
bit_size: 1
enum: TIMSW
- name: TIM8SW
description: Timer8 clock source selection
bit_offset: 9
bit_size: 1
enum: TIMSW
- name: TIM15SW
description: Timer15 clock source selection
bit_offset: 10
bit_size: 1
enum: TIMSW
- name: TIM16SW
description: Timer16 clock source selection
bit_offset: 11
bit_size: 1
enum: TIMSW
- name: TIM17SW
description: Timer17 clock source selection
bit_offset: 13
bit_size: 1
enum: TIMSW
- name: TIM20SW
description: Timer20 clock source selection
bit_offset: 15
bit_size: 1
enum: TIMSW
- name: USART2SW
description: USART2 clock source selection
bit_offset: 16
bit_size: 2
enum: USARTSW
- name: USART3SW
description: USART3 clock source selection
bit_offset: 18
bit_size: 2
enum: USARTSW
- name: UART4SW
description: UART4 clock source selection
bit_offset: 20
bit_size: 2
enum: USARTSW
- name: UART5SW
description: UART5 clock source selection
bit_offset: 22
bit_size: 2
enum: USARTSW
- name: TIM2SW
description: Timer2 clock source selection
bit_offset: 24
bit_size: 1
enum: TIMSW
- name: TIM34SW
description: Timer34 clock source selection
bit_offset: 25
bit_size: 1
enum: TIMSW
fieldset/CIR:
description: Clock interrupt register (RCC_CIR)
fields:
@ -583,7 +916,6 @@ fieldset/CSR:
description: Reset flag of the 1.8 V domain
bit_offset: 23
bit_size: 1
enum_read: OBLRSTFR
- name: RMVF
description: Remove reset flag
bit_offset: 24
@ -593,37 +925,45 @@ fieldset/CSR:
description: Option byte loader reset flag
bit_offset: 25
bit_size: 1
enum_read: OBLRSTFR
- name: PINRSTF
description: PIN reset flag
bit_offset: 26
bit_size: 1
enum_read: OBLRSTFR
- name: PORRSTF
description: POR/PDR reset flag
bit_offset: 27
bit_size: 1
enum_read: OBLRSTFR
- name: SFTRSTF
description: Software reset flag
bit_offset: 28
bit_size: 1
enum_read: OBLRSTFR
- name: IWDGRSTF
description: Independent watchdog reset flag
bit_offset: 29
bit_size: 1
enum_read: OBLRSTFR
- name: WWDGRSTF
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
enum_read: OBLRSTFR
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1
enum_read: OBLRSTFR
enum/ADCPRE:
bit_size: 2
variants:
- name: Div2
description: PCLK divided by 2
value: 0
- name: Div4
description: PCLK divided by 4
value: 1
- name: Div6
description: PCLK divided by 6
value: 2
- name: Div8
description: PCLK divided by 8
value: 3
enum/ADCPRES:
bit_size: 5
variants:
@ -666,6 +1006,15 @@ enum/ADCPRES:
- name: Div256
description: PLL clock divided by 256
value: 27
enum/CECSW:
bit_size: 1
variants:
- name: HSI_Div244
description: HSI clock divided by 244 selected as CEC clock source
value: 0
- name: LSE
description: LSE clock selected as CEC clock source
value: 1
enum/CSSCW:
bit_size: 1
variants:
@ -738,6 +1087,15 @@ enum/ICSW:
- name: SYSCLK
description: SYSCLK clock selected as I2C clock source
value: 1
enum/ISSRC:
bit_size: 1
variants:
- name: SYSCLK
description: System clock used as I2S clock source
value: 0
- name: CKIN
description: External clock mapped on the I2S_CKIN pin used as I2S clock source
value: 1
enum/LSEBYP:
bit_size: 1
variants:
@ -855,15 +1213,6 @@ enum/MCOPRE:
- name: Div128
description: MCO is divided by 128
value: 7
enum/OBLRSTFR:
bit_size: 1
variants:
- name: NoReset
description: No reset has occured
value: 0
- name: Reset
description: A reset has occured
value: 1
enum/PLLMUL:
bit_size: 4
variants:
@ -1032,6 +1381,57 @@ enum/RTCSEL:
- name: HSE
description: HSE oscillator clock divided by a prescaler used as RTC clock
value: 3
enum/SDPRE:
bit_size: 5
variants:
- name: Div2
description: SYSCLK divided by 2
value: 0
- name: Div4
description: SYSCLK divided by 4
value: 17
- name: Div6
description: SYSCLK divided by 6
value: 18
- name: Div8
description: SYSCLK divided by 8
value: 19
- name: Div10
description: SYSCLK divided by 10
value: 20
- name: Div12
description: SYSCLK divided by 12
value: 21
- name: Div14
description: SYSCLK divided by 14
value: 22
- name: Div16
description: SYSCLK divided by 16
value: 23
- name: Div20
description: SYSCLK divided by 20
value: 24
- name: Div24
description: SYSCLK divided by 24
value: 25
- name: Div28
description: SYSCLK divided by 28
value: 26
- name: Div32
description: SYSCLK divided by 32
value: 27
- name: Div36
description: SYSCLK divided by 36
value: 28
- name: Div40
description: SYSCLK divided by 40
value: 29
- name: Div44
description: SYSCLK divided by 44
value: 30
- name: Div48
description: SYSCLK divided by 48
value: 31
enum/SW:
bit_size: 2
variants:
@ -1080,3 +1480,12 @@ enum/USARTSW:
- name: HSI
description: HSI selected as USART clock source
value: 3
enum/USBPRE:
bit_size: 1
variants:
- name: DIV1_5
description: PLL clock is divided by 1.5
value: 0
- name: DIV1
description: PLL clock is not divided
value: 1

2
data/registers/rcc_l5.yaml
View File

@ -633,7 +633,7 @@ fieldset/APB1ENR1:
description: SPI2 clock enable
bit_offset: 14
bit_size: 1
- name: SP3EN
- name: SPI3EN
description: SPI3 clock enable
bit_offset: 15
bit_size: 1

371
stm32data/__main__.py
View File

@ -51,6 +51,9 @@ FAKE_PERIPHERALS = [
'GPIO',
'DMA',
# IRTIM is just TIM16+TIM17
'IRTIM',
# I2S is just SPI on disguise
'I2S1',
'I2S2',
@ -61,11 +64,13 @@ FAKE_PERIPHERALS = [
'I2S7',
'I2S8',
# We add this as ghost peri
'SYS',
# These are software libraries
'FREERTOS',
'PDM2PCM',
'FATFS',
# 'CRC',
'LIBJPEG',
'MBEDTLS',
'LWIP',
@ -73,6 +78,7 @@ FAKE_PERIPHERALS = [
'USB_DEVICE',
'GUI_INTERFACE',
'TRACER_EMB',
'TOUCHSENSING',
]
perimap = [
@ -118,19 +124,19 @@ perimap = [
('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
('.*:DCMI:cci_v2_0', 'dcmi_v1/DCMI'),
('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'),
('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
('STM32F7.*:SYS:.*', 'syscfg_f7/SYSCFG'),
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
('STM32L1.*:SYS:.*', 'syscfg_l1/SYSCFG'),
('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
('STM32G4.*:SYS:.*', 'syscfg_g4/SYSCFG'),
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
('STM32U5.*:SYS:.*', 'syscfg_u5/SYSCFG'),
('STM32WB.*:SYS:.*', 'syscfg_wb/SYSCFG'),
('STM32WL5.*:SYS:.*', 'syscfg_wl5/SYSCFG'),
('STM32WLE.*:SYS:.*', 'syscfg_wle/SYSCFG'),
('STM32F0.*:SYSCFG:.*', 'syscfg_f0/SYSCFG'),
('STM32F4.*:SYSCFG:.*', 'syscfg_f4/SYSCFG'),
('STM32F7.*:SYSCFG:.*', 'syscfg_f7/SYSCFG'),
('STM32L4.*:SYSCFG:.*', 'syscfg_l4/SYSCFG'),
('STM32L0.*:SYSCFG:.*', 'syscfg_l0/SYSCFG'),
('STM32L1.*:SYSCFG:.*', 'syscfg_l1/SYSCFG'),
('STM32G0.*:SYSCFG:.*', 'syscfg_g0/SYSCFG'),
('STM32G4.*:SYSCFG:.*', 'syscfg_g4/SYSCFG'),
('STM32H7.*:SYSCFG:.*', 'syscfg_h7/SYSCFG'),
('STM32U5.*:SYSCFG:.*', 'syscfg_u5/SYSCFG'),
('STM32WB.*:SYSCFG:.*', 'syscfg_wb/SYSCFG'),
('STM32WL5.*:SYSCFG:.*', 'syscfg_wl5/SYSCFG'),
('STM32WLE.*:SYSCFG:.*', 'syscfg_wle/SYSCFG'),
('.*:IWDG:iwdg1_v2_0', 'iwdg_v2/IWDG'),
('.*:WWDG:wwdg1_v1_0', 'wwdg_v1/WWDG'),
@ -178,24 +184,24 @@ perimap = [
('STM32WLE.*:EXTI:.*', 'exti_wle/EXTI'),
('.*:EXTI:.*', 'exti_v1/EXTI'),
('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
('STM32L0.*:CRS:.*', 'crs_l0/CRS'),
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
('.*:STM32G0_pwr_v1_0', 'pwr_g0/PWR'),
('.*:STM32G4_pwr_v1_0', 'pwr_g4/PWR'),
('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'),
('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),
('.*:STM32F7_pwr_v1_0', 'pwr_f7/PWR'),
('.*:STM32L1_pwr_v1_0', 'pwr_l1/PWR'),
('.*:STM32U5_pwr_v1_0', 'pwr_u5/PWR'),
('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'),
('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'),
('.*:STM32F1_flash_v1_0', 'flash_f1/FLASH'),
('.*:STM32F4_flash_v1_0', 'flash_f4/FLASH'),
('.*:STM32F7_flash_v1_0', 'flash_f7/FLASH'),
('.*:STM32L4_flash_v1_0', 'flash_l4/FLASH'),
('.*:STM32U5_flash_v1_0', 'flash_u5/FLASH'),
('STM32G0.*:PWR:.*', 'pwr_g0/PWR'),
('STM32G4.*:PWR:.*', 'pwr_g4/PWR'),
('STM32H7(42|43|53|50).*:PWR:.*', 'pwr_h7/PWR'),
('STM32H7.*:PWR:.*', 'pwr_h7smps/PWR'),
('STM32F4.*:PWR:.*', 'pwr_f4/PWR'),
('STM32F7.*:PWR:.*', 'pwr_f7/PWR'),
('STM32L1.*:PWR:.*', 'pwr_l1/PWR'),
('STM32U5.*:PWR:.*', 'pwr_u5/PWR'),
('STM32WL.*:PWR:.*', 'pwr_wl5/PWR'),
('STM32H7.*:FLASH:.*', 'flash_h7/FLASH'),
('STM32F0.*:FLASH:.*', 'flash_f0/FLASH'),
('STM32F1.*:FLASH:.*', 'flash_f1/FLASH'),
('STM32F4.*:FLASH:.*', 'flash_f4/FLASH'),
('STM32F7.*:FLASH:.*', 'flash_f7/FLASH'),
('STM32L4.*:FLASH:.*', 'flash_l4/FLASH'),
('STM32U5.*:FLASH:.*', 'flash_u5/FLASH'),
('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'),
('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'),
@ -205,35 +211,38 @@ perimap = [
('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'),
('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),
('.*:STM32F0_dbgmcu_v1_0', 'dbgmcu_f0/DBGMCU'),
('.*:STM32F1_dbgmcu_v1_0', 'dbgmcu_f1/DBGMCU'),
('.*:STM32F2_dbgmcu_v1_0', 'dbgmcu_f2/DBGMCU'),
('.*:STM32F3_dbgmcu_v1_0', 'dbgmcu_f3/DBGMCU'),
('.*:STM32F4_dbgmcu_v1_0', 'dbgmcu_f4/DBGMCU'),
('.*:STM32F7_dbgmcu_v1_0', 'dbgmcu_f7/DBGMCU'),
('.*:STM32G0_dbgmcu_v1_0', 'dbgmcu_g0/DBGMCU'),
('.*:STM32G4_dbgmcu_v1_0', 'dbgmcu_g4/DBGMCU'),
('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'),
('.*:STM32L0_dbgmcu_v1_0', 'dbgmcu_l0/DBGMCU'),
('.*:STM32L1_dbgmcu_v1_0', 'dbgmcu_l1/DBGMCU'),
('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'),
('.*:STM32U5_dbgmcu_v1_0', 'dbgmcu_u5/DBGMCU'),
('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'),
('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'),
('STM32F0.*:DBGMCU:.*', 'dbgmcu_f0/DBGMCU'),
('STM32F1.*:DBGMCU:.*', 'dbgmcu_f1/DBGMCU'),
('STM32F2.*:DBGMCU:.*', 'dbgmcu_f2/DBGMCU'),
('STM32F3.*:DBGMCU:.*', 'dbgmcu_f3/DBGMCU'),
('STM32F4.*:DBGMCU:.*', 'dbgmcu_f4/DBGMCU'),
('STM32F7.*:DBGMCU:.*', 'dbgmcu_f7/DBGMCU'),
('STM32G0.*:DBGMCU:.*', 'dbgmcu_g0/DBGMCU'),
('STM32G4.*:DBGMCU:.*', 'dbgmcu_g4/DBGMCU'),
('STM32H7.*:DBGMCU:.*', 'dbgmcu_h7/DBGMCU'),
('STM32L0.*:DBGMCU:.*', 'dbgmcu_l0/DBGMCU'),
('STM32L1.*:DBGMCU:.*', 'dbgmcu_l1/DBGMCU'),
('STM32L4.*:DBGMCU:.*', 'dbgmcu_l4/DBGMCU'),
('STM32U5.*:DBGMCU:.*', 'dbgmcu_u5/DBGMCU'),
('STM32WB.*:DBGMCU:.*', 'dbgmcu_wb/DBGMCU'),
('STM32WL.*:DBGMCU:.*', 'dbgmcu_wl/DBGMCU'),
('STM32F1.*:GPIO.*', 'gpio_v1/GPIO'),
('.*:GPIO.*', 'gpio_v2/GPIO'),
('.*:IPCC:v1_0', 'ipcc_v1/IPCC'),
('.*:DMAMUX:v1', 'dmamux_v1/DMAMUX'),
('.*:DMAMUX.*', 'dmamux_v1/DMAMUX'),
('.*:BDMA:DMA', 'bdma_v1/DMA'),
('.*:BDMA:.*', 'bdma_v1/DMA'),
('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', 'dma2d_v2/DMA2D'),
('.*:DMA2D:dma2d1_v1_0', 'dma2d_v1/DMA2D'),
('STM32L4[PQRS].*:.*:DMA', 'bdma_v1/DMA'), # L4+
('STM32L[04].*:.*:DMA', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above)
('STM32F030.C.*:.*:DMA', 'bdma_v2/DMA'), # Weird F0
('STM32F09.*:.*:DMA', 'bdma_v2/DMA'), # Weird F0
('STM32F[247].*:.*:DMA', 'dma_v2/DMA'),
('STM32H7.*:.*:DMA', 'dma_v1/DMA'),
('.*:DMA', 'bdma_v1/DMA'),
('STM32L4[PQRS].*:DMA.*', 'bdma_v1/DMA'), # L4+
('STM32L[04].*:DMA.*', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above)
('STM32F030.C.*:DMA.*', 'bdma_v2/DMA'), # Weird F0
('STM32F09.*:DMA.*', 'bdma_v2/DMA'), # Weird F0
('STM32F[247].*:DMA.*', 'dma_v2/DMA'),
('STM32H7.*:DMA.*', 'dma_v1/DMA'),
('.*:DMA.*', 'bdma_v1/DMA'),
('.*:CAN:bxcan1_v1_1.*', 'can_bxcan/CAN'),
# stm32F4 CRC peripheral
@ -245,9 +254,26 @@ perimap = [
('STM32L[04].*:CRC:integtest1_v2_0', 'crc_v3/CRC'),
('.*:CRC:integtest1_v2_0', 'crc_v2/CRC'),
('.*:CRC:integtest1_v2_2', 'crc_v3/CRC'),
]
peri_rename = {
'HDMI_CEC': 'CEC',
'SUBGHZ': 'SUBGHZSPI',
}
ghost_peris = [
'GPIOA', 'GPIOB', 'GPIOC', 'GPIOD', 'GPIOE', 'GPIOF', 'GPIOG', 'GPIOH', 'GPIOI', 'GPIOJ', 'GPIOK', 'GPIOL', 'GPIOM', 'GPION', 'GPIOO', 'GPIOP', 'GPIOQ', 'GPIOR', 'GPIOS', 'GPIOT',
'DMA1', 'DMA2', 'BDMA', 'DMAMUX', 'DMAMUX1', 'DMAMUX2',
'SYSCFG', 'EXTI', 'FLASH', 'DBGMCU', 'CRS', 'PWR', 'AFIO',
]
alt_peri_defines = {
'DBGMCU': ['DBGMCU_BASE', 'DBG_BASE'],
'FLASH': ['FLASH_R_BASE'],
'ADC_COMMON': ['ADC_COMMON', 'ADC1_COMMON', 'ADC12_COMMON', 'ADC123_COMMON'],
'CAN': ['CAN_BASE', 'CAN1_BASE'],
}
# Device address overrides, in case of missing from headers
address_overrides = {
'STM32F412VE:GPIOF_BASE': 0x40021400,
@ -424,6 +450,12 @@ def parse_pin_name(pin_name):
return port, pin
def get_peri_addr(defines, pname):
possible_defines = alt_peri_defines.get(pname) or [f'{pname}_BASE', pname]
for d in possible_defines:
if addr := defines.get(d):
return addr
return None
def parse_chips():
os.makedirs('data/chips', exist_ok=True)
@ -445,6 +477,8 @@ def parse_chips():
for f in sorted(glob('sources/cubedb/mcu/STM32*.xml')):
if 'STM32MP' in f:
continue
if 'STM32GBK' in f:
continue
print(f)
@ -522,9 +556,10 @@ def parse_chips():
if chip_bdma is not None:
chip_bdma = chip_bdma['@Version']
rcc = next(filter(lambda x: x['@Name'] == 'RCC', chip['ips'].values()))['@Version']
rcc = removesuffix(rcc, '-rcc_v1_0')
rcc = removesuffix(rcc, '_rcc_v1_0')
rcc_kind = next(filter(lambda x: x['@Name'] == 'RCC', chip['ips'].values()))['@Version']
assert rcc_kind is not None
rcc_block = match_peri(f'{chip_name}:RCC:{rcc_kind}')
assert rcc_block is not None
h = header.get_for_chip(chip_name)
if h is None:
@ -579,41 +614,34 @@ def parse_chips():
pkind = ip['@Name'] + ':' + ip['@Version']
pkind = removesuffix(pkind, '_Cube')
if pname == 'SYS':
pname = 'SYSCFG'
if pname == 'SUBGHZ':
pname = 'SUBGHZSPI'
if pname == 'SYSCFG_VREFBUF':
pname = 'SYSCFG'
if pname in FAKE_PERIPHERALS:
continue
if rename := peri_rename.get(pname):
pname = rename
if pname.startswith('ADC'):
if not 'ADC_COMMON' in peri_kinds:
peri_kinds['ADC_COMMON'] = 'ADC_COMMON:' + removesuffix(ip['@Version'], '_Cube')
peri_kinds[pname] = pkind
for pname in ghost_peris:
if pname not in peri_kinds and (addr := get_peri_addr(defines, pname)):
peri_kinds[pname] = 'unknown'
peris = {}
for pname, pkind in peri_kinds.items():
addr = defines.get(pname)
if addr is None:
if pname == 'ADC_COMMON':
addr = defines.get('ADC1_COMMON')
if addr is None:
addr = defines.get('ADC12_COMMON')
if addr is None:
addr = defines.get('ADC123_COMMON')
addr = get_peri_addr(defines, pname)
if addr is None:
continue
p = OrderedDict({
'address': addr,
'kind': pkind,
})
if pname in clocks[rcc]:
p['clock'] = clocks[rcc][pname]
if rcc_info := match_peri_clock(rcc_block, pname):
p['rcc'] = rcc_info
if block := match_peri(chip_name + ':' + pname + ':' + pkind):
p['block'] = block
@ -637,132 +665,8 @@ def parse_chips():
for (extra_name, extra_p) in extra['peripherals'].items():
peris[extra_name] = extra_p
# Handle GPIO specially.
for p in range(20):
port = 'GPIO' + chr(ord('A') + p)
if addr := lookup_address(defines, chip_name, port + '_BASE'):
block = 'gpio_v2/GPIO'
if chip['family'] == 'STM32F1':
block = 'gpio_v1/GPIO'
p = OrderedDict({
'address': addr,
'block': block,
})
peris[port] = p
# Handle DMA specially.
for dma in ('DMA1', 'DMA2', 'BDMA'):
if addr := defines.get(dma + '_BASE'):
p = OrderedDict({
'address': addr,
})
if block := match_peri(chip_name + ':' + dma + ':DMA'):
p['block'] = block
if chip_nvic in chip_interrupts:
if dma in chip_interrupts[chip_nvic]:
# filter by available, because some are conditioned on <Die>
p['interrupts'] = filter_interrupts(chip_interrupts[chip_nvic][dma], interrupts)
peris[dma] = p
# DMAMUX is not in the cubedb XMLs
for dma in ('DMAMUX', 'DMAMUX1', "DMAMUX2"):
if addr := defines.get(dma + '_BASE'):
kind = 'DMAMUX:v1'
dbg_peri = OrderedDict({
'address': addr,
'kind': kind,
})
if block := match_peri(chip_name + ':' + dma + ':' + kind):
dbg_peri['block'] = block
peris[dma] = dbg_peri
# EXTI is not in the cubedb XMLs
if addr := defines.get('EXTI_BASE'):
peri = OrderedDict({
'address': addr,
'kind': 'EXTI',
})
if block := match_peri(chip_name + ':EXTI:EXTI:v1'):
peri['block'] = block
peris['EXTI'] = peri
# FLASH is not in the cubedb XMLs
if addr := defines.get('FLASH_R_BASE'):
kind = 'FLASH:' + chip_name[:7] + '_flash_v1_0'
flash_peri = OrderedDict({
'address': addr,
'kind': kind,
})
if block := match_peri(kind):
flash_peri['block'] = block
peris['FLASH'] = flash_peri
# DBGMCU is not in the cubedb XMLs
if addr := defines.get('DBGMCU_BASE') or defines.get('DBG_BASE'):
kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0'
dbg_peri = OrderedDict({
'address': addr,
'kind': kind,
})
if block := match_peri(kind):
dbg_peri['block'] = block
peris['DBGMCU'] = dbg_peri
# CRS is not in the cubedb XMLs
if addr := defines.get('CRS_BASE'):
kind = 'CRS:' + chip_name[:7] + '_crs_v1_0'
crs_peri = OrderedDict({
'address': addr,
'kind': kind,
})
if block := match_peri(kind):
crs_peri['block'] = block
peris['CRS'] = crs_peri
# PWR is not in some XMLs
if 'PWR' not in peris:
if addr := defines.get('PWR_BASE'):
kind = 'PWR:' + chip_name[:7] + '_pwr_v1_0'
pwr_peri = OrderedDict({
'address': addr,
'kind': kind,
})
if block := match_peri(kind):
pwr_peri['block'] = block
peris['PWR'] = pwr_peri
# AFIO is not in the cubedb XMLs
if addr := defines.get('AFIO_BASE'):
kind = 'AFIO'
afio_peri = OrderedDict({
'address': addr,
'kind': kind,
})
if block := match_peri(chip_name[:7] + ':' + kind + ':'):
afio_peri['block'] = block
peris['AFIO'] = afio_peri
core['peripherals'] = peris
if 'block' in core['peripherals']['RCC']:
rcc_block = core['peripherals']['RCC']['block']
for (name, body) in core['peripherals'].items():
if 'clock' not in body:
peri_clock = None
if chip_name.startswith('STM32G0') and name.startswith('TIM'):
peri_clock = 'APB'
elif chip_name.startswith('STM32G0') and name.startswith('SYSCFG'):
peri_clock = 'APB'
else:
peri_clock = match_peri_clock(rcc_block, name)
if peri_clock is not None:
core['peripherals'][name]['clock'] = peri_clock
# Process DMA channels
chs = {}
if chip_dma in dma_channels:
@ -1009,7 +913,7 @@ def parse_dma():
dmamux_file = 'L4PQ'
if ff.startswith('STM32L4S'):
dmamux_file = 'L4RS'
for mf in glob('data/dmamux/{}_*.yaml'.format(dmamux_file)):
for mf in sorted(glob('data/dmamux/{}_*.yaml'.format(dmamux_file))):
with open(mf, 'r') as yaml_file:
y = yaml.load(yaml_file)
mf = removesuffix(mf, '.yaml')
@ -1120,28 +1024,6 @@ def parse_dma():
dma_channels[ff] = chip_dma
clocks = {}
def parse_clocks():
for f in glob('sources/cubedb/mcu/IP/RCC-*rcc_v1_0_Modes.xml'):
ff = removeprefix(f, 'sources/cubedb/mcu/IP/RCC-')
ff = removesuffix(ff, '_rcc_v1_0_Modes.xml')
ff = removesuffix(ff, '-rcc_v1_0_Modes.xml')
chip_clocks = {}
r = xmltodict.parse(open(f, 'rb'))
for ref in r['IP']['RefParameter']:
name = ref['@Name']
if name.startswith("APB") and name.endswith("Freq_Value") and not name.endswith("TimFreq_Value") and '@IP' in ref:
name = removesuffix(name, "Freq_Value")
peripherals = ref['@IP']
peripherals = peripherals.split(",")
for p in peripherals:
chip_clocks[p] = name
clocks[ff] = chip_clocks
peripheral_to_clock = {}
@ -1153,26 +1035,38 @@ def parse_rcc_regs():
family_clocks = {}
with open(f, 'r') as yaml_file:
y = yaml.load(yaml_file)
for (key, body) in y.items():
if 'SMENR' in key: continue
if key.startswith("fieldset/A") and key.endswith("ENR"):
clock = removesuffix(key, "ENR")
clock = removeprefix(clock, "fieldset/")
clock = removesuffix(clock, "L")
clock = removesuffix(clock, "H")
for field in body['fields']:
if field['name'].endswith('EN'):
peri = removesuffix(field['name'], 'EN')
family_clocks[peri] = clock
for (key, body) in y.items():
if m := re.match('^fieldset/(A[PH]B\d?)[LH]?ENR\d?$', key):
reg = removeprefix(key, 'fieldset/')
clock = m.group(1)
for field in body['fields']:
if field['name'].endswith('EN'):
peri = removesuffix(field['name'], 'EN')
regs = {
'enable': OrderedDict({
'register': reg,
'field': field['name'],
})
}
if rstr := y[key.replace('ENR', 'RSTR')]:
if field := next(filter(lambda f: f['name'] == f'{peri}RST', rstr['fields']), None):
regs['reset'] = OrderedDict({
'register': reg.replace('ENR', 'RSTR'),
'field': f'{peri}RST',
})
family_clocks[peri] = {
'clock': clock,
'registers': regs
}
peripheral_to_clock['rcc_' + ff + '/RCC'] = family_clocks
def match_peri_clock(rcc_block, peri_name):
if rcc_block in peripheral_to_clock:
family_clocks = peripheral_to_clock[rcc_block]
if peri_name in family_clocks:
return family_clocks[peri_name]
# print("found no clock for ", peri_name)
if res := peripheral_to_clock[rcc_block].get(peri_name):
return res
if peri_name.endswith("1"):
return match_peri_clock(rcc_block, removesuffix(peri_name, "1"))
return None
@ -1339,5 +1233,4 @@ parse_rcc_regs()
parse_documentations()
parse_dma()
parse_gpio_af()
parse_clocks()
parse_chips()