diff --git a/data/registers/adc_f1.yaml b/data/registers/adc_f1.yaml new file mode 100644 index 0000000..ee9c98f --- /dev/null +++ b/data/registers/adc_f1.yaml @@ -0,0 +1,402 @@ +--- +block/ADC: + description: Analog-to-digital converter + items: + - name: SR + description: status register + byte_offset: 0 + fieldset: SR + - name: CR1 + description: control register 1 + byte_offset: 4 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 8 + fieldset: CR2 + - name: SMPR1 + description: sample time register 1 + byte_offset: 12 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 16 + fieldset: SMPR2 + - name: JOFR + description: injected channel data offset register x + array: + len: 4 + stride: 4 + byte_offset: 20 + fieldset: JOFR + - name: HTR + description: watchdog higher threshold register + byte_offset: 36 + fieldset: HTR + - name: LTR + description: watchdog lower threshold register + byte_offset: 40 + fieldset: LTR + - name: SQR1 + description: regular sequence register 1 + byte_offset: 44 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 48 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 52 + fieldset: SQR3 + - name: JSQR + description: injected sequence register + byte_offset: 56 + fieldset: JSQR + - name: JDR + description: injected data register x + array: + len: 4 + stride: 4 + byte_offset: 60 + access: Read + fieldset: JDR + - name: DR + description: regular data register + byte_offset: 76 + access: Read + fieldset: DR +fieldset/CR1: + description: control register 1 + fields: + - name: AWDCH + description: Analog watchdog channel select bits + bit_offset: 0 + bit_size: 5 + - name: EOCIE + description: Interrupt enable for EOC + bit_offset: 5 + bit_size: 1 + - name: AWDIE + description: Analog watchdog interrupt enable + bit_offset: 6 + bit_size: 1 + - name: JEOCIE + description: Interrupt enable for injected channels + bit_offset: 7 + bit_size: 1 + - name: SCAN + description: Scan mode + bit_offset: 8 + bit_size: 1 + - name: AWDSGL + description: Enable the watchdog on a single channel in scan mode + bit_offset: 9 + bit_size: 1 + - name: JAUTO + description: Automatic injected group conversion + bit_offset: 10 + bit_size: 1 + - name: DISCEN + description: Discontinuous mode on regular channels + bit_offset: 11 + bit_size: 1 + - name: JDISCEN + description: Discontinuous mode on injected channels + bit_offset: 12 + bit_size: 1 + - name: DISCNUM + description: Discontinuous mode channel count + bit_offset: 13 + bit_size: 3 + - name: DUALMOD + description: Dual mode selection + bit_offset: 16 + bit_size: 4 + enum: DUALMOD + - name: JAWDEN + description: Analog watchdog enable on injected channels + bit_offset: 22 + bit_size: 1 + - name: AWDEN + description: Analog watchdog enable on regular channels + bit_offset: 23 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: ADON + description: A/D Converter ON / OFF + bit_offset: 0 + bit_size: 1 + - name: CONT + description: Continuous conversion + bit_offset: 1 + bit_size: 1 + - name: CAL + description: A/D Calibration + bit_offset: 2 + bit_size: 1 + - name: RSTCAL + description: Reset calibration + bit_offset: 3 + bit_size: 1 + - name: DMA + description: Direct memory access mode (for single ADC mode) + bit_offset: 8 + bit_size: 1 + - name: ALIGN + description: Data alignment + bit_offset: 11 + bit_size: 1 + - name: JEXTSEL + description: External event select for injected group + bit_offset: 12 + bit_size: 3 + enum: EXTSEL + - name: JEXTTRIG + description: External trigger conversion mode for injected channels + bit_offset: 15 + bit_size: 1 + - name: EXTSEL + description: External event select for regular group + bit_offset: 17 + bit_size: 3 + enum: EXTSEL + - name: EXTTRIG + description: External trigger conversion mode for regular channels + bit_offset: 20 + bit_size: 1 + - name: JSWSTART + description: Start conversion of injected channels + bit_offset: 21 + bit_size: 1 + enum_write: JSWSTARTW + - name: SWSTART + description: Start conversion of regular channels + bit_offset: 22 + bit_size: 1 + enum_write: SWSTARTW + - name: TSVREFE + description: Temperature sensor and VREFINT enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: regular data register + fields: + - name: DATA + description: Regular data + bit_offset: 0 + bit_size: 16 + - name: ADC2DATA + description: ADC2 data + bit_offset: 16 + bit_size: 16 +fieldset/HTR: + description: watchdog higher threshold register + fields: + - name: HT + description: Analog watchdog higher threshold + bit_offset: 0 + bit_size: 12 +fieldset/JDR: + description: injected data register x + fields: + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 +fieldset/JOFR: + description: injected channel data offset register x + fields: + - name: JOFFSET + description: Data offset for injected channel x + bit_offset: 0 + bit_size: 12 +fieldset/JSQR: + description: injected sequence register + fields: + - name: JSQ + description: 1st conversion in injected sequence + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: JL + description: Injected sequence length + bit_offset: 20 + bit_size: 2 +fieldset/LTR: + description: watchdog lower threshold register + fields: + - name: LT + description: Analog watchdog lower threshold + bit_offset: 0 + bit_size: 12 +fieldset/SMPR1: + description: sample time register 1 + fields: + - name: SMP + description: Channel x sample time selection + bit_offset: 0 + bit_size: 3 + array: + len: 8 + stride: 3 + enum: SAMPLE_TIME +fieldset/SMPR2: + description: sample time register 2 + fields: + - name: SMP + description: Channel 0 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SAMPLE_TIME +fieldset/SQR1: + description: regular sequence register 1 + fields: + - name: SQ + description: 13th to 16th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: L + description: Regular channel sequence length + bit_offset: 20 + bit_size: 4 +fieldset/SQR2: + description: regular sequence register 2 + fields: + - name: SQ + description: 7th to 12th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 +fieldset/SQR3: + description: regular sequence register 3 + fields: + - name: SQ + description: 1st to 6th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 +fieldset/SR: + description: status register + fields: + - name: AWD + description: Analog watchdog flag + bit_offset: 0 + bit_size: 1 + - name: EOC + description: Regular channel end of conversion + bit_offset: 1 + bit_size: 1 + - name: JEOC + description: Injected channel end of conversion + bit_offset: 2 + bit_size: 1 + - name: JSTRT + description: Injected channel start flag + bit_offset: 3 + bit_size: 1 + - name: STRT + description: Regular channel start flag + bit_offset: 4 + bit_size: 1 +enum/DUALMOD: + bit_size: 4 + variants: + - name: Independent + description: Independent mode. + value: 0 + - name: RegularInjected + description: Combined regular simultaneous + injected simultaneous mode + value: 1 + - name: RegularAlternateTrigger + description: Combined regular simultaneous + alternate trigger mode + value: 2 + - name: InjectedFastInterleaved + description: Combined injected simultaneous + fast interleaved mode + value: 3 + - name: InjectedSlowInterleaved + description: Combined injected simultaneous + slow Interleaved mode + value: 4 + - name: Injected + description: Injected simultaneous mode only + value: 5 + - name: Regular + description: Regular simultaneous mode only + value: 6 + - name: FastInterleaved + description: Fast interleaved mode only + value: 7 + - name: SlowInterleaved + description: Slow interleaved mode only + value: 8 + - name: AlternateTrigger + description: Alternate trigger mode only + value: 9 +enum/EXTSEL: + bit_size: 3 + variants: + - name: TIM1TRGO + description: Timer 1 TRGO event + value: 0 + - name: TIM1CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3CC4 + description: Timer 3 CC4 event + value: 4 + - name: TIM4TRGO + description: Timer 4 TRGO event + value: 5 + - name: TIM8CC4 + description: EXTI line 15/Timer 8 CC4 event + value: 6 + - name: SWSTART + description: SWSTART + value: 7 +enum/SAMPLE_TIME: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 cycles + value: 0 + - name: Cycles7_5 + description: 7.5 cycles + value: 1 + - name: Cycles13_5 + description: 13.5 cycles + value: 2 + - name: Cycles28_5 + description: 28.5 cycles + value: 3 + - name: Cycles41_5 + description: 41.5 cycles + value: 4 + - name: Cycles55_5 + description: 55.5 cycles + value: 5 + - name: Cycles71_5 + description: 71.5 cycles + value: 6 + - name: Cycles239_5 + description: 239.5 cycles + value: 7